JP5487590B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a high electron mobility transistor (HEMT) using a compound semiconductor, a manufacturing method thereof, and the like.

  In recent years, development of GaN field effect transistors (FETs) such as GaN HEMTs using a heterojunction between a GaN layer and an AlGaN layer has been active. In such a GaN-based FET, the GaN layer functions as an electron transit layer. Since GaN has a wide band gap, a high breakdown electric field strength, and a high saturation electron velocity, it is very promising as a material for devices that can easily obtain good high-frequency characteristics and can operate at high voltage and high output.

  FIG. 1 is a cross-sectional view showing a conventional GaN-based FET. As shown in FIG. 1, in a conventional GaN-based FET, a buffer layer 102a, an electron transit layer 102b, and an electron supply layer 102c are formed on a semi-insulating SiC substrate 101 by crystal growth. The buffer layer 102a, the electron transit layer 102b, and the electron supply layer 102c are made of a compound semiconductor. A gate electrode 106 is formed on the electron supply layer 102c, and a source electrode 104 and a drain electrode 105 are formed with the gate electrode 106 interposed therebetween.

  Instead of the semi-insulating SiC substrate 101, a sapphire substrate or a silicon substrate may be used.

  However, the semi-insulating SiC substrate has a problem that the price is remarkably high compared to other substrates. The sapphire substrate has a large difference in lattice constant between the compound semiconductor layer grown on the sapphire substrate, the compound semiconductor layer is liable to cause defects, the leakage current of the semiconductor device increases, and the breakdown voltage decreases. There is a point. The silicon substrate has a problem that the high frequency characteristics of the semiconductor device are lowered due to high conductivity.

JP 2006-216671 A JP 2007-59928 A JP 2006-24927 A

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can obtain good high-frequency characteristics without using a semi-insulating SiC substrate.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

The semi-conductor device, a conductive substrate, a compound semiconductor layer provided on the substrate, the compound semiconductor layer above the formed source electrode, the drain electrode, and a gate electrode, is provided . An opening exposing the compound semiconductor layer on the substrate below the source electrode, the drain electrode, and the gate electrode is provided from the whole below the source electrode to the whole below the drain electrode. In the opening, a member made of one selected from SiC, AlN, GaN, graphite, and carbon nanotubes is provided.

The manufacturing method of a semiconductor device, the conductive substrate on which a compound semiconductor layer, then, the source electrode above the compound semiconductor layer, the drain electrode, and forming a gate electrode. Next, an opening that exposes the compound semiconductor layer on the substrate below the source electrode, the drain electrode, and the gate electrode is formed from the whole below the source electrode to the whole below the drain electrode, and A member made of one selected from SiC, AlN, GaN, graphite, and carbon nanotubes is formed in the opening.

  According to the above semiconductor device or the like, good high frequency characteristics can be obtained without using an expensive semi-insulating SiC substrate as the substrate.

(Reference example)
It is conceivable to use a conductive SiC substrate that is cheaper than a semi-insulating SiC substrate. However, since the conductivity of the conductive SiC substrate is as high as that of the silicon substrate, there is a problem that the high frequency characteristics of the semiconductor device are lowered. As shown in FIG. 2 (a), when the conductive SiC substrate 111 is used instead of the semi-insulating SiC substrate 101, there are large parasitic resistances and parasitic capacitances, so the high frequency characteristics are low. It will end up.

  Therefore, as shown in FIG. 2B, it is conceivable to reduce the parasitic resistance and the parasitic capacitance by providing a thick AlN layer as the high resistance layer 112 between the conductive SiC substrate 111 and the buffer layer 102a.

  However, it is extremely difficult to form the thick high-resistance layer 112 while maintaining its crystalline state in good condition. Further, when the thick high resistance layer 112 is formed, the conductive SiC substrate 111 may be warped or cracked due to stress.

(First embodiment)
Next, a first embodiment will be described. FIG. 3 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the first embodiment.

In the first embodiment, as shown in FIG. 3, for example, a compound semiconductor region 2 is formed on a conductive SiC substrate 1. The thickness of the conductive SiC substrate 1 is, for example, several hundred μm. The compound semiconductor region 2 includes a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a surface layer 2d that are sequentially stacked. The buffer layer 2a and the electron transit layer 2b are, for example, GaN layers (i-GaN layers) that are not intentionally doped with impurities, and their total thickness is about 3 μm. Buffer layer 2a prevents the propagation of lattice defects existing on the surface of conductive SiC substrate 1 to electron transit layer 2b. The electron supply layer 2c is, for example, an n-type Al _0.25 Ga _0.75 N layer (n-Al _0.25 Ga _0.75 N layer) or an undoped AlGaN layer, and has a thickness of about 20 nm. The surface layer 2d is, for example, an n-type GaN layer (n-GaN layer), and has a thickness of 10 nm or less (for example, 5 nm). An Al _0.25 Ga _0.75 N layer (thickness: about 3 nm) that is not intentionally doped with impurities may be provided between the electron transit layer 2b and the electron supply layer 2c. Further, the ratio of Al and Ga in each AlGaN layer is not particularly limited.

  The compound semiconductor region 2 is provided with an element isolation region 3 that defines an active region. Opening 1a is formed in conductive SiC substrate 1 so as to be aligned with the active region. The area ratio between the active region and the element isolation region 3 is about 1: 5 to 1:10.

  The surface layer 2d is formed with two openings that expose the electron supply layer 2c, and an ohmic electrode is formed as the source electrode 4 or the drain electrode 5 in each of the openings. Further, a silicon nitride film 10 covering the surface layer 2d, the source electrode 4 and the drain electrode 5 is formed. The thickness of the silicon nitride film 10 is, for example, about 50 nm. In the silicon nitride film 10, an opening 10 a is formed at a position approximately in the middle between the source electrode 4 and the drain electrode 5. A gate electrode 6 in contact with the surface layer 2d through the opening 10a is formed on the silicon nitride film 10.

  In the first embodiment, since the conductive SiC substrate 1 does not exist below the active region of the compound semiconductor region 2, the parasitic resistance and the parasitic capacitance are small, and good high frequency characteristics can be obtained. Conductive SiC substrate 1 is less expensive than a semi-insulating SiC substrate. Furthermore, when the conductive SiC substrate 1 is not present at all, the thickness of the semiconductor device itself is extremely thin, and handling (handling) becomes difficult. However, in this embodiment, the conductive material is provided below the element isolation region 3. Since the SiC substrate 1 exists, it can be handled easily.

  In addition, if a flip chip structure is employed, it is possible to obtain good heat dissipation characteristics.

  Next, a method for manufacturing the GaN-based HEMT according to the first embodiment will be described. 4A to 4I are cross-sectional views illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment in the order of steps.

  First, as shown in FIG. 4A, a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a surface are formed on a conductive SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). The layer 2d is epitaxially grown in this order. The buffer layer 2a, the electron transit layer 2b, the electron supply layer 2c, and the surface layer 2d are included in the compound semiconductor region 2.

  Next, as illustrated in FIG. 4B, an element isolation region 3 that defines an active region is formed in the compound semiconductor region 2 by selectively implanting Ar toward the compound semiconductor region 2.

Thereafter, a resist pattern is formed on the compound semiconductor region 2 to open a region where the source electrode is to be formed and a region where the drain electrode is to be formed. Subsequently, by using the resist pattern as a mask, dry etching using an inert gas and a chlorine-based gas such as Cl ₂ gas is performed on the surface layer 2d, so that the surface layer 2d has 2 Openings are formed. Regarding the depth of the opening, a part of the surface layer 2d may be left, or a part of the electron supply layer 2c may be removed. That is, the depth of the opening does not need to match the thickness of the surface layer 2d.

  Thereafter, as shown in FIG. 4C, the source electrode 4 is formed in one opening, and the drain electrode 5 is formed in the other opening. In forming the source electrode 4 and the drain electrode 5, for example, first, a Ti layer is formed by an evaporation method, and an Al layer is formed thereon by an evaporation method. The thickness of the Ti layer is about 20 nm, and the thickness of the Al layer is about 200 nm. Then, the resist pattern used for forming the opening is removed. That is, in forming the source electrode 4 and the drain electrode 5, for example, vapor deposition and lift-off techniques are used. Thereafter, a heat treatment at about 550 ° C. is performed to make ohmic contact between the electron supply layer 2 c and the source electrode 4 and the drain electrode 5.

  Next, as shown in FIG. 4D, a silicon nitride film 10 that covers the source electrode 4 and the drain electrode 5 is formed on the entire surface of the compound semiconductor region 2 by a plasma chemical vapor deposition (CVD) method.

Thereafter, as shown in FIG. 4E, a resist pattern 21 having an opening 21a aligned with a region where the opening 10a is to be formed is formed on the silicon nitride film 10. Then, an opening 10a is formed in the silicon nitride film 10 by performing dry etching using the resist pattern 21 as a mask. In this dry etching, for example, SF ₆ gas is used. Subsequently, the resist pattern 21 is removed.

  Thereafter, as shown in FIG. 4F, the lower resist pattern 22 having an opening 22a that matches the region where the gate electrode 6 is to be formed and the upper resist pattern 23 having an opening 23a narrower than the opening 22a are silicon nitrided. It is formed on the film 10.

  In forming the lower layer resist pattern 22 and the upper layer resist pattern 23, first, an alkali-soluble resin (trade name PMGI: manufactured by US Microchem Co., Ltd.) is applied on the silicon nitride film 10 by, for example, spin coating, and heat treatment is performed. By performing, a resist film is formed. Furthermore, a photosensitive resist agent (trade name PFI32-A8: manufactured by Sumitomo Chemical Co., Ltd.) is applied by, for example, a spin coat method, and heat treatment is performed to form a resist film. Next, an opening 23a having a width of about 0.8 μm is formed in the upper resist film by ultraviolet exposure. As a result, an upper resist pattern 23 having an opening 23a is obtained. Thereafter, using the upper resist pattern 23 as a mask, the lower resist film is wet etched using an alkali developer. As a result, the lower resist pattern 22 having the opening 22a is obtained. By these treatments, as shown in FIG. 4F, a multi-layer resist having a ridge structure is obtained.

  After the formation of the lower layer resist pattern 22 and the upper layer resist pattern 23, the gate electrode 6 is formed in the opening 22a as shown in FIG. 4F. In forming the gate electrode 6, for example, a Ni layer is formed by a vapor deposition method, and an Au layer is formed thereon by a vapor deposition method. The thickness of the Ni layer is about 10 nm, and the thickness of the Au layer is about 300 nm.

  Next, as shown in FIG. 4G, the resist patterns 22 and 23 are removed using a heated organic solvent. That is, even in the formation of the gate electrode 6, for example, vapor deposition and lift-off techniques are used.

  Thereafter, as shown in FIG. 4H, a surface protective layer 25 is formed on the entire surface of the conductive SiC substrate 1, and the front and back of the conductive SiC substrate 1 are reversed. Subsequently, a resist pattern or a metal mask pattern that covers a region overlapping the element isolation region 3 in a plan view of the back surface of the conductive SiC substrate 1 and exposes a region overlapping the active region is formed, and the resist pattern is used as a mask to conduct electricity. Etching of the reactive SiC substrate 1 forms the opening 1a. In this etching, for example, a gas containing fluorine gas is used.

  Next, as shown in FIG. 4I, the front and back of the conductive SiC substrate 1 are reversed, and the surface protective layer 25 is removed. Thereafter, wiring (not shown) or the like is formed as necessary to complete the GaN-based HEMT.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 5 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the second embodiment.

  In the second embodiment, as shown in FIG. 5, a heat dissipation member 15 that is in contact with the compound semiconductor region 2 through the opening 1 a is provided. The heat conductivity of the heat radiating member 15 is preferably 150 W / m · K or more. Examples of the material of the heat radiating member 15 include SiC, AlN, GaN, graphite, and carbon nanotubes. Other configurations are the same as those of the first embodiment.

  According to such a second embodiment, good heat dissipation characteristics can be obtained without employing a flip chip structure. For example, better heat dissipation characteristics can be obtained than when a sapphire substrate is used.

  In addition, what is necessary is just to form the thermal radiation member 15 in the state in which the surface protective layer 25 was formed, for example after formation of the opening part 1a.

(Third embodiment)
Next, a third embodiment will be described. FIG. 6 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the third embodiment. While the first embodiment is a Schottky gate type transistor, this embodiment is a MIS (metal insulator semiconductor) gate type transistor. That is, as shown in FIG. 6, the opening 10 a is not formed in the silicon nitride film 10, and the gate electrode 16 is provided on the silicon nitride film 10 instead of the gate electrode 6. Other configurations are the same as those of the first embodiment.

  Even in such a MIS gate type transistor, the same effect as in the first embodiment can be obtained.

  In order to manufacture the GaN-based HEMT according to the third embodiment, for example, the gate electrode 16 may be formed without forming the opening 10a.

(Fourth embodiment)
Next, a fourth embodiment will be described. 7A and 7B are cross-sectional views showing the structure of a GaN-based HEMT (semiconductor device) according to the fourth embodiment. 7A and 7B show cross sections orthogonal to each other.

  In the present embodiment, there is a conductive SiC substrate 1 below the active region. That is, the processing of the conductive SiC substrate 1 as in the first embodiment is not performed. On the other hand, a high-resistance intrinsic GaN (i-GaN) film 32 is formed below the element isolation region 3 between the conductive SiC substrate 1 and the buffer layer 2a. For this reason, a cavity 34 is provided between the conductive SiC substrate 1 and the compound semiconductor region 2 below the active region, and the conductive SiC substrate 1 and the compound semiconductor region 2 are separated from each other. That is, the i-GaN film 32 supports the compound semiconductor region 2 on the conductive SiC substrate 1 as a support member. The height of the cavity 34 is preferably 2 μm or less, for example, about 1 μm. Other configurations are the same as those of the first embodiment.

  Also according to the fourth embodiment, the parasitic resistance and the parasitic capacitance are small as in the first embodiment, and a good high frequency characteristic can be obtained.

  Next, a method for manufacturing a GaN-based HEMT according to the fourth embodiment will be described. 8 to 14 are cross-sectional views showing a method of manufacturing the GaN-based HEMT according to the fourth embodiment in the order of steps. 8 to 14, (a) is a plan view, (b) is a cross-sectional view taken along the line II in (a), and (c) is taken along the line II-II in (a). FIG.

  First, as shown in FIG. 8, the insulating film 31 is formed as a dummy film on the conductive SiC substrate 1 by, for example, a plasma CVD method or an organic metal CVD (MOCVD) method. Next, a resist pattern is formed on the insulating film 31 so as to cover the region where the active region is to be formed and to expose the region where the element isolation region 3 is to be formed. Then, by etching the insulating film 31 using this resist pattern, the insulating film 31 is left in a region where an active region is to be formed.

  Thereafter, as shown in FIG. 9, a high-resistance intrinsic GaN (i-GaN) film 32 is formed on the surface of the conductive SiC substrate 1 by, for example, the MOVPE method or the molecular beam epitaxy (MBE) method. To do.

  Subsequently, as shown in FIG. 10, a planarization process is performed to make the thickness of the insulating film 31 uniform and the thickness of the surrounding i-GaN film 32.

  Next, as shown in FIG. 11, the buffer layer 2a, the electron transit layer 2b, the electron supply layer 2c, and the surface layer 2d are formed on the insulating film 31 and the i-GaN film 32 as in the first embodiment. . Furthermore, as in the first embodiment, the element isolation region 3 is formed above the i-GaN film 32.

  Thereafter, as shown in FIG. 12, trenches 33 are formed in the element isolation region 3, the underlying buffer layer 2 a, and the i-GaN film 32 along a pair of sides of the active region facing each other.

  Subsequently, as shown in FIG. 13, the insulating film 31 is removed by impregnating the insulating film 31 with an etching solution (hydrofluoric acid or the like) from the groove 33. As a result, a cavity 34 is formed between conductive SiC substrate 1 and compound semiconductor region 2.

  Next, as shown in FIG. 14, the source electrode 4, the drain electrode 5, the gate electrode 6, and the silicon nitride film 10 are formed in the same manner as in the first embodiment. Then, if necessary, wiring (not shown) or the like is formed to complete the GaN-based HEMT. The cavity 34 may be formed after the source electrode 4 and the like are formed.

You may combine such 4th Embodiment and 3rd Embodiment. That is, a MIS gate type transistor may be employed in the fourth embodiment. Furthermore, other materials may be used as the material of the substrate, but it is preferable to use a conductive substrate having a resistivity of 1 × 10 ⁵ Ω · cm or less.

  Further, the surface layer 2d and / or the silicon nitride film 10 may not be provided. Further, the opening 1a in the first to third embodiments does not have to completely correspond to the active region. That is, there may be a deviation between the opening 1a and the active region in plan view. Moreover, the depth of the opening 1a does not need to match the thickness of the conductive SiC substrate 1, and the opening 1a may enter the buffer layer 2a. Conversely, conductive SiC substrate 1 may remain at the bottom of opening 1a.

  Further, the cavity 34 in the fourth embodiment does not need to completely correspond to the active region, and there may be a gap between the cavity 34 and the active region in plan view.

It is sectional drawing which shows the conventional GaN-type FET. It is sectional drawing which shows the reference example using a conductive SiC substrate. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 4B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4A. 4B is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4B. 4C is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4C. 4D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4D. FIG. 4E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4E. 4F is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4F. FIG. 4G is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4G. 4H is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4H. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 3rd Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 4th Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 4th Embodiment. FIG. 9 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 8. FIG. 10 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 9. FIG. 11 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 10. FIG. 12 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 11. FIG. 13 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 12. FIG. 14 is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 13.

Explanation of symbols

1: Conductive SiC substrate 1a: Opening 2: Compound semiconductor region 3: Element isolation region 4: Source electrode 5: Drain electrode 6, 16: Gate electrode 15: Heat radiation member 34: Cavity

Claims (4)

A conductive substrate;
A compound semiconductor layer provided on the substrate;
A source electrode, a drain electrode, and a gate electrode formed above the compound semiconductor layer;
Have
An opening for exposing the compound semiconductor layer to the substrate below the source electrode, the drain electrode, and the gate electrode is provided from the whole below the source electrode to the whole below the drain electrode, and A semiconductor device characterized in that a member made of one selected from SiC, AlN, GaN, graphite, and carbon nanotube is provided in the opening. The semiconductor device according to claim 1, wherein the substrate is a conductive SiC substrate. Forming a compound semiconductor layer on a conductive substrate;
Forming a source electrode, a drain electrode, and a gate electrode above the compound semiconductor layer;
Forming an opening that exposes the compound semiconductor layer on the substrate below the source electrode, the drain electrode, and the gate electrode from the whole below the source electrode to the whole below the drain electrode;
Forming a member made of one selected from SiC, AlN, GaN, graphite and carbon nanotubes in the opening;
A method for manufacturing a semiconductor device, comprising: The method for manufacturing a semiconductor device according to claim 3 , wherein a conductive SiC substrate is used as the substrate.

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