KR101598200B1 - III-V semiconductor compound device package and method of manufacturing the same - Google Patents

Abstract

A semiconductor device package according to the present invention includes a substrate on which an active element region and a passive element region are defined; A semiconductor element formed on the active element region of the substrate; And a capacitor formed on the passive element region of the substrate, the semiconductor element comprising: a gate electrode including a body portion and a head portion on the body portion; a source electrode spaced apart from the gate electrode, And a passivation structure surrounding the gate electrode, the capacitor having a lower electrode, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer, wherein the passivation structure and the capacitor dielectric layer Includes the same material.

Description

III-V compound semiconductor device package and a method of manufacturing the same

The present invention relates to a III-V semiconductor device package and a manufacturing method thereof, and more particularly, to a Pseudomorphic high electron mobility transistor device (PHEMT) package and a method of manufacturing the same.

With the development of information and communication technology, there is a growing demand for high frequency, high temperature, and high power electronic devices. Particularly, various studies are being conducted on power devices capable of controlling high power. In the case of the amorphous high electron mobility transistor device using the heterojunction structure of the III-V compound semiconductor series, since the band-discontinuity at the junction interface is large, a high concentration of electrons can be concentrated at the junction interface, The electron mobility can be further increased. Therefore, a variety of researches have been conducted on transistors of III-V family semiconductor series using a heterojunction structure having high breakdown voltage, high sheet carrier density, high saturation current and the like.

However, in general, a III-V compound semiconductor semiconductor device uses an insulating substrate such as sapphire having a low thermal conductivity, and the driving voltage of the power device employing the insulating substrate is high, so that the heat radiation characteristic and the withstand voltage Need to improve.

A technical object of the present invention is to provide a III-V compound semiconductor device package having excellent heat dissipation characteristics and withstanding voltage resistance.

The technical problem to be solved by the present invention is to provide a method of manufacturing a III-V compound semiconductor device package having excellent heat dissipation characteristics and withstanding voltage resistance.

According to an aspect of the present invention, there is provided a semiconductor device package comprising: a substrate having an active device region and a passive device region defined therein; A semiconductor element formed on the active element region of the substrate; And a capacitor formed on the passive element region of the substrate, the semiconductor element comprising: a gate electrode including a body portion and a head portion on the body portion; a source electrode spaced apart from the gate electrode, And a passivation structure surrounding the gate electrode, the capacitor having a lower electrode, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer, wherein the passivation structure and the capacitor dielectric layer Includes the same material.

In exemplary embodiments, the gate electrode may have a T shape.

In exemplary embodiments, the width of the head portion may be greater than the width of the body portion.

In exemplary embodiments, the passivation structure may include: a first passivation layer surrounding a sidewall of the body portion of the gate electrode; And a second passivation layer formed on the first passivation layer and surrounding a side wall and an upper surface of the head portion of the gate electrode.

In exemplary embodiments, the capacitor dielectric layer may comprise the same material as the second passivation layer.

In exemplary embodiments, it may further comprise a resistor formed on the passive element region of the substrate.

In exemplary embodiments, the source electrode is formed on a front side of the substrate, and a first via hole penetrating the substrate from a rear face of the substrate is formed so as to overlap with the source electrode. And a source ground via electrically connected to the source electrode on the inner wall of the first via hole.

In the exemplary embodiments, a second via hole is formed through the substrate from the backside of the substrate to overlap with the capacitor, and a heat dissipation layer electrically connected to the lower electrode of the capacitor on the inner wall of the second via hole Vias. ≪ / RTI >

In exemplary embodiments, the heat sink vias and the source ground vias may comprise the same material.

In exemplary embodiments, it may further comprise a source ground layer formed on the backside of the substrate and connected to the source ground vias.

A III-V group compound semiconductor device package according to the present invention comprises a semiconductor element mounted on an active element region of a substrate, the element including a monomorphic high electron mobility transistor, a passive element such as a capacitor mounted on a passive element region of the substrate, So that a compact semiconductor device package can be realized. Also, heat radiation vias and source ground vias are provided to improve the heat dissipation characteristics and withstand voltage.

1 is a cross-sectional view illustrating a III-V compound semiconductor device package in accordance with exemplary embodiments of the present invention.
2A to 2F are cross-sectional views illustrating a method of manufacturing a gate electrode according to exemplary embodiments of the present invention.
3A-3H are cross-sectional views illustrating a method of fabricating a III-V compound semiconductor device package in accordance with exemplary embodiments of the present invention.
4 to 6 are graphs showing electrical characteristics of the III-V group compound semiconductor device package according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. The scope of technical thought is not limited to the following examples. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the scope of the invention to those skilled in the art. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items. The same reference numerals denote the same elements at all times. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the technical spirit of the present invention is not limited by the relative size or spacing depicted in the accompanying drawings.

1 is a cross-sectional view illustrating a III-V compound semiconductor device package 1000 in accordance with exemplary embodiments of the present invention.

Referring to FIG. 1, a III-V compound semiconductor device package 1000 may include a semiconductor device 100, a resistor 200, and a capacitor 300 formed on a substrate 110.

The active element region I and the passive element region II may be defined in the substrate 110. [ The semiconductor device 100 may be formed in the active device region I and the resistor 200 and the capacitor 300 may be formed in the passive device region II. Passive elements such as an inductor necessary for driving the semiconductor device 100 may be further formed in the passive element region II in addition to the resistor 200 and the capacitor 300. [

An element isolation region 140 may be formed in the substrate 110. The element isolation region 140 may be formed in a portion of the active element region I to define an active region (not shown) in which the semiconductor element 100 is to be formed. For example, an element isolation region 140 is formed in the edge portion of the active element region I and the passive element region II in the upper surface of the substrate 110, and a substrate (not shown) in which the element isolation region 140 is not formed The semiconductor device 100 may be disposed on the surface of the semiconductor device 100.

Hereinafter, the semiconductor element 100 formed in the active element region I will be described.

The semiconductor device 100 includes a first buffer layer 112 formed on a substrate 110, a second buffer layer 114, a channel layer 122, a gate contact layer 124, an etch stop layer 130, a capping layer 132, a ohmic layer 134, a gate electrode 150, a passivation structure 160, a source electrode 172, and a drain electrode 174. Further, a source ground electrode structure 180 connected to the source electrode 172 of the semiconductor device 100 may be further formed.

The substrate 110 may include a gallium arsenide substrate, a silicon carbide substrate, a silicon substrate, an aluminum nitride substrate, a sapphire substrate, or the like. In the exemplary embodiments, the substrate 110 may comprise a semi-insulating gallium arsenide substrate. However, the type of the substrate 110 is not limited thereto.

A first buffer layer 112 and a second buffer layer 114 may be sequentially stacked on the substrate 110. The first and second buffer layers 112 and 114 prevent crystal quality deterioration due to a defect such as a misfit dislocation due to a difference in lattice constant between the substrate 110 material and the channel layer 122 Can play a role.

The first buffer layer 112 may be a superlattice layer. For example, when the substrate 110 comprises a semi-insulating gallium arsenide substrate, the first buffer layer 112 may be a superlattice layer comprising gallium arsenide.

The second buffer layer 114 may be formed of a stacked structure of a first layer (not shown) containing gallium arsenide and a second layer (not shown) containing aluminum gallium arsenide. The second buffer layer 114 may extend in a vertical direction from the bottom surface of the second buffer layer 114 in contact with the first buffer layer 112 to the top surface of the second buffer layer 114 in contact with the channel layer 122. In this case, And a plurality of layers (not shown) in which the content of aluminum is changed along the thickness direction of the substrate. For example, along the vertical direction from the bottom surface to the top surface of the second buffer layer 114, the content of aluminum from gallium arsenide to a specific composition of aluminum gallium arsenide (Al _1-x Ga _x As, 0 <x <1) That is, x may increase sequentially.

Although not shown in FIG. 1, a spacer (not shown) may be optionally formed between the second buffer layer 114 and the channel layer 122.

The channel layer 122 and the gate contact layer 124 may be sequentially formed on the second buffer layer 114. In the exemplary embodiments, the channel layer 122 may comprise indium gallium arsenide and the gate contact layer 124 may comprise n-type aluminum gallium arsenide. In particular, the gate contact layer 124 may be doped with an n-type impurity such as silicon (Si), germanium (Ge), or tin (Sn). A two-dimensional electron gas layer (not shown) may be formed in the channel layer 122 near the interface between the channel layer 122 and the gate contact layer 124 , This 2DEG layer can constitute the channel region of the semiconductor device 100. [

An etch stop layer 130 and a capping layer 132 may be further formed on the gate contact layer 124. The etch stop layer 130 may serve as a protective layer to prevent damage to the underlying channel layer 122 and the gate contact layer 124 in a recessed (not shown) etching process for forming the gate electrode 150 have. In the exemplary embodiments, the etch stop layer 130 may comprise aluminum arsenide. According to exemplary embodiments, the capping layer 132 may comprise n-type gallium arsenide. In addition, the capping layer 132 may be formed of a laminated structure of gallium arsenide and indium gallium arsenide.

A gate electrode 150 may be formed over the gate contact layer 124. The gate electrode 150 is formed to include the body portion 152 and the head portion 154, and may have a T-shape. The body portion 152 may be formed with a predetermined width and thickness in contact with the gate contact layer 124. The head portion 154 may be formed to have a greater width than the body portion 152 above the body portion 152. When the gate electrode 150 is formed to have a T-shape, the area in which the body portion 152 contacts the gate contact layer 124 can be reduced, and the parasitic resistance can be reduced. The width of the head portion 154 is greater than the width of the body portion 152 so that the resistance of the gate electrode 150 can be reduced and the parasitic capacitance of the gate electrode 150 can be reduced. In the case where the vertical cross section of the gate electrode is formed in a rectangular shape, it is difficult to form the gate electrode with a small width in order to reduce the parasitic resistance. However, in the present invention, the width of the gate electrode can be reduced by using the double exposure method. A method of forming the gate electrode 150 having such a shape will be described in detail later with reference to FIGS. 2A to 2F.

The passivation structure 160 may be formed to surround the gate electrode 150. The passivation structure 160 may include a first passivation layer 162 and a second passivation layer 164. The first passivation layer 162 surrounds the sidewalls of the body portion 152 contacting the top of the gate contact layer 124 and the second passivation layer 164 surrounds the body portion 152 on the first passivation layer 162. [ And the head portion 154 may be formed in a shape that surrounds the side wall and the head portion 154. [ The thicknesses of the first passivation layer 162 and the second passivation layer 164 may vary. In the exemplary embodiments, the first and second passivation layers 162 and 164 may comprise silicon oxide, silicon nitride, high dielectric constant materials, and the like. For example, the first and second passivation layers 162 and 164 may comprise the same material or may comprise different materials.

The passivation structure 160 may be formed by depositing a lower gate contact layer 124 and a channel layer 122 to prevent oxidation of the lower gate contact layer 124 and channel layer 122 when exposed or damage by moisture and other contaminants. 122 may be protected. The first passivation layer 162 of the passivation structure 160 covers the sidewalls of the body portion 152 of the gate electrode 150, thereby reducing the contact resistance of the gate electrode 150.

The source electrode 172 and the drain electrode 174 may be formed on the capping layer 132 and spaced apart from each other with the gate electrode 150 therebetween. A source pad 176 and an ohmic layer 134 may be further formed between the source electrode 172 and the capping layer 132. A drain pad 178 may be formed between the drain electrode 174 and the capping layer 132. [ And the ohmic layer 134 may be further formed. The ohmic layer 134 may serve to reduce the contact resistance between the source and drain electrodes 172 and 174 and the gate contact layer 124. For example, the ohmic layer 134 may include AuGe / Au / Ni . &Lt; / RTI &gt;

The source ground electrode structure 180 is formed on the lower surface of the substrate 110, that is, on the opposite surface of the upper surface of the substrate 110 on which the source electrode 172 is formed. The source ground electrode structure 180 may include a source ground via 182 and a source ground layer 184. The source ground vias 182 may be formed on the inner wall of the via hole 181 formed at a predetermined depth from the lower surface of the substrate 110. A source ground layer 184 may be formed on the bottom surface of the substrate 110. Since the via hole 181 is formed to expose the source pad 176 through the substrate 110, the source ground via 182 can be electrically connected to the source electrode 172 through the source pad 176 The source ground layer 184 may be electrically connected to the source electrode 172 through the source ground via 182 and the source pad 176. [ The source ground electrode structure 180 serves as a ground layer connected from the source electrode 172 to the lower surface of the substrate 110 and the source ground layer 184 covers the entire lower surface of the substrate 110 And may act as a heat sink for discharging heat generated in the semiconductor device 100 to the outside of the substrate 110. [

A seed layer 190 may be further formed between the source electrode 172 and the source pad 176 and between the drain electrode 174 and the drain pad 178. [ In exemplary embodiments, the seed layer 190 may be conformally formed to a predetermined thickness along the bottom surface of the source electrode 172 and the drain electrode 174. In addition, the seed layer 190 may be formed to have a predetermined thickness between the source ground electrode structure 180 and the substrate 110.

The above-described semiconductor device 100 may constitute a pseudomorphic high electron mobility transistor (pHEMT) device using indium gallium arsenide as the channel layer 122. In particular, pHEMT devices using indium gallium arsenide can exhibit high breakdown voltage characteristics due to high drain current density and small gate parasitic resistance.

The resistor 200 may be formed on the element isolation region 140 of the passive element region II. The first insulating layer 210 is formed on the element isolation region 140 of the passive element region II and the resistor 200 is formed on the first insulating layer 210 . A conductive pattern 220 is formed on the resistor 200 and the resistor 200 may be electrically connected to the source electrode 172 through the conductive pattern 220. Meanwhile, a second insulating layer 215 may be further formed on the resistor 200.

In the exemplary embodiments, the first and second insulating layers 210 and 215 may comprise the same materials as the first and second passivation layers 162 and 164, respectively. In this case, the first and second insulating layers 210 and 215 may be simultaneously formed on the passive device region II in the process of forming the first and second passivation layers 162 and 164. Alternatively, the first and second insulating layers 210 and 215 may comprise materials different from the first and second passivation layers 162 and 164 materials.

The capacitor 300 may be formed on the element isolation region 140 of the passive element region II. In the exemplary embodiments, the capacitor 300 may include an upper electrode 305, a capacitor dielectric layer 315, and a lower electrode 320. Particularly, a lower electrode 320 is formed on the element isolation region 140 on the passive element region II, a capacitor dielectric film 315 is formed on the lower electrode 320, An electrode 305 may be formed.

In the exemplary embodiments, the upper electrode 305 of the capacitor 300 may comprise the same materials as the materials of the source and drain electrodes 172, 174. In this case, the upper electrode 305 can be simultaneously formed on the passive device region II in the process of forming the source and drain electrodes 172 and 174. [ Alternatively, the upper electrode 305 may comprise a material different from the material of the source and drain electrodes 172, 174.

Alternatively, a via hole 331 may be formed from the bottom of the substrate 110 in the region where the capacitor 300 is formed, and a heat dissipation via 332 may be further formed on the inner wall of the via hole 331. The heat dissipation vias 332 may serve as a heat transfer path for discharging heat generated from the capacitors 300 to the lower surface of the substrate 110. [

The encapsulation layer 192 may be formed on the substrate 110 to cover the semiconductor device 100, the resistor 200, and the capacitor 300. The encapsulation layer 192 may comprise an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicone resin, or epoxy resin. The encapsulation layer 192 can prevent components such as the exposed source and drain electrodes 172 and 174 and the capacitor 300 from being damaged by mechanical shock or moisture from the outside.

The semiconductor device package 1000 according to the present invention can arrange a passive device such as an active device including the semiconductor device 100, a resistor 200, and a capacitor 300 on one substrate 110. Therefore, the package 1000 of a compact size can be realized as compared with a package manufactured by a method in which passive elements are individually manufactured and then mounted on a substrate by using a connecting member such as a wire or a solder ball. The semiconductor device package 1000 according to the present invention includes a source ground electrode structure 180 that electrically connects the source electrode 172 to the lower surface of the substrate 110, can do. Further, by providing the heat radiation vias 332, the semiconductor device package 1000 can have excellent heat radiation characteristics.

2A to 2F are cross-sectional views illustrating a method of manufacturing a gate electrode according to exemplary embodiments of the present invention. This manufacturing method is an exemplary method for manufacturing the gate electrode (150 in FIG. 1) shown in FIG. 1, and may be a method of manufacturing a gate electrode using a double-exposure method in particular.

Referring to FIG. 2A, an epitaxial layer 20 is formed on a substrate 10, and a hard mask layer 30 may be formed on an epitaxial layer 20. The epitaxial layer 20 may be a III-V compound semiconductor layer and may include, for example, aluminum gallium arsenide, indium gallium arsenide, aluminum indium gallium arsenide, and the like. The hardmask layer 30 may comprise an insulating material such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

A photoresist structure 40 formed in a laminated structure of a first material layer 42, a second material layer 44, and a third material layer 46 may be deposited on the hard mask layer 30. The first to third material layers 42, 44, and 46 may each include materials having different optical properties such as light absorptivity. In exemplary embodiments, the first material layer 42 may comprise poly (methylmethacrylate) (PMMA) and the second material layer 44 may comprise polydimethylglutarimide the material of the first to third material layers 42, 44, 46 may comprise ZEP of the manufacturer ZEON, but the third material layer 46 may comprise ZEP of the manufacturer ZEON. But is not limited thereto.

A first exposure mask M1 may be placed on top of the photoresist structure 40 and a first electron beam exposure process S1 may be performed. The electron beam can pass through the first mask opening M1a of the first exposure mask M1 and irradiate the photoresist structure 40. [ For example, using JEOL's JBX6000FS / E, the first exposure step (S1) can be performed with an electron beam acceleration voltage of 50 kV, a probe beam current of 1 nA, and a beam resolution of 50 nm. However, the acceleration voltage and the probe beam current used in the first electron beam exposure process S1 are not limited thereto, and may be appropriately determined in consideration of the light absorptivity of the first to third material layers 42, 44, Can be selected.

Referring to FIG. 2B, the third material layer 46 and the second material layer 44 may be patterned by performing a developing process on the photoresist structure 40 on which the first exposure process S1 has been performed. At this time, the first material layer 42 may not be patterned by the first exposure step S1.

In the exemplary embodiments, since the third material layer 46 and the second material layer 44 have different light absorptions, the patterned widths may be different from each other. For example, the third material layer 46 may be patterned with a width substantially equal to the width of the first mask opening M1a of the first exposure mask M1, and the second material layer 44 may be patterned Can be patterned with a width larger than the width of the mask opening M1a. The second material layer 44 is recessed relative to the patterned third material layer 46 to form a first recessed portion 44 at the boundary of the third material layer 46 and the second material layer 44 40R1 may be formed.

Referring to FIG. 2C, a second exposure mask M2 may be placed on top of the photoresist structure 40, and a second electron beam exposure process S2 may be performed. The electron beam passes through the first mask opening portion M2a of the second exposure mask M2 and can be irradiated to the photoresist structure 40. [

The width of the second mask opening M2a may be less than the width of the first mask opening M1a and the second mask opening M2a may be smaller than the width of the first material layer 42, As shown in FIG. Accordingly, the first material layer 42 can be patterned in the second electron beam exposure step S2.

Referring to FIG. 2D, the first material layer 42 may be patterned by performing a developing process on the photoresist structure 40 on which the second exposure process S2 has been performed. The second recess portion 40R2 may be formed at the patterned portion of the first material layer 42. [

Referring to FIG. 2E, the hard mask layer 30 may be patterned using the photoresist structure 40 as a mask. Accordingly, the hard mask layer 30 can be patterned with a width substantially equal to the patterning width of the first material layer 42. [ The third recess portion 30R1 may be formed in the patterned portion of the hard mask layer 30 and the upper surface of the epitaxial layer 20 may be exposed by the third recess portion 30R1.

In the exemplary embodiments, the width of the third recess portion 30R1 may be formed to be substantially equal to the width of the second recess portion 40R2.

Thereafter, the third material layer 46 may optionally be removed. However, depending on the optical properties of the first to third material layers 42, 44, 46 and the shape of the gate electrode (50 in Figure 2f) to be formed in a subsequent process, the third material layer 46 may not be removed have.

Referring to FIG. 2F, the gate electrode 50 may be formed using the photoresist structure 40 and the hard mask layer 30 as a mask. In the exemplary embodiments, the gate electrode 50 may be formed by an electron beam evaporation method.

In the exemplary embodiments, the first to third recesses 40R1, 40R2, 30R1 formed by patterning the hard mask layer 30 and the first and second material layers 42, A gate electrode 50 filling the inside can be formed. The gate electrode 50 may include a body portion 52 and a head portion 54 above the body portion. The portion of the gate electrode 50 that fills the inside of the second and third recess portions 40R2 and 30R1 is referred to as a body portion 52 and the portion of the gate electrode 50 that fills the inside of the first recess portion 40R1 is referred to as a head portion Can be referred to as &quot; portion 54 &quot;. Therefore, the width of the body portion 52 can be made narrower than the width of the head portion 54. [ The bottom surface of the body portion 52 of the gate electrode 50 may be formed to contact the top surface of the epitaxial layer 20 and the side walls of the body portion 52 may be surrounded by the hard mask layer 30. [ have.

The photoresist structure 40 may then be removed.

By performing the above-described processes, a T-shaped gate electrode 50 can be formed. According to the manufacturing method according to the present embodiment, by using the photoresist structure 40 formed in a laminated structure of the first to third material layers 42, 44, 46 having different optical characteristics, (S1, S2) sequentially. The gate electrode 50 having the body portion 52 having a narrower width than the head portion 54 can be formed in the second exposure process for patterning the body portion 52. [ Patterning can be performed, and the metal lift-off characteristic can be excellent.

3A-3H are cross-sectional views illustrating a method of fabricating a III-V compound semiconductor device package 1000 in accordance with exemplary embodiments of the present invention.

Referring to FIG. 3A, a substrate 110 is defined in which an active element region I and a passive region II are defined. The first buffer layer 112, the second buffer layer 114, the channel layer 122, the gate contact layer 124, the etch stop layer 130 and the capping layer 132 are sequentially formed on the substrate 110 . The layers may be formed on the entire upper surface of the substrate 110, that is, in both the active element region I and the passive region II. Alternatively, the layers may be formed only on the upper surface of the substrate 110 of the active element region I.

In the exemplary embodiments, the first buffer layer 112, the second buffer layer 114, the channel layer 122, the gate contact layer 124, the etch stop layer 130, and the capping layer 132 are formed by epitaxy An epitaxial growth process, or metal organic chemical vapor deposition (MOCVD). Hereinafter, for convenience, the layers are collectively referred to as epitaxial layers (E).

Referring to FIG. 3B, an element isolation region 140 is defined by performing an ion implantation process from an edge portion of the active element region I and an upper surface of the substrate 110 of the passive element region II. The element isolation region 140 can be defined to an edge portion of the active element region I and a predetermined depth in the vertical direction from the upper surface of the epitaxial layers E formed in the passive element region II. The bottom surface of the element isolation region 140 may be formed to be located on a lower level than the bottom surface of the buffer layer 112 (FIG. 3A), so that the active region is connected to the adjacent active region and the element isolation region 140 It can be electrically insulated.

Referring to FIG. 3C, an ohmic layer 134 is formed on a portion of the capping layer 132, and a first recess R 1 is formed in a portion of the capping layer 132 on which the ohmic layer 134 is not formed. . In the exemplary embodiments, a dry or wet etch process is performed on the capping layer 132 until the top surface of the etch stop layer 130 is exposed using the ohmic layer 134 as an etch mask, (R1) may be formed. In this case, the first recess Rl may be formed in a manner that self-aligns with the ohmic layer 134.

The etch stop layer 130 may comprise a material having an etch selectivity with the capping layer 132 and / or the gate contact layer 124, such that the capping layer 132 It is possible to prevent the etching stopper film 130 from damaging the epitaxial layers E under the etching stopper film 130 in the etching process.

Referring to FIG. 3D, a second recess R2 may be formed in a portion of the etch stop layer 130 exposed by the first recess R1. The width of the second recess R2 may be smaller than the width of the first recess R1. In the exemplary embodiments, only the etch stop layer 130 is selectively etched using the etching selectivity difference between the gate contact layer 124 and the etch stop layer 130 in the process of forming the second recess R 2 Can be removed. In this case, it is possible to reduce mechanical / chemical damage that may occur in the underlying epitaxial layers (E).

A first passivation layer 162 may then be formed to cover over the gate contact layer 124 exposed on the substrate 110. The first passivation layer 162 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), or the like using silicon oxide, silicon oxynitride, silicon nitride or the like. Preferably, the first passivation layer 162 may be formed to a thickness of about several hundred nanometers using silicon nitride.

Thereafter, an etching process for removing portions of the first passivation layer 162 covering the upper portion of the ohmic layer 134 may be further performed, so that a portion of the upper surface of the ohmic layer 134 may be exposed. A part of the upper surface of the element isolation region 140 of the passive element region II is also exposed and the first and third insulating layers 210 and 310 may remain on the element isolation region 140 .

Referring to FIG. 3E, the gate electrode 150 may be formed on the gate contact layer 124 exposed by the second recess (R2 in FIG. 3D). In the exemplary embodiments, the gate electrode 150 may be formed by performing the method described with reference to Figs. 2A-2F. In particular, a first passivation layer 162 may serve as the hardmask layer (30 of FIG. 2F) described in FIGS. 2A-2F, ) May be further formed. In this case, the gate electrode 150 may be formed in a T-shape having a body portion (152 in FIG. 1) and a head portion (154 in FIG. 1). However, the step of forming the gate electrode 150 is not limited to the above method.

Thereafter, the resistor 200 may be formed on the first insulating layer 210 of the passive device region II. In the exemplary embodiments, the resistor 200 may be formed by electron beam evaporation using a mixture of nickel and chromium. However, the material and forming method of the resistor 200 are not limited thereto. In addition to the resistor 200, a passive element such as an inductor (not shown) may be further formed on the first insulating layer 210 of the passive element region II.

Referring to FIG. 3F, after a conductive layer (not shown) is formed on the first passivation layer 162 and the first and third insulating layers 210 and 310, the conductive layer is patterned, The drain pad 176 and the drain pad 178 can be formed. In particular, the portion of the conductive layer formed on the passive element region II can also be patterned in the same process. At this time, the conductive pattern 220 may be formed to expose the upper surface of the resistor 200 and connect to the source pad 176. In addition, the portion of the conductive layer formed on the passive element region II may be patterned to form the lower electrode 320 of the capacitor (300 of FIG. 3H) to be formed in the subsequent process.

The conductive pattern 220 connected to the resistor 200 and the lower electrode 320 of the capacitor 300 may be formed in the same process as the source pad 176 and the drain pad 178, have. However, the embodiment of the present invention is not limited thereto. After the step of forming the source pad 176 and the drain pad 178, the conductive pattern 220 and the lower electrode 320 are performed in separate processes, 176 and the drain pad 178 may be formed to include materials different from the conductive pattern 220 and the lower electrode 320.

Thereafter, an insulating layer (not shown) covering both the active element region I and the passive element region II is formed, and the insulating layer can be patterned. A second passivation layer 164 covering the upper portion of the gate electrode 150 is formed in the active element region I and a second insulating layer 215 is formed on the resistor 200 in the passive element region II. And a capacitor dielectric layer 315 may be formed on the lower electrode 320 of the passive device region II.

In the exemplary embodiments, the second passivation layer 164 may be formed using an insulating material of silicon oxide, silicon nitride, or silicon oxynitride. The first passivation layer 162 and the second passivation layer 164 formed in the active element region I may be referred to as a passivation structure 160. The passivation structure 160 may be formed to completely cover the body portion 152 and the head portion 154 of the gate electrode 150.

Referring to FIG. 3G, a source electrode 172 and a drain electrode 174 may be formed on the source pad 176 and the drain pad 178, respectively. In addition, the upper electrode 305 may be formed on the capacitor dielectric film 315. In the exemplary embodiments, the formation process of the source electrode 172, the drain electrode 174, and the upper electrode 305 may be performed in the same process. For example, after forming a photoresist pattern (not shown) exposing the source pad 176, the drain pad 178 and the capacitor dielectric layer 315 on the substrate 110, Layer 190 may be formed. Thereafter, an electroplating or electroless plating process is performed to form a conductive layer (not shown) on portions of the seed layer 190 above the source pad 176, the drain pad 178 and the capacitor dielectric layer 315 The source electrode 172, the drain electrode 174, and the upper electrode 305 can be formed. In this case, the source electrode 172, the drain electrode 174, and the upper electrode 305 may be formed to include the same material.

Thereafter, an encapsulation layer 192 covering the source electrode 172, the drain electrode 174, and the upper electrode 305 may be formed. Preferably, the encapsulation layer 192 may be formed of an insulating material such as silicon nitride.

The carrier substrate 196 may be attached using an adhesive member 194 over the encapsulation layer 192. Thereafter, a step of polishing the back surface F2 of the substrate 110 to a predetermined thickness may be further performed.

3H, the substrate 110 is placed upside down so that the rear face F2 of the substrate 110 is positioned at the top and the carrier substrate 196 is positioned at the bottom, and the rear face F2 of the substrate 110 is placed at a predetermined thickness The first via hole 181 and the second via hole 331 can be formed.

The first via hole 181 may be formed at a position overlapping the source electrode 172 and the second via hole 331 may be formed at a position overlapping the lower electrode 320. In particular, the first via hole 181 exposes a portion of the ohmic layer 134 under the source electrode 172, and the second via hole 331 exposes a portion of the lower electrode 320.

Thereafter, a seed layer 186 is formed on the rear surface F2 of the substrate 110, and then an electrolytic plating or electroless plating process is performed to form a source ground layer 184 on the seed layer 186 have. Source ground vias 182 and heat dissipation vias 332 may be further formed on the inner walls of the first and second via holes 181 and 331 in the process of forming the source ground layer 184. [

The source ground vias 182, the heat dissipation vias 332 and the source ground layer 184 are formed in the same process so that the source ground vias 182, the heat dissipation vias 332 and the source ground layer 184 all have the same material As shown in FIG. Although the inner walls of the first and second via holes 181 and 331 are not completely filled in FIG. 3H, the source ground vias 182 and the heat dissipation vias 332 are formed in the first and second via holes 181 And 331, respectively.

Thereafter, the source ground layer 184 is patterned and the substrate 110 is diced to complete the semiconductor device package 1000 shown in FIG.

According to the manufacturing method of the semiconductor device package 1000 according to the present invention, since the active device and the passive device are formed in the same process on the substrate, a compact package 1000 can be realized. In addition, by forming the T-shaped gate electrode 150 using the dual exposure method, the parasitic resistance of the semiconductor device 100 can be reduced and the breakdown voltage can be increased.

4A to 6 are graphs showing electrical characteristics of a semiconductor device package according to the present invention.

4A to 4C show the voltage-current characteristics, the transconductance and the breakdown voltage of the semiconductor device package according to the embodiment of the present invention, respectively. The embodiment corresponds to the case of providing a double recess, and as a comparative example, semiconductor device packages in a state in which recesses are not formed are also compared.

The DC characteristics were measured using Keithley's 4200-SCS / F. DC characteristics were measured in the state that Vdc = 0-15 V and Vgs = 1 to -5 V. The gate bias was kept below + 1V by the high forward gate current. At this time, it can be seen that the embodiment is more excellent in saturation characteristics and more excellent in the pitch off characteristic. The examples and comparative examples show a maximum saturation current of 480 mA / mm and 480 mA / mm, respectively, which corresponds to a maximum saturation current of the embodiment increased by about 15% compared to the comparative example. Peak extrinsic conductance of the external conductance of the embodiment is 280 mS / mm, which is superior to 260 mS / mm of the comparative example. The breakdown voltage was measured at a pinch off gate bias of -5 V, and 45 V and 36 V were measured in the examples and comparative examples, respectively, confirming that the example is 25% better than the comparative example.

5A and 5B show voltage-current characteristics and transconductance of the semiconductor device package according to the embodiment of the present invention, respectively. The embodiments correspond to the case where the T-type gate is formed using the double exposure method, and the semiconductor device packages in the case where the T-type gate is formed by using the single exposure method as a comparative example are also compared.

Referring to FIGS. 5A and 5B, the maximum saturation current density of 680 mA / mm and 620 mA / mm is shown in the embodiment and the comparative example, and the embodiment shows about 13% superior to the comparative example. In addition, the examples and comparative examples show transconductances of 500 mS / mm and 390 mS / mm, respectively. Therefore, it can be confirmed that the embodiment shows better saturation characteristics and pinch off characteristics than the comparative example.

FIG. 6 shows the relationship between the output power P _out and the gain G _P of the package when the T-type gate is formed using the dual exposure method as a comparison example using a single exposure method Together. Particularly, in order to confirm the reproducibility, eight measurement data of the packages according to the embodiments are shown, and as a comparative example, the measurement data of the two packages are shown.

Referring to FIG. 6, it can be seen that the error bars of the output power and gain of the package according to the embodiment are all reduced to within 3.2%. Therefore, it can be confirmed that the package according to the present invention can be manufactured through a reproducible manufacturing process.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. Will be apparent to those of ordinary skill in the art.

100: semiconductor device 110: substrate
112, 114: buffer layer 122: channel layer
124: gate contact layer 130: etch stop film
132: capping layer 134: ohmic layer
140: Element isolation region 150: Gate electrode
152: body part 154: head part
160: passivation structure 162: first passivation layer
164: second passivation layer 172: source electrode
174: drain electrode 176: source pad
178: drain pad 180: source ground electrode structure
181, 331: via hole 182: source ground via
184: source ground layer 186, 190: seed layer
192: Encapsulation layer 194: Adhesive member
196: Carrier substrate 200:
210, 215, 310: insulating layer 220: conductive pattern
300: capacitor 305: upper electrode
315: capacitor dielectric film 320: lower electrode
332: heat dissipation via 1000: semiconductor device package

Claims (11)

A substrate on which an active element region and a passive element region are defined;
A semiconductor element formed on the active element region of the substrate; And
And a capacitor formed on the passive element region of the substrate,
The semiconductor device may further include:
A gate electrode including a body portion and a head portion on the body portion,
A source electrode and a drain electrode spaced apart from each other with the gate electrode interposed therebetween,
And a passivation structure surrounding the gate electrode,
The capacitor
Lower electrode,
A capacitor dielectric film on the lower electrode, and
And an upper electrode on the capacitor dielectric film,
Wherein the passivation structure and the capacitor dielectric layer comprise the same material,
The passivation structure may include:
A first passivation layer surrounding the sidewalls of the body portion of the gate electrode; And
And a second passivation layer formed on the first passivation layer and surrounding the side walls and the upper surface of the head portion of the gate electrode. The method according to claim 1,
Wherein the gate electrode has a T shape. The method according to claim 1,
Wherein a width of the head portion is larger than a width of the body portion. delete The method according to claim 1,
Wherein the capacitor dielectric layer comprises the same material as the second passivation layer. The method according to claim 1,
And a resistor formed on the passive element region of the substrate. The method according to claim 1,
The source electrode is formed on a front side of the substrate,
Wherein a first via hole is formed through the substrate from a rear face of the substrate so as to overlap with the source electrode,
And a source ground via electrically connected to the source electrode on the inner wall of the first via hole. 8. The method of claim 7,
And a second via hole penetrating the substrate from the back surface of the substrate so as to overlap with the capacitor,
And a heat dissipation via electrically connected to the lower electrode of the capacitor on the inner wall of the second via hole. 9. The method of claim 8,
Wherein the heat radiation vias and the source ground vias comprise the same material. 8. The method of claim 7,
And a source ground layer formed on a back surface of the substrate and connected to the source ground via. Defining an active element region and a passive element region on a substrate;
Forming a first passivation layer on the active element region of the substrate;
Forming a gate electrode on the active element region of the substrate by a double exposure method using the first passivation layer as a mask;
Forming a second passivation layer covering the gate electrode on the active element region and forming a capacitor dielectric film on the passive element region; And
Forming a source electrode and a drain electrode spaced apart from each other with the gate electrode therebetween on the second passivation layer and forming an upper electrode on the capacitor dielectric film,
The gate electrode has a T-shape,
Wherein the gate electrode includes a body portion and a head portion on the body portion,
Wherein the first passivation layer surrounds the sidewalls of the body portion.

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