JP3715477B2 - Bipolar transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bipolar transistor, and more particularly to a lateral bipolar transistor.
[0002]
[Prior art]
In recent years, reports have been made on the use of heterojunction bipolar transistors (HBT) made of InGaP / GaAs or the like as elements constituting optical communication ICs and mobile phone power amplifiers. Usually, in the case of a bipolar transistor, the npn type transistor has higher high-frequency performance than the pnp type, and therefore an npn type transistor is exclusively used.
[0003]
However, if an npn bipolar transistor and a pnp bipolar transistor are integrated on the same semiconductor substrate, the degree of freedom in designing an IC increases. As the pnp bipolar transistor integrated on the substrate on which the npn HBT is formed, a lateral bipolar transistor as shown in FIG. 17 can be realized.
[0004]
In FIG. 17, n as a base contact layer is formed on a semiconductor substrate 171 made of semi-insulating GaAs. ⁺ A type GaAs layer 172 is formed and this n ⁺ N-type GaAs layer 172 is formed as a base layer. ^- A type GaAs layer 173 is formed. n ^- On the type GaAs layer 173, a p-type GaAs layer 175 as an emitter layer and a p-type GaAs layer 176 as a collector layer are provided adjacent to each other. An emitter electrode 177 and a collector electrode 178 are formed on the p-type GaAs layer 175 and the p-type GaAs layer 176, respectively. N ^- A portion of the type GaAs layer 173 has been removed by etching, and the n exposed at the removed portion ⁺ A base electrode 179 is provided on the type GaAs layer 172. FIG. 18 is a top view of the lateral bipolar transistor of FIG.
[0005]
In general, in order to obtain a high current gain β in a lateral bipolar transistor, it is necessary to suppress the injection of holes from the emitter to the base. In the lateral bipolar transistor shown in FIG. 17, the base layer 173 has a large area under the emitter layer 175, and a large amount of holes injected from the emitter layer 175 flow into the base layer 173. Therefore, few holes reach the collector layer 176. In order to obtain a high current gain β, it is necessary to make the emitter area sufficiently small.
[0006]
Furthermore, in order to realize the designed characteristics, it is necessary to form the emitter-collector distance Ls (FIG. 17) with good controllability. As described above, in order to obtain a high current gain in the lateral bipolar transistor, it is possible to reduce the emitter area as much as possible so that the ratio L / S of the emitter peripheral length L to the emitter area S is increased in the structure shown in FIG. It is valid. FIG. 19 is a characteristic diagram showing the relationship between the current gain β and L / S. As L / S increases, the current gain β increases.
[0007]
However, even when L / S is increased to reduce the emitter area, the current gain β is insufficient, and it is desired to realize a lateral bipolar transistor that more effectively suppresses hole injection from the emitter to the base.
[0008]
[Problems to be solved by the invention]
As described above, in the lateral bipolar transistor, it is conceivable to suppress the injection of carriers from the emitter to the base in order to obtain a high current gain, but even with such an improvement, the increase in the current gain is insufficient. It is desired to realize a lateral bipolar transistor that more effectively suppresses carrier injection from the emitter to the base.
[0009]
[Means for Solving the Problems]
In order to solve the above-described problems, a first aspect of the present invention includes a first base layer, an emitter layer and a collector layer provided side by side on the first base layer, and a portion below the first base layer. A second base layer having a band gap larger than the band gap of the first base layer, and a band gap smaller than the second base layer formed below the second base layer. And a third base layer having a bipolar transistor.
[0010]
In the second aspect of the present invention, the first base layer, an emitter layer and a collector layer provided side by side on the first base layer, and the first base layer are formed under the first base layer. A second base layer having a band gap larger than that of the base layer, and a third base layer formed under the second base layer and having a higher impurity concentration than the first base layer. A bipolar transistor is provided.
[0011]
In the second aspect of the present invention, it is preferable that the impurity concentration of the third base layer is the same as or higher than the impurity concentration of the second base layer.
[0012]
According to a third aspect of the present invention, the first base layer, an emitter layer and a collector layer provided side by side on the first base layer, and the first base layer are formed under the first base layer. A bipolar transistor comprising: a second base layer having a band gap larger than that of the base layer; and a base contact layer formed under the second base layer.
[0013]
According to a fourth aspect of the present invention, there is provided a first base layer, an emitter layer and a collector layer provided side by side on the first base layer, and a second base layer formed below the first base layer. A base layer and a third base layer formed under the second base layer, wherein the second base layer is formed with respect to carriers injected from the emitter layer into the first base layer. There is provided a bipolar transistor that constitutes a potential barrier and suppresses the carrier from flowing to the third base layer.
[0014]
In the first to fourth aspects of the present invention described above, it is more preferable to have the following configuration.
[0015]
(1) A base region having a band gap smaller than that of the second base layer is provided between the second base layer and the third base layer or the base contact layer.
[0016]
(2) A base in which a band gap increases continuously or stepwise from the first base layer to the second base layer between the first base layer and the second base layer. There must be an area.
[0017]
(3) Between the second base layer and the third base layer or the base contact layer, a band is formed continuously or stepwise from the second base layer to the third base layer. A base region with a small gap is provided.
[0018]
(4) The emitter layer and the collector layer are made of the same semiconductor material.
[0019]
(5) The emitter layer and the collector layer have substantially the same impurity concentration and thickness.
[0020]
(6) The emitter layer and the collector layer are patterned from the same layer.
[0021]
(7) The emitter layer, the collector layer, and the first base layer have the same band gap.
[0022]
(8) The bipolar transistor is a pnp type transistor.
[0023]
(9) The bipolar transistor is made of a Group 3-5 compound semiconductor material.
[0024]
According to a fifth aspect of the present invention, a first conductivity type first base layer formed in the first semiconductor region on the substrate surface and a second conductivity type provided side by side on the first base layer is provided. A first emitter layer, a first collector layer of a second conductivity type, and a first conductivity type formed below the first base layer and having a band gap larger than the band gap of the first base layer; A first bipolar transistor comprising: a second base layer; and a third base layer of a first conductivity type formed below the second base layer and having a smaller band gap than the second base layer. A second collector layer of the first conductivity type formed in a second semiconductor region on the substrate surface, a fourth base layer of the second conductivity type formed on the second collector layer, Second emitter of the first conductivity type formed on the fourth base layer Providing a bipolar transistor, characterized by comprising a second bipolar transistor having and.
[0025]
According to a sixth aspect of the present invention, a first conductivity type first base layer formed in the first semiconductor region on the substrate surface and a second conductivity type provided side by side on the first base layer are provided. A first emitter layer, a first collector layer of a second conductivity type, and a first conductivity type formed below the first base layer and having a band gap larger than the band gap of the first base layer; A first bipolar transistor comprising a second base layer and a third base layer of a first conductivity type formed under the second base layer and having an impurity concentration higher than that of the first base layer; A second collector layer of the first conductivity type formed in a second semiconductor region on the surface of the substrate, a fourth base layer of the second conductivity type formed on the second collector layer, and the second And a second emitter layer of the first conductivity type formed on the base layer of 4. By comprising a second bipolar transistor to provide a bipolar transistor according to claim.
[0026]
In the sixth aspect of the present invention, it is preferable that the impurity concentration of the third base layer is the same as or higher than the impurity concentration of the second base layer.
[0027]
According to a seventh aspect of the present invention, a first conductivity type first base layer formed in the first semiconductor region on the substrate surface and a second conductivity type provided side by side on the first base layer is provided. A first emitter layer, a first collector layer of a second conductivity type, and a first conductivity type formed below the first base layer and having a band gap larger than the band gap of the first base layer; A first bipolar transistor having a second base layer and a base contact layer of a first conductivity type formed under the second base layer; a second semiconductor region on the substrate surface; A first conductivity type second collector layer; a second conductivity type fourth base layer formed on the second collector layer; and a first conductivity type formed on the fourth base layer. And a second bipolar transistor having a second emitter layer. To provide a bipolar transistor which is characterized in Rukoto.
[0028]
According to an eighth aspect of the present invention, a first conductivity type first base layer formed in the first semiconductor region on the substrate surface and a second conductivity type provided side by side on the first base layer are provided. A first emitter layer and a first conductivity type first collector layer; a first conductivity type second base layer formed under the first base layer; and a second base layer formed under the second base layer. A third base layer of the first conductivity type, wherein the second base layer constitutes a potential barrier against carriers injected from the emitter layer to the first base layer, and A first bipolar transistor that suppresses carriers from flowing to the third base layer; a second collector layer of a first conductivity type formed in a second semiconductor region of the substrate surface; and the second collector A fourth base layer of the second conductivity type formed on the layer; and Providing a bipolar transistor, characterized by comprising a second bipolar transistor having a first conductivity type second emitter layer formed in over scan layer.
[0029]
In the fifth to eighth aspects of the present invention described above, it is further preferable to have the following configuration.
[0030]
(1) The first emitter layer and the first collector layer of the first bipolar transistor and the fourth base layer of the second bipolar transistor are made of the same semiconductor material.
[0031]
(2) The first emitter layer and the first collector layer of the first bipolar transistor and the fourth base layer of the second bipolar transistor have substantially the same impurity concentration and thickness.
[0032]
(3) The first emitter layer and the first collector layer of the first bipolar transistor and the fourth base layer of the second bipolar transistor are patterned from the same layer.
[0033]
(4) The first emitter layer, the first collector layer, and the first base layer of the first bipolar transistor, and the fourth base layer and the second of the second bipolar transistor. The collector layers of have the same band gap.
[0034]
(5) The first conductivity type is n-type, the second conductivity type is p-type, and the first and second bipolar transistors constitute pnp-type and npn-type transistors, respectively.
[0035]
(6) Both the first and second bipolar transistors are made of a Group 3-5 compound semiconductor material.
[0036]
In the fifth to eighth aspects of the present invention, it is preferable to have the configuration related to the band gap described in the first to fourth (1) to (3) of the present invention.
[0037]
As the material having a large band gap used for the second base layer, InGaAsP, InGaP, InP, AlGaN, AlGaAs, InAlAs, Si, or the like can be used. As the base material other than the second base layer, InGaAs, GaAs, InGaAsP, GaN, SiGe, or the like can be used as a material having a small band gap.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0039]
(First embodiment)
FIG. 1 is a cross-sectional view showing the configuration of the first embodiment according to the bipolar transistor of the present invention. The bipolar transistor shown in FIG. 1 is a lateral pnp bipolar transistor.
[0040]
As shown in FIG. 1, n as a base contact layer is formed on a semiconductor substrate 1 made of GaAs. ⁺ Type GaAs layer 2 (Si concentration 5 × 10 ¹⁸ cm ^-3 ) Is formed, and this n ⁺ An n-type InGaP layer 3 (Si concentration 5 × 10 ¹⁶ cm ^-3 ) Is formed. On the n-type InGaP layer 3, an n-type GaAs layer 4 (Si concentration 5 × 10 10 as a base layer) is formed. ¹⁶ cm ^-3 The p-type GaAs layer 5 as the emitter layer and the p-type GaAs layer 6 as the collector layer are provided adjacent to each other on the n-type GaAs layer 4. An emitter electrode 7 and a collector electrode 8 are formed on the p-type GaAs layer 5 and the p-type GaAs layer 6, respectively. N ^- A portion of the type GaAs layer 3 has been removed by etching, and n exposed at the removed portion ⁺ A base electrode 9 is provided on the type GaAs layer 2.
[0041]
In the lateral pnp bipolar transistor, since holes diffuse from the emitter layer 5 to the collector layer 6, the base layer 4 in contact with the emitter layer 5 does not have an n-type GaAs layer with a narrow band gap. Do not. According to the lateral pnp bipolar transistor of this embodiment, the n-type GaAs layer (base layer) 4 and n ⁺ Since an n-type InGaP layer 3 having a larger band gap than the base layer 4 is formed between the n-type GaAs layer (base contact layer) 2, an emitter current (hole current) flows from the emitter layer 5 to the collector layer 6. ) Flows, it is possible to prevent holes from diffusing from the base layer 4 to the base contact layer 2.
[0042]
That is, as shown in the band gap diagram of FIG. 11, the presence of the n-type InGaP layer 3 having a larger band gap than the base layer 4 allows the emitter layer 5 to the base contact layer 2 via the base layer 4. The n-type InGaP layer 3 serves as a barrier against holes that are about to flow. For this reason, it is possible to prevent a large amount of holes injected from the emitter layer 5 into the base layer 4 from flowing into the base contact layer 2 and increase the number of holes reaching the collector layer 6 to obtain a high current gain. It becomes possible.
[0043]
Next, an example will be described in which the lateral pnp bipolar transistor described above is manufactured simultaneously on the same substrate as the vertical npn bipolar transistor.
[0044]
First, as shown in FIG. 2, n nm of 500 nm is formed on a semiconductor substrate 20 made of GaAs. ⁺ Type GaAs layer 21 (Si concentration 5 × 10 ¹⁸ cm ^-3 ). This n ⁺ 300 nm n-type InGaP layer 22 (Si concentration 5 × 10 ¹⁶ cm ^-3 ) And a 200 nm n-type GaAs layer 23 (Si concentration 5 × 10 5) ¹⁶ cm ^-3 ). Next, on the n-type GaAs layer 23, a 60-nm p-type GaAs layer 24 (C concentration 5 × 10 ¹⁹ cm ^-3 ) And n-type In of 30 nm thereon _0.5 Ga _0.5 P passivation layer 25 (Si concentration 5 × 10 ¹⁷ cm ^-3 And a 5 nm GaAs layer 26 serving as an etching stopper layer. The GaAs layer 26 is not doped.
[0045]
Next, a 100 nm n-type In layer is formed on the GaAs layer 26. _0.5 Ga _0.5 P layer 27 (Si concentration 5 × 10 ¹⁷ cm ^-3 ), 50 nm n-type GaAs layer 28 (Si concentration 3 × 10 ¹⁸ cm ^-3 ), N-type InGaAs emitter contact layer 29 (Si concentration 3 × 10 ¹⁹ cm ^-3 ) Are epitaxially grown sequentially from the bottom. Further, a WSi layer is laminated on the n-type InGaAs emitter contact layer 29 by sputtering. Next, as shown in FIG. 3, the WSi layer is processed by reactive ion etching (RIE) using a resist mask (not shown) having an emitter electrode pattern shape to form a WSi pattern 30.
[0046]
Next, as shown in FIG. 4, using the WSi pattern 30 as a mask, the n-type InGaAs emitter contact layer 29 and the n-type GaAs layer 28 are etched with an aqueous solution of phosphoric acid and hydrogen peroxide. Further, using a hydrochloric acid-based etchant, a 50 nm thick n-type GaAs layer 28 is used as a mask for n-type In. _0.5 Ga _0.5 The P layer 27 is etched.
[0047]
Next, as shown in FIG. ₂ Layer 31 is deposited by CVD or the like. After this, B ⁺ Element isolation is performed by ion implantation. Next, as shown in FIG. 6, a base electrode pattern (resist pattern 32 in the center of FIG. 6) is used for a vertical npn type HBT, and an emitter electrode and a collector electrode pattern (right side of FIG. 6) for a horizontal type pnp bipolar transistor. The resist pattern 32) is formed.
[0048]
Next, as shown in FIG. ₂ The layer 31 is removed by etching with ammonium fluoride using the resist pattern 32 as a mask, and then the 5 nm GaAs layer 26 is etched with a phosphoric acid-based etchant. _0.5 Ga _0.5 The P passivation layer 25 is etched with a hydrochloric acid-based etchant. By this etching, the GaAs layer 26a and the n-type In are formed under the emitter mesa structure. _0.5 Ga _0.5 A P passivation layer 25a is formed, and around these layers, a GaAs layer 26b and an n-type In _0.5 Ga _0.5 A P passivation layer 25b is formed. At this time, the 5 nm GaAs layer 26 functions as an etching stopper.
[0049]
When this thin 5 nm GaAs layer 26 is used as a part of a mask, an InGaP layer (in this case, n-type In _0.5 Ga _0.5 Side etching of the P passivation layer 25) can be suppressed. n-type In _0.5 Ga _0.5 The P passivation layer 25a covers the surface of the p-type GaAs layer (vertical npn-type HBT base layer) 24, and this n-type In _0.5 Ga _0.5 Since the edge portion of the P passivation layer 25a is depleted, the leakage current between the emitter and the base can be suppressed. n-type In _0.5 Ga _0.5 If the side etching of the P passivation layer 25a can be suppressed, it is possible to reliably prevent such a leak current between the emitter and the base. The film thickness of the GaAs layer 26 is preferably 3 nm to 10 nm.
[0050]
Next, as shown in FIG. 7, a laminated film laminated with Pt / Mo / Pt / Au / Mo in order from the bottom is formed by vapor deposition. This laminated film becomes the laminated electrodes 33a and 33b in the region where the horizontal pnp bipolar transistor is formed, and becomes the laminated electrode 33c in the region where the vertical npn type HBT is formed. The laminated electrode 33b is formed so as to surround the laminated electrode 33a. The 33b laminated electrodes 33a and 33b constitute the emitter electrode and collector electrode of the lateral pnp bipolar transistor, respectively, and the laminated electrode 33c constitutes the base electrode of the vertical npn HBT. Note that the laminated film 33 d remains on the resist pattern 32.
[0051]
Next, as shown in FIG. 8, the resist pattern 32 is removed and lift-off is performed. The laminated film 33d is removed by this lift-off. Further, a resist pattern 34 is formed so as to cover a part of the emitter mesa structure and the laminated electrode 33c. Furthermore, as shown in FIG. 9, the resist pattern 34 and the stacked electrodes 33a, 33b, and 33c are used as masks. ₂ The layer 31 is removed by etching with ammonium fluoride. Further, the 5 nm GaAs layers 26a and 26b are made of an alkaline etchant which is a mixed solution of ammonia and hydrogen peroxide solution. _0.5 Ga _0.5 The P passivation layers 25a and 25b are removed by etching with a hydrochloric acid-based etchant.
[0052]
Next, the p-type GaAs layer 24 is etched using the resist pattern 34 and the stacked electrodes 33a, 33b, and 33c as a mask. By this etching, the p-type GaAs layer 24 becomes the p-type emitter layer 24a and the p-type collector layer 24b of the lateral pnp bipolar transistor and the p-type base layer 24c of the vertical npn-type HBT (FIG. 9). The p-type collector layer 24b is formed so as to surround the p-type emitter layer 24a.
[0053]
Next, as shown in FIG. 10, after removing the resist pattern 34, SiO 2 ₂ Layer 31 is etched away with ammonium fluoride. Further, a pattern which becomes a base electrode in a horizontal pnp bipolar transistor and a collector electrode in a vertical npn HBT is formed with a photoresist (not shown), and the n-type GaAs layer 23 and n-type InGaP are formed using this resist as a mask. The layer 22 is etched away to expose the n + -type GaAs layer 21. Further, an electrode laminated with AuGe / Ni / Ti / Pt / Au in order from the bottom is formed on the surface of the n + -type GaAs layer 21, and the base electrode 35a of the lateral pnp bipolar transistor and the collector electrode 35b of the vertical npn HBT are formed. Form. Through the above steps, a lateral pnp bipolar transistor and a vertical npn type HBT are manufactured.
[0054]
In the lateral pnp bipolar transistor and the vertical npn HBT described above, the p-type emitter layer 24a and the p-type collector layer 24b of the lateral pnp bipolar transistor are the same layer 24 as the p-type base layer 24c of the vertical npn-type HBT. From the same etching process. Therefore, the following effects can be obtained as well as simple production of both the transistors.
[0055]
That is, when the impurity concentration of the p-type base layer 24c is increased in the vertical npn type HBT to increase the device speed, the impurity concentrations of the p-type emitter layer 24a and the p-type collector layer 24b of the lateral pnp bipolar transistor also increase. This increases the amount of holes injected. Even in such a case, according to the invention according to the present embodiment, the presence of the n-type InGaP layer 22 having a larger band gap than the n-type GaAs layer (base layer) 23 causes the holes injected as described above to be p. The type collector layer 24b can be efficiently reached, and the increased injection hole amount can be used effectively, so that a high current gain can be obtained.
[0056]
In the manufacture of the lateral pnp bipolar transistor and the vertical npn HBT described above, in order to form the fine p-type emitter layer 24a, the method of etching the p-type GaAs layer 24 using the emitter electrode 33a as a mask as described above. It is considered effective. When using an acid etchant such as a mixed solution of phosphoric acid and hydrogen peroxide, which is commonly used as an etching solution for GaAs, if the electrode serving as a mask is in ohmic contact with the semiconductor layer to be etched, the electrochemical effect Therefore, abnormal etching occurs as shown in FIG. 12A, and the side etching amount cannot be controlled. Reference numeral 121 denotes a portion where etching has progressed due to abnormal etching. Therefore, it is difficult to form a fine emitter structure, and the distance between the emitter and the collector cannot be precisely controlled.
[0057]
On the other hand, when an etchant in which the pH of the mixed solution of ammonia and hydrogen peroxide is adjusted from 10 to 12 is used, the above-described abnormal etching does not occur, and side etching control is performed as shown in FIG. Is possible. Therefore, the p-type GaAs layer 24 can be finely processed using the emitter electrode 33a having a size of 1 μm × 1 μm as a mask, and a minute emitter of a lateral pnp bipolar transistor can be formed.
[0058]
(Second Embodiment)
FIG. 13A is a cross-sectional view showing the configuration of the second embodiment of the bipolar transistor of the present invention, and FIG. 13B is a diagram showing the band gap of the bipolar transistor of FIG. is there.
[0059]
As shown in FIG. 13, the lateral pnp bipolar transistor of this embodiment is different from that of the first embodiment in that a larger band gap is provided between the n-type GaAs layers (base layers) 23a and 23b. 10 nm n-type InGaP layer 40 (Si concentration 5 × 10 ¹⁶ cm ^-3 ) Is used.
[0060]
According to the structure according to the second embodiment, as shown in FIG. 13B, the base of the holes (n-type GaAs layer 23b and n-type) is obtained from the difference in tunneling probability of electrons and holes with respect to the n-type InGaP layer 40. ⁺ Injection into the type GaAs layer 21) can be suppressed, and as a result, the current gain can be improved.
[0061]
(Third embodiment)
FIG. 14A is a sectional view showing the configuration of the third embodiment of the bipolar transistor of the present invention, and FIG. 14B is a diagram showing the band gap of the bipolar transistor of FIG. is there.
[0062]
As shown in FIG. 14, the lateral pnp bipolar transistor of this embodiment is different from that of the first embodiment in that an n-type GaAs layer (base layer) 23 and a 300 nm n-type having a larger band gap are used. InGaP layer 50 (Si concentration 5 × 10 ¹⁶ cm ^-3 ) With a 100 nm grading layer 60 interposed therebetween.
[0063]
The grading layer 60 has a band gap that continuously increases from the n-type GaAs layer (base layer) 23 toward the n-type InGaP layer 50. The composition of the grading layer 60 is InGaAsP. By forming the grading layer 60, the conduction band of the n-type GaAs layer (base layer) 23 and the conduction band of the n-type InGaP layer 50 formed thereunder can be smoothly connected to each other. n-type GaAs layer) 23 and base contact layer (n ⁺ The electron flow between the n-type InGaP layer 50 and the n-type InGaP layer 50 is less likely to be disturbed. For this reason, in the vertical npn type HBT, electrons injected into the collector can reach the collector contact layer 21 without feeling a barrier.
[0064]
Also in the present embodiment, the base contact layer (n ⁺ Injection into the (type GaAs layer) 21 can be suppressed, and as a result, the current gain can be improved.
[0065]
(Fourth embodiment)
FIG. 15A is a sectional view showing the configuration of the fourth embodiment of the bipolar transistor of the present invention, and FIG. 15B is a diagram showing the band gap of the bipolar transistor of FIG. is there.
[0066]
As shown in FIG. 15, the lateral pnp bipolar transistor of this embodiment is different from that of the first embodiment in that an n-type GaAs layer (base layer) 23 and a base contact layer (n ⁺ 5 nm n-type InGaP layer 80 (Si concentration 5 × 10 5) having a larger band gap than the n-type GaAs layer (base layer) 23. ¹⁶ cm ^-3 ) And a structure in which the grading layer 70 is sandwiched.
[0067]
The grading layer 70 has a band gap from the n-type InGaP layer 80 to the base contact layer (n ⁺ Type GaAs layer) 21 continuously decreases. The composition of the grading layer 50 is InGaAsP. By forming the grading layer 70, in the vertical npn type HBT in which the base and the collector are reverse-biased, the flow of electrons injected into the collector is not easily disturbed, and the lateral shape in which the emitter and base are forward-biased. In the pnp bipolar transistor, it works to prevent the injection of electrons from the base to the emitter.
[0068]
Also in the present embodiment, the base contact layer (n ⁺ Injection into the (type GaAs layer) 21 can be suppressed, and as a result, the current gain can be improved.
[0069]
(Fifth embodiment)
FIG. 16A is a cross-sectional view showing the configuration of the fifth embodiment of the bipolar transistor of the present invention, and FIG. 16B is a diagram showing the band gap of the bipolar transistor of FIG. is there.
[0070]
As shown in FIG. 16, the lateral pnp bipolar transistor of this embodiment is different from that of the first embodiment in that an n-type GaAs layer (base layer) 23 and a 300 nm n-type having a larger band gap are used. InGaP layer 90 (Si concentration 5 × 10 ¹⁶ cm ^-3 ) Between the two layers 100 and 110 made of InGaAsP. The composition of InGaAsP layers 100 and 110 is In _0.43 Ga _0.57 As _0.2 P _0.8 , In _0.15 Ga _0.85 As _0.7 P _0.3 The thickness is 50 nm and 50 nm, respectively, and the impurity concentration is 5 × 10 5 respectively. ¹⁶ cm ^-3 (Si concentration).
[0071]
The band gap of the InGaAsP layer 100 is larger than that of the InGaAsP layer 110, and the band gap gradually increases from the n-type GaAs layer (base layer) 23 toward the n-type InGaP layer 90. By forming the InGaAsP layers 100 and 110, the conduction band of the n-type GaAs layer (base layer) 23 and the conduction band of the n-type InGaP layer 90 formed thereunder can be smoothly connected to each other. Layer (n-type GaAs layer) 23 and base contact layer (n ⁺ The electron flow between the n-type InGaP layer 50 and the n-type InGaP layer 50 is less likely to be disturbed. Therefore, in the vertical npn type HBT, electrons injected into the collector can reach the collector contact layer 21 without feeling a barrier.
[0072]
Also in the present embodiment, the base contact layer (n ⁺ Injection into the (type GaAs layer) 21 can be suppressed, and as a result, the current gain can be improved. Note that the number of layers in which the band gap energy increases stepwise may be three or more.
[0073]
The present invention is not limited to the above embodiment. For example, the impurity concentration of the collector layer of the vertical npn type HBT may not be uniform, and a part of the wide gap collector layer is doped with a high concentration. Accordingly, it is possible to employ a structure that reduces the tunnel barrier against the flow of electrons from the base to the collector contact layer.
[0074]
In addition, various modifications can be made without departing from the spirit of the present invention.
[0075]
【The invention's effect】
According to the present invention, carriers injected from the emitter of the lateral bipolar transistor can efficiently reach the collector, and a high current gain can be obtained. Further, a lateral bipolar transistor and a vertical bipolar transistor can be easily manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a first embodiment according to a bipolar transistor of the present invention.
FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a bipolar transistor according to the first embodiment of the present invention.
FIG. 3 is a process cross-sectional view illustrating a method for manufacturing the bipolar transistor according to the first embodiment of the present invention following FIG. 2;
4 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the present invention following FIG. 3;
5 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the present invention following FIG. 4;
6 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the present invention following FIG. 5;
7 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the present invention following FIG. 6;
8 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the present invention following FIG. 7;
FIG. 9 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the invention following FIG. 8;
FIG. 10 is a process cross-sectional view illustrating the method for manufacturing the bipolar transistor according to the first embodiment of the invention following FIG. 9;
FIG. 11 is a diagram showing a band gap of the bipolar transistor according to the first embodiment of the present invention.
FIG. 12 is a process cross-sectional view illustrating an etching method in manufacturing a bipolar transistor according to the first embodiment of the present invention.
FIG. 13 is a cross-sectional view showing a configuration of a second embodiment according to the bipolar transistor of the present invention and a diagram showing its band gap.
FIG. 14 is a cross-sectional view showing a configuration of a third embodiment according to the bipolar transistor of the present invention and a diagram showing its band gap.
FIG. 15 is a cross-sectional view showing a configuration of a fourth embodiment according to the bipolar transistor of the present invention and a diagram showing its band gap.
FIG. 16 is a cross-sectional view showing the configuration of a fifth embodiment of the bipolar transistor of the present invention and a diagram showing its band gap.
FIG. 17 is a cross-sectional view showing a structure of a lateral bipolar transistor.
18 is a top view showing the structure of the lateral bipolar transistor of FIG.
FIG. 19 is a characteristic diagram showing the relationship between current gain β and L / S.
[Explanation of symbols]
1 ... Semiconductor substrate made of GaAs
2 ... n ⁺ Type GaAs layer (base contact layer)
3 ... n-type InGaP layer (base layer)
4 ... n-type GaAs layer (base layer)
5 ... p-type GaAs layer (emitter layer)
6 ... p-type GaAs layer (collector layer)
7 Emitter electrode
8 ... Collector electrode
9 ... Base electrode

Claims (7)

An n- type first base layer, a p- type first emitter layer and a p- type first collector formed side by side on the first base layer, formed in a first semiconductor region on the substrate surface A layer, an n- type second base layer formed under the first base layer and having a band gap larger than the band gap of the first base layer, and formed under the second base layer. A first bipolar transistor comprising: an n- type third base layer having a smaller band gap than the second base layer ; and a base electrode formed on the third base layer; and the substrate An n- type second collector layer formed on the surface of the second semiconductor region, a p- type fourth base layer formed on the second collector layer, and formed on the fourth base layer second by having an n-type second emitter layer which is Comprising a chromatography La transistor, the fourth base layer of said first emitter layer and said first collector layer and said second bipolar transistor of said first bipolar transistor, it made of the same semiconductor material Bipolar transistor characterized by An n- type first base layer, a p- type first emitter layer and a p- type first collector formed side by side on the first base layer, formed in a first semiconductor region on the substrate surface A layer, an n- type second base layer formed under the first base layer and having a band gap larger than the band gap of the first base layer, and formed under the second base layer. A first bipolar transistor having an n- type base contact layer and a second semiconductor region on the substrate surface; an n- type second collector layer; and a second collector layer formed on the second collector layer. A second bipolar transistor comprising a p- type fourth base layer and an n- type second emitter layer formed on the fourth base layer , wherein the first bipolar transistor comprises: The first emitter layer and the first emitter layer It said collector layer and said second bipolar transistor of the fourth base layer is a bipolar transistor, characterized in that it consists of the same semiconductor material. An n- type first base layer, a p- type first emitter layer and a p- type first collector formed side by side on the first base layer, formed in a first semiconductor region on the substrate surface A layer, an n- type second base layer formed under the first base layer, an n- type third base layer formed under the second base layer, and the third base A base electrode formed on the layer , wherein the second base layer forms a potential barrier with respect to carriers injected from the emitter layer into the first base layer, and the carriers are in the first layer. Formed on the second semiconductor region of the substrate surface, an n- type second collector layer, and a second collector layer formed on the second collector layer. a fourth base layer of p-type, formed in the fourth base layer The and a second bipolar transistor having an n-type second emitter layer of said first emitter layer and said first collector layer and the second bipolar of said first bipolar transistor The bipolar transistor, wherein the fourth base layer of the transistor is made of the same semiconductor material . Said fourth base layer of said first emitter layer and the first collector layer and said second bipolar transistor of the first bipolar transistor, claims and having the same impurity concentration and thickness Item 4. The bipolar transistor according to any one of Items 1 to 3 . The fourth base layer of said first emitter layer and the first collector layer and said second bipolar transistor of said first bipolar transistor, according to claim 1, characterized in that to be patterned from the same layer The bipolar transistor of any one of thru | or 4 . Before Symbol first and second bipolar transistors each pnp type bipolar transistor according to any one of claims 1 to 5, characterized in that it constitutes a npn type transistor. The bipolar transistor according to any one of claims 1 to 6, wherein each of the first and second bipolar transistors is made of a Group 3-5 compound semiconductor material.

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