JP2006128528A - Hetero-junction type bipolar semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero-junction type bipolar semiconductor device and its manufacturing method which can improve property such as high frequency property or the like by stably forming base contact. <P>SOLUTION: In a hetero-junction type bipolar semiconductor device (HBT) 20a, formed by laminating a collector layer 3, a base layer 4, and an emitter layer 5 in this order; a base ohmmic contact portion 13 for connecting the base layer 4 with exterior is formed by ion implantation such as carbon small in diffusion coefficient, or the like. This ion implantation region is formed in high concentration as far as a middle depth set in the base layer 4. The device 20a is processed in low resistance by RTA treatment. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a heterojunction bipolar semiconductor device suitable for, for example, an ultrahigh-speed digital integrated circuit, a microwave analog integrated circuit, an optical signal amplifying device, and the like, and a manufacturing method thereof.

  Conventionally, a heterojunction bipolar transistor (hereinafter sometimes referred to as HBT (Hetero junction Bipolar Transistor)) using a wide gap semiconductor for the emitter layer has a high emitter injection efficiency and a high current gain. Since the base resistance can be reduced while maintaining the current gain, it is promising as an ultrahigh-speed device.

  In addition, since it can operate as a single power source and has characteristics such as low power consumption, high linearity, and high power density, it is widely used as an element for a power amplifier of a mobile phone. Furthermore, it is also used as an element for a digital IC for high-speed optical communication because of the characteristic that the HBT can operate at high speed. In these applications, the device is required to have high reliability as well as high performance.

  In the HBT having such characteristics, reducing the base travel time by reducing the thickness of the base layer is performed as a means for improving the high frequency characteristics. However, when the thickness of the base layer is reduced, the base resistance increases, so that it is necessary to increase the carrier concentration of the base layer.

Increasing the carrier concentration of the base layer not only reduces the base sheet resistance, but also reduces the base contact resistance, which seems to be effective in improving the device characteristics, but on the other hand, from the base layer to the emitter layer Hole injection cannot be suppressed, and current gain is reduced. Therefore, B.I. As shown in Jalali et al. (See Non-Patent Document 1 described later), in the InP / InGaAs system, about 1 × 10 ²⁰ cm ⁻³ is considered the limit of carrier concentration (solid solubility limit).

  Apart from the above means, the collector current is increased to improve the high-frequency characteristics of the HBT. In this case, if one HBT consumes a large current, heat generation increases, and integration becomes difficult. Therefore, it is important to reduce the power consumption by miniaturizing the emitter layer.

  When the emitter layer is miniaturized as described above, most of the base resistance is determined by the contact resistance, and it is necessary to reduce the contact resistance of the base electrode.

  With reference to FIG. 9A, an example of an HBT 74a will be described (see Patent Document 1 described later).

In this heterojunction bipolar semiconductor device 74a, an n ⁺ -type GaAs subcollector layer (not shown), an n-type GaAs collector layer 53, and a p-type GaAs base layer 54 are formed on a semi-insulating GaAs substrate (not shown). , An n-type AlGaAs emitter layer 55, an n ⁺ -type GaAs emitter contact layer 55b, a base electrode 65, and an emitter electrode 66 are stacked, and the side surfaces of the emitter layer 55, the emitter contact layer 55b, and the emitter electrode 66 are covered with an insulating film 70. Covering.

In addition, an intrinsic base region 54b to which carbon having a concentration of 1 × 10 ²⁰ cm ⁻³ is added is formed at the center of the base layer on the collector layer 53. This carbon is passivated by hydrogen. The pore concentration is 5 × 10 ¹⁹ cm ⁻³ .

Further, an external base region (base contact region) 54c to which carbon having a concentration of 1 × 10 ²⁰ cm ⁻³ is added is formed on the surface around the base layer. This carbon is almost 100% active. Therefore, the hole concentration is 1 × 10 ²⁰ cm ⁻³ . The emitter layer 55 is formed by hetero-coupling on the intrinsic base region 54b, and the base electrode 65 is formed in ohmic contact on the external base region 54c.

  FIG. 9B shows another example 74b of a heterojunction bipolar semiconductor device (see Patent Document 2 described later).

  The heterojunction bipolar semiconductor device 74b includes an n-type GaAs collector buffer layer 53b, a GaAs collector layer 53, a C-doped p-type AlGaAs internal base layer 54d, and a low-resistance external C-doped layer stacked on a semi-insulating GaAs substrate 51. The p-type AlGaAs base layer 54e, the n-type AlGaAs emitter layer 55, the n-type InGaAs emitter cap layer 55c, the collector electrode 64, the base electrode 65, and the emitter electrode 66 are included.

  Then, a carbon-hydrogen concentration having a carbon concentration of 10% or more is included in the inner base layer 54d, and traps are formed in the inner base layer 54d by this carbon-hydrogen.

  On the other hand, for the purpose of suppressing the recombination current, an emitter ledge structure that does not expose the surface of the base layer is employed (see, for example, JP-A-2001-326229). This is because a large amount of electrons, which are minority carriers for the base layer, are injected from the emitter layer side at the junction between the emitter layer and the base layer, and recombination of electrons and holes is very likely to occur. However, the increase of the recombination current is prevented by not exposing the surface of the base layer, and such a ledge structure is very effective in this respect.

  FIG. 10 shows a heterojunction bipolar semiconductor device 74c having such a structure (see Patent Document 3 described later).

This heterojunction bipolar semiconductor device 74c includes an n ⁺ -type InGaAs subcollector layer 52, an n-type InGaAs collector layer 53, a p ⁺ -type InGaAs base layer 54, a Pt diffusion region (stacked on a semi-insulating InP substrate 51). A base contact region 73, an n-type InP single crystal member 72 covering the base layer 54, an n-type InAlAs emitter layer 55, an n ⁺ -type InGaAs emitter contact layer 71, a collector electrode 64, a base electrode 65 and an emitter electrode 66. Is. In this case, the InP substrate 51 is used because the lattice constant of indium is large, so that an epitaxially grown layer such as the InGaAs layer 52 having a high operating speed can be satisfactorily lattice-matched with the lower layer to form fewer defects (hereinafter the same) ).

B. Jalali, Appl. Phys. Lett. 56, 1460, 1990 JP-A-7-2111729 (page 5, left column, line 17 to page 5, right column, line 6, line 1) JP 2000-174033 A (page 3 left column 43 line to page 3 right column 40 line, FIG. 1) JP-A-2002-368003 (2nd page, right column, 26th line to 3rd page, left column, 13th line, FIG. 1)

  However, in the case of the heterojunction bipolar semiconductor devices 74a and 74b shown in FIGS. 9A and 9B, the base contact region is formed by treatment in a hydrogen atmosphere in any structure. Therefore, when the base layer is thinned, it is difficult to control the depth of the base contact region, and it is not easy to stably form the base contact region with good reproducibility.

In the case of the heterojunction bipolar semiconductor device 74c shown in FIG. 10, for example, the electrode material of the metal base electrode 65 having a three-layer structure made of Ti / Pt / Au is used on the emitter ledge layer (single crystal member 72). Then, an ohmic contact (Pt diffusion region 73) is formed in the base layer 54, so that the diffusion coefficient is large (4 × 10 ⁻¹⁵ cm ² / sec) when the base layer is thinned. It is difficult to obtain a stable base contact because of low controllability of metal diffusion.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a heterojunction bipolar semiconductor device capable of stably forming a base contact and improving characteristics such as high-frequency characteristics and the like. It is to provide a manufacturing method.

  That is, according to the present invention, in a heterojunction bipolar semiconductor device in which a collector layer, a base layer, and an emitter layer are laminated in this order, a base contact region for connecting the base layer to the outside is formed by ion implantation. The present invention relates to a heterojunction bipolar semiconductor device.

  The present invention also provides a method of manufacturing a heterojunction bipolar semiconductor device in which a collector layer, a base layer, and an emitter layer are laminated in this order, and a step of ion-implanting a substance having the same conductivity type as the base layer into the base layer; And a step of forming a base contact region for connecting the base layer to the outside by annealing the ion implantation region, and a method for manufacturing a heterojunction bipolar semiconductor device.

  According to the heterojunction bipolar semiconductor device of the present invention, since the base contact region for connecting the base layer to the outside is formed by ion implantation, even when the base layer is thinned, the implantation depth and By ion implantation with excellent controllability of the doping amount, the base contact region can be stably formed with good reproducibility, and a stable base contact resistance can be obtained. As a result, it is possible to sufficiently cope with the miniaturization of the emitter capable of increasing the collector current and improving the high-frequency characteristics.

  According to the method of manufacturing a heterojunction bipolar semiconductor device of the present invention, a step of ion-implanting a material having the same conductivity type as the base layer into the base layer, and annealing the ion-implanted region, the base Forming a base contact region for connecting the layer to the outside, annealing the ion implantation region to activate the implanted ions, increasing the impurity concentration of the base contact region, and reducing the base contact resistance Therefore, it is easy to achieve miniaturization of the emitter (and hence improvement of high frequency characteristics).

In the present invention, in order to suppress diffusion during annealing by heat treatment after ion implantation, carbon and / or zinc and / or magnesium, particularly carbon ion implantation having a small diffusion coefficient of 4 × 10 ⁻¹⁶ cm ² / sec or less. Thus, it is desirable to form the base contact region.

  Further, at least a surface of the base contact region is covered with the emitter layer (that is, in an emitter ledge structure), the base contact region is formed by the ion implantation through the emitter layer, and the ion implantation in the base contact region is performed. It is desirable to make the doping amount larger than the impurity concentration of the emitter layer. As a result, the impurity concentration of the emitter layer can be compensated and the reverse conductivity type impurity necessary for the base contact can be doped at a high concentration.

  In addition, it is preferable that the base contact region by the ion implantation is formed to a halfway depth of the base layer. This depth can be realized with good controllability by ion implantation together with the concentration, and a desired set depth can always be realized by ion implantation conditions (especially acceleration energy).

  Further, it is desirable to have a constituent layer lattice-matched to indium phosphide. In this case, the collector layer and the emitter layer, and further the substrate under the collector layer is composed of an indium phosphide (InP) layer, and the collector layer The sub-collector layer between the substrate and the base, the base layer, and the cap layer on the emitter layer are preferably composed of a compound semiconductor layer containing indium as a main component, for example, an InGaAs layer. This is because if the InP layer is the lower layer, the lattice constant of indium is large, and therefore an epitaxial growth layer such as an InGaAs layer having a high operating speed can be satisfactorily lattice-matched with the lower layer and can be formed with fewer defects.

  Further, it is desirable that the ion implantation region is subjected to RTA (Rapid Thermal Annealing) treatment to activate the introduced impurities and to reduce the resistance of the ion implantation region. This RTA treatment can be effectively activated while suppressing the diffusion of introduced impurities sufficiently by high-speed, high-temperature (for example, 5 sec, 800 ° C.) treatment.

  Further, it is desirable to perform the ion implantation a plurality of times while changing the implantation energy. That is, each ion range is changed by a plurality of ion implantations, and the introduced impurity concentration in the ion implantation region as a whole is averaged to obtain a sufficient impurity concentration over the entire region of the base contact region.

  In addition, after sequentially forming a collector constituent material layer, a base constituent material layer, and an emitter constituent material layer, the emitter constituent material layer is half-etched to form the emitter layer (emitter ledge structure) covering the base layer. Then, the ion implantation is performed through the base coating layer to form the base contact region. At this time, for the same reason as described above, the doping amount of the ion implantation in the base contact region is larger than the impurity concentration of the emitter layer. It is desirable to increase it.

  Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

First Embodiment FIGS. 1 to 5 show a first embodiment of the present invention.

First, the structure of the heterojunction bipolar semiconductor device (HBT) 20a in this embodiment will be described with reference to FIG. 1A. On a semi-insulating InP substrate (base) 1, a film thickness of 300 nm and an impurity concentration of 1 An n ⁺ -type InGaAs subcollector layer 2 of × 10 ¹⁹ cm ^-3 , an n-type InP collector layer 3 having a film thickness of 300 nm sufficient for increasing the withstand voltage and an impurity concentration of 1 × 10 ¹⁶ cm ^-3 , and a film thickness A p ⁺ -type InGaAs base layer 4 having an impurity concentration of 3 × 10 ¹⁹ cm ⁻³ and an n-type InP emitter thin layer portion 5b having an emitter ledge structure (covering structure of the base layer 4), a film thickness of 100 nm, and an impurity concentration an n-type InP emitter layer 5 of 1 × 10 ¹⁸ cm ^-3, thickness 50 nm, and the n ⁺ -type InGaAs cap (contact) layer 6 of an impurity concentration of 1 × 10 ¹⁹ cm ^-3 are sequentially stacked, respectively of the semiconductor A collector electrode 14, an emitter electrode 16, and a base electrode 15 are provided on the layer, and these electrodes are respectively taken out to a wiring 19 on the insulating layer 18 through a plug 17 attached to a through hole of the insulating layer 18. ing. These electrodes may be formed of a laminated structure of Pt / Ti / Pt / Au.

  It should be noted that, in order to connect the base layer 4 to the outside, a base ohmic contact portion (base contact region) 13 into which, for example, carbon is ion-implanted at a high concentration is formed below the base electrode 15. That is, the intermediate depth of the base layer 4 is formed through the portion 5b, that is, a set depth.

  That is, in the emitter ledge structure in which the surface of the base layer 4 (or at least the surface of the base ohmic contact portion 13) is covered with the emitter thin layer portion 5b, the base ohmic contact portion 13 is formed by ion implantation through the emitter thin layer portion 5b. 4, the doping amount of ion implantation (introduced impurity amount) in the base ohmic contact portion 13 is higher than the concentration of impurities in the emitter thin layer portion 5b.

In order to form the base ohmic contact portion 13, it is desirable to ion-implant a p-type impurity such as carbon a plurality of times from above the emitter thin layer portion 5b while changing ion implantation conditions (particularly acceleration energy). As a result, the integrated concentration of the ion implantation region formed from the upper surface of the emitter thin layer portion 5b to the intermediate depth of the base layer 4 can be increased to, for example, 1 × 10 ²⁰ cm ⁻³ .

  This will be explained with reference to FIG. 1B. When ions are implanted a plurality of times with different acceleration energies so that the range of ion implantation of each time in the thickness direction of each semiconductor layer is, for example, Rp1, Rp2, and Rp3, Introduced impurity concentration distributions by implantation overlap. As a result, as indicated by a broken line in the figure, the impurity concentration of the emitter thin layer portion 5b can be offset, and a sufficient impurity concentration necessary for the contact can be obtained relatively uniformly up to the intermediate depth of the base layer 4.

  The collector layer 3 and the emitter layer 5, and the substrate 1 below the collector layer 3 is an InP layer, and is on the subcollector layer 2, the base layer 4, and the emitter layer 5 between the collector layer 3 and the substrate 1. The cap layer 6 is made of an InGaAs layer containing indium as a main component.

  As described above, the structure in which the InGaAs layers are alternately stacked on the InP layer is because the lattice constant of InP or InGaAs is large, so that the InGaAs or InP stacked on the InP layer is easily grown epitaxially. This is because epitaxial growth can be performed with good lattice matching (without crystal defects).

  Next, an example of a method for manufacturing the HBT 20a will be described with reference to FIGS.

First, as shown in FIGS. 2A and 2B, an n ⁺ -type InGaAs subcollector layer 2 having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is formed on a semi-insulating InP substrate 1 by chemical vapor deposition. It is formed to a thickness of 300 nm by the method (CVD).

Next, as shown in FIG. 2C, an n-type InP collector material (collector constituent material layer) 3a having an impurity concentration of 1 × 10 ¹⁶ cm ⁻³ is formed on the subcollector layer 2 to a thickness of 300 nm by CVD. To do.

Next, as shown in FIG. 2D, a p ⁺ -type InGaAs base material (base constituent material layer) 4a having an impurity concentration of 3 × 10 ¹⁹ cm ⁻³ is formed on the collector material 3a to a thickness of 50 nm by CVD. .

Next, as shown in FIG. 2E, an n-type InP emitter material (emitter constituent material layer) 5a having an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ is formed on the base material 4a to a thickness of 100 nm by CVD.

Next, as shown in FIG. ^3F, an n ⁺ -type InGaAs cap material (emitter cap constituent material layer) 6a having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is formed on the emitter material 5a to a thickness of 50 nm by CVD. To do.

  Next, as shown in FIG. 3G, a photoresist 7 having a predetermined pattern is formed on the cap material 6a.

  Next, as shown in FIG. 3H, the cap material 6a is etched using the photoresist 7 as a mask to form the cap layer 6 at a predetermined position.

  Next, as shown in FIG. 3I, the photoresist 7 is removed, and the emitter material 5a other than the lower portion of the cap layer 6 is removed by etching to a halfway depth using the cap layer 6 as a mask (half etching). Then, the emitter layer 5 is formed in a mesa shape (emitter ledge structure) in which the emitter thin layer portion 5b (base coating layer) having a thickness sufficient to cover the base material 4a without exposing the base material 4a.

  In the emitter mesa region thus formed, the emitter material 5a is removed by a thickness that does not expose the surface of the base material 4a so that the surface does not deteriorate. This is because a large amount of electrons which are minority carriers for the base layer 4 are injected from the emitter layer 5 at the junction between the emitter layer 5 (emitter material 5a) and the base layer 4 (base material 4a). Since this is a region where recombination with the hole is very likely to occur, it is an important point to prevent an increase in recombination current, so that this part is not exposed to the surface, and such a ledge structure is very effective. It is shown that.

Next, as shown in FIG. 4J, for example, a SiN film 8 having a thickness of 50 nm is deposited by CVD and etched into a mask shape. That is, in order to form a region for implanting carbon ions C ⁺ in the next step, an opening 10 is formed at a predetermined position of the SiN film 8 by etching to expose a part of the emitter thin layer portion 5b.

Next, as shown in FIG. 4 (k), using the SiN film 8 as a mask, carbon which is a substance having the same conductivity type as the base layer 4 (base material 4a) through the exposed surface of the emitter thin layer portion 5b in the opening 10 is used. Ions (C ⁺ ) 30 are ion-implanted.

The acceleration energy and ion implantation amount (dose amount) at the time of this ion implantation are, for example, 50 keV and 1 × 10 ¹³ cm ⁻² (a doping amount of 1 × 10 ²⁰ cm ^{−3 in} terms of volume), and the implanted ions are the collector material. Ion implantation is performed at a concentration that does not reach 3a and offsets the impurity concentration of the emitter layer. Here, since the diffusion coefficient of carbon is one digit or more smaller than that of zinc Zn or magnesium Mg (for example, 4 × 10 ⁻¹⁶ cm ² / sec or less), ions are difficult to diffuse and ion implantation with excellent controllability is possible. It is. However, Zn and Mg can be ion-implanted depending on conditions.

  In this case, as described with reference to FIG. 1B, by performing ion implantation a plurality of times while changing the acceleration energy, the integrated concentration of implanted impurities can be increased and the concentration distribution can be averaged (flattened). Moreover, the depth position of the ion implantation region (base ohmic contact portion 13) can be ensured with high accuracy.

  Next, the base ohmic contact is achieved by, for example, activating the implanted ions by increasing the impurity concentration in the ion implantation region and reducing the resistance by rapid thermal annealing (RTA) (rapid thermal annealing) at 800 ° C. for 5 seconds. The portion 13 is formed, and a low resistance base ohmic contact can be realized.

  This RTA is a heat treatment at a high temperature for a short time, and has a feature of realizing a high activation rate and suppressing the deterioration of crystals, and is therefore a heat treatment method suitable for a device having an epitaxial structure such as HBT. Further, with this RTA, the implanted ions hardly diffuse.

  Next, as shown in FIG. 4L, after removing the SiN film 8 as the ion implantation mask, a new SiN film 8 ′ covering the base ohmic contact portion 13, the emitter thin layer portion 5b, and the cap layer 6 is formed. It is formed into a predetermined shape by etching.

  Subsequently, by using the SiN film 8 ′ as a mask, the emitter material 5a, the base material 4a, and the collector material 3a under the opening 12 are removed by etching, whereby the emitter layer 5, the base layer 4 and the emitter layer 5 having the emitter thin layer portion 5b are removed. The collector layer 3 is formed, and a part of the surface of the subcollector layer 2 is exposed.

  Next, as shown in FIG. 5 (m), after the SiN film 8 ′ is removed, a laminated film of Pt / Ti / Pt / Au or the like is formed in a predetermined pattern by a lift-off method, a vapor deposition method, or the like, and a base electrode is formed. 15, an emitter electrode 16 and a collector electrode 14 are formed.

  Then, in order to alloy the interface between each of these electrodes and the semiconductor layer to increase the bonding strength, for example, RTA is performed at 300 ° C. or normal heat treatment is performed. In this case, the impurities in the ohmic contact portion 13 below the base electrode 15 do not diffuse.

  Next, as shown in FIG. 1A, for example, an insulating layer 18 made of a polyimide resin, which is a low-k material that reduces parasitic capacitance and is easy to be flat when applied, is formed on the entire surface. Conductive plugs 17 are formed in the provided through holes (via holes), and wirings 19 are formed in a predetermined pattern on the insulating layer 18 to complete the production of the heterojunction bipolar transistor (HBT) 20a.

  According to the present embodiment, since the base ohmic contact portion 13 is formed by implanting carbon ions by ion implantation excellent in controllability of implantation depth and doping amount, even when the base layer 4 is thinned, the setting is performed. The base ohmic contact portion 13 can be stably formed with high reproducibility and the stable base contact resistance with the depth and the implantation amount. Thus, when the HBT is integrated, it is possible to sufficiently cope with the miniaturization of the emitter that can increase the collector current and improve the high-frequency characteristics.

  Also, by performing RTA treatment on the ion implantation region, the implanted ions are activated, the impurity concentration is increased, and the base contact resistance between the base electrode 15 and the base layer 4 can be reduced, and the emitter It becomes easy to achieve miniaturization (and thus improve high-frequency characteristics). In addition, the advantages of the emitter ledge structure can be effectively exhibited.

Second Embodiment FIGS. 6 to 8 show a second embodiment of the present invention.

  As shown in FIG. 6, according to the structure of the heterojunction bipolar semiconductor device (HBT) 20b in the present embodiment, the base ohmic contact portion 13 has the same material and the same level position as the cap layer 6 on the emitter layer 5. The first embodiment is the same as the first embodiment except that the ion implantation is performed through the cap layer 6A.

  An example of a manufacturing process of the HBT 20b will be described with reference to FIGS.

  First, as shown in FIG. 7A, the sub-collector layer 2, the collector material 3a, and the base material 4a are formed on the substrate 1 through steps similar to those shown in FIGS. 2A to 3F. The emitter material 5a and the cap material 6a are sequentially laminated.

  Next, as shown in FIG. 7B, photoresists 7 and 7 'having a predetermined pattern are formed on the cap material 6a.

  Next, as shown in FIG. 7C, the cap material 6a is etched using the photoresists 7 and 7 'as a mask to form the cap layer 6A together with the cap layer 6 at a predetermined position. These cap layers 6 and 6A are formed at the same level position.

  Next, as shown in FIG. 7D, using the cap layers 6 and 6A as a mask, the emitter material 5a other than the lower portions of the cap layers 6 and 6A is half-etched to a halfway depth to remove the emitter thin layer portion 5b. An emitter mesa region is formed.

  Next, as shown in FIG. 8E, for example, a SiN film 8 having a thickness of 50 nm is deposited by a CVD method and etched into a predetermined pattern. Thereby, an opening 11 for ion implantation through the cap layer 6A is formed at a predetermined position of the SiN film 8, and a part of the cap layer 6A is exposed.

Next, as shown in FIG. 8 (f), carbon C ⁺ or the like having a small diffusion coefficient 30 passes through the exposed surface of the cap layer 6A in the opening 11 to the intermediate depth of the base material 4a from the cap layer 6A and the emitter material 5a. Is implanted to form the base ohmic contact portion 13.

The acceleration energy and the implantation amount at the time of ion implantation are, for example, 150 keV and 1 × 10 ¹³ cm ⁻² , and the acceleration energy is such that the implanted ions do not reach the collector material 3a. Also at this time, ion implantation is performed a plurality of times in the same manner as described above to form a high concentration ion implantation region that offsets the impurity concentration of the cap layer 6A and the emitter material 5a from the cap layer 6A to the intermediate depth of the base layer 4. .

  Next, the base ohmic contact portion 13 is formed by, for example, activating the implanted ions and increasing the impurity concentration in the ion implantation region to reduce the resistance by RTA (Rapid Thermal Annealing) at 800 ° C. for 5 seconds. be able to. With this RTA, the implanted ions hardly diffuse.

  Next, as shown in FIG. 8 (g), after substantially the same steps as those shown in FIGS. 4 (l) to 5 (m), one of the emitter material 5a, the base material 4a and the collector material 3a is obtained. By removing the portion, the emitter layer 5 having the emitter thin layer portion 5b, the base layer 4 and the collector layer 3 are formed, and after exposing a part of the surface of the subcollector layer 2, the base electrode 15 and the emitter electrode 16 and collector electrode 14 are formed.

  Here, for example, RTA can be performed at 300 ° C. or alloying by a normal heat treatment can be performed. At this time, when the interface between each electrode and the semiconductor layer is alloyed, impurities in the base ohmic contact portion 13 do not diffuse.

  Further, as shown in FIG. 6, for example, an insulating layer 18 made of polyimide resin, which is a low-k material that reduces parasitic capacitance, a plug 17 and a wiring 19 are formed, and a heterojunction bipolar transistor (HBT) 20b. The production of is finished.

  In the present embodiment, since the cap layer 6 on the emitter layer 5 and the cap layer 6A on which the base ohmic contact portion 13 is formed are arranged at the same level position, Since the step is eliminated and the insulating layer 18 is more easily flattened, a via hole for forming the plug 17 and further the wiring 19 on the insulating layer 18 are easily formed.

  In addition, in this embodiment, the same operations and effects as described in the first embodiment are obtained.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  For example, the implantation material, implantation energy intensity and implantation time in the ion implantation step, temperature and processing time in the RTA, and the like may be changed according to conditions such as the characteristics of the layer to be ion-implanted and the formation range of the base ohmic contact portion 13. .

  In addition, the layer configuration and constituent materials of the heterojunction bipolar semiconductor device described above may be changed, and other layers for adjusting the energy level may be formed between the respective layers. In addition to the transistor, this semiconductor device may be used as a diode, a resistor, or the like.

  The present invention is advantageously applied to the above-described emitter ledge structure, but may be applied to a normal heterojunction bipolar semiconductor device having no ledge structure.

  The heterojunction bipolar semiconductor device and the manufacturing method thereof according to the present invention can be applied to ultrahigh-speed digital integrated circuits, microwave analog integrated circuits, optical signal amplification devices, and the like.

It is sectional drawing (A) of the heterojunction type bipolar semiconductor device by the 1st Embodiment of this invention, and the graph (B) which shows the relationship between the ion implantation density | concentration and the thickness direction of an implantation area | region. FIG. 6 is a cross-sectional view sequentially showing the manufacturing steps of the heterojunction bipolar semiconductor device. FIG. 6 is a cross-sectional view sequentially showing the manufacturing steps of the heterojunction bipolar semiconductor device. FIG. 6 is a cross-sectional view sequentially showing the manufacturing steps of the heterojunction bipolar semiconductor device. It is sectional drawing which shows the manufacturing process of a heterojunction bipolar semiconductor device equally. It is sectional drawing of the heterojunction bipolar semiconductor device by the 2nd Embodiment of this invention. FIG. 6 is a cross-sectional view sequentially showing the manufacturing steps of the heterojunction bipolar semiconductor device. FIG. 6 is a cross-sectional view sequentially showing the manufacturing steps of the heterojunction bipolar semiconductor device. It is sectional drawing (A) which shows an example of the heterojunction type bipolar semiconductor device by a prior art example, and sectional drawing (B) which shows another example. It is sectional drawing which shows another example of the heterojunction type bipolar semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Subcollector layer, 3 ... Collector layer, 3a ... Collector material, 4 ... Base layer, 4a ... Base material, 5 ... Emitter layer, 5a ... Emitter material, 5b ... Emitter thin layer part,
6, 6A ... cap layer, 6a ... cap material, 7, 7 '... photoresist,
8, 8 '... SiN layer, 13 ... base ohmic contact, 14 ... collector electrode,
15 ... Base electrode, 16 ... Emitter electrode, 17 ... Plug, 18 ... Insulating layer,
20a, 20b ... heterojunction bipolar semiconductor device, 30 ... implanted ions

Claims (14)

  In a heterojunction bipolar semiconductor device in which a collector layer, a base layer, and an emitter layer are laminated in this order, a base contact region for connecting the base layer to the outside is formed by ion implantation. Heterojunction bipolar semiconductor device.   The heterojunction bipolar semiconductor device according to claim 1, wherein the base contact region is formed by ion implantation of carbon and / or zinc and / or magnesium having a small diffusion coefficient.   At least the surface of the base contact region is covered with the emitter layer, and the base contact region is formed by ion implantation through the emitter layer, and the doping amount of the ion implantation in the base contact region is an impurity of the emitter layer. The heterojunction bipolar semiconductor device according to claim 1, wherein the heterojunction bipolar semiconductor device is higher than the concentration.   2. The heterojunction bipolar semiconductor device according to claim 1, wherein the base contact region formed by the ion implantation is formed up to an intermediate depth of the base layer.   The heterojunction bipolar semiconductor device according to claim 1, comprising a constituent layer lattice-matched to indium phosphide.   The collector layer and the emitter layer, and the substrate under the collector layer is an indium phosphide layer, and a subcollector layer between the collector layer and the substrate, the base layer, and a cap layer on the emitter layer are formed. The heterojunction bipolar semiconductor device according to claim 5, comprising a compound semiconductor layer containing indium as a main component.   In a method for manufacturing a heterojunction bipolar semiconductor device in which a collector layer, a base layer, and an emitter layer are laminated in this order, a step of ion-implanting a material having the same conductivity type as the base layer into the base layer, and the ion-implanted region And a step of forming a base contact region for connecting the base layer to the outside by annealing the substrate. A method for manufacturing a heterojunction bipolar semiconductor device.   The method of manufacturing a heterojunction bipolar semiconductor device according to claim 7, wherein carbon and / or zinc and / or magnesium having a small diffusion coefficient are ion-implanted.   8. The method of manufacturing a heterojunction bipolar semiconductor device according to claim 7, wherein the ion implantation region is subjected to RTA (Rapid Thermal Annealing) processing.   The method of manufacturing a heterojunction bipolar semiconductor device according to claim 7, wherein the ion implantation is performed a plurality of times while changing the implantation energy.   After sequentially forming a collector constituent material layer, a base constituent material layer, and an emitter constituent material layer, the emitter constituent material layer is half-etched to form the emitter layer covering the base layer, and through the base covering layer, the emitter layer is formed. The heterojunction bipolar semiconductor according to claim 7, wherein the base contact region is formed by performing ion implantation, and at this time, a doping amount of the ion implantation in the base contact region is made larger than an impurity concentration of the emitter layer. Device manufacturing method.   The method of manufacturing a heterojunction bipolar semiconductor device according to claim 7, wherein the base contact region by the ion implantation is formed up to an intermediate depth of the base layer.   8. The method of manufacturing a heterojunction bipolar semiconductor device according to claim 7, wherein a heterojunction bipolar semiconductor device having a constituent layer lattice-matched to indium phosphide is manufactured. The collector layer and the emitter layer, and further the substrate under the collector layer are formed of indium phosphide, and a subcollector layer between the collector layer and the substrate, the base layer, and a cap layer on the emitter layer are formed. The method of manufacturing a heterojunction bipolar semiconductor device according to claim 13, wherein the heterojunction bipolar semiconductor device is formed of a compound semiconductor layer containing indium as a main component.

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