JPH05291282A - Manufacture of hetero-junction bipolar transistor of collector-up structure - Google Patents

Abstract

PURPOSE:To reduce a parasitic leakage current to a satisfactory extent by selectively eliminating a second insulating film, exposing an outer base layer comprising a third semiconductor layer and forming a base electrode in a self- alignment fashion and enhance high frequency properties, and especially a maximum oscillation frequency by further reducing base resistance dramatically. CONSTITUTION:Formation of an outer emitter high resistor layer 7 stabilized by oxygen ion implantation reduces a parasitic leakage current flowing during the junction of an outer emitter base. Moreover, the base resistance is reduced by connecting continuously a high concentration outer base layer 8 and a collector layer 10 to an inner intrinsic base layer 4 and making an epitaxial growth based on a regrowth process and forming a base electrode 14 in a self-alignment fashion. This construction makes it possible to reduce the base resistance dramatically and enhance a current amplification factor, high frequency properties and especially a maximum oscillation frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an ultra-high speed heterojunction bipolar transistor, and more particularly to a method for manufacturing a collector-up structure heterojunction bipolar transistor.

[0002]

2. Description of the Related Art A heterojunction bipolar transistor (hereinafter abbreviated as HBT) using a III-V group compound semiconductor is
Basically, it is a vertical transistor having a mesa structure, and is roughly classified into an emitter-up structure in which an emitter is provided on the semiconductor surface side and a collector-up structure in which a collector is provided on the semiconductor surface side. Since the HBT has a mesa structure, the base-collector junction capacitance C _{BC of the} collector-up having a smaller collector area is smaller than that of the emitter-up. Particularly, in the emitter-up structure, the proportion of the external base in the base-emitter junction area increases rapidly as the element size becomes finer. Therefore, the collector-up structure is overwhelmingly advantageous for reducing C _BC .

The high frequency characteristics of the HBT can be understood from the equivalent circuit including the intrinsic transistor and external parasitic effect. The figure of merit of the ultra-high frequency characteristics is the current gain cutoff frequency f _T and the maximum oscillation frequency f _max , of which f _T is related to the delay time when minority carriers flow from the emitter to the collector, It is represented by the formula 1).

F _T = 1 / (2π · τ _EC ) = 1 / 2π [r _E (C _BE + C _BC ) + ( _RE + _RC ) C _BC + τ _B + τ _C ] ... (1) where , R _E are internal emitter resistances and depend on the amount of emitter current. C _BC is the junction capacitance between the base and the emitter.
_RE and _RC are resistance components added to the intrinsic transistor as viewed from the terminals, and are equivalent resistances including those distributed internally. τ _B and τ _C are base and collector transit times, respectively, and are mainly determined by the structure of each base and emitter layer _{, the} film thickness _{, and the} impurity concentration. Therefore, the values are almost irrelevant to the structure for both emitter up and collector up. After all, the component that depends on the structure is only the second term of the formula (1), and R _E and R _C have no difference from the symmetry of the structure, and C _BC
It can be seen that the collector-up structure, which is overwhelmingly small, is advantageous for reducing the delay time and increasing f _T.

On the other hand, f _max greatly depends on the base resistances R _B and C _BC as expressed by the equation (2).

## EQU00002 ## f _max = (f _T / 8πR _B C _BC ) ^1/2 (2) R _E is determined by the sheet resistance of the internal intrinsic base, the sheet resistance of the external base, and the contact resistance. Even if it is up, there is no structural difference. Therefore, a collector-up structure having a small C _BC is extremely advantageous for increasing f _max . In addition to this, the collector-up structure has an advantage in that the emitter can be provided on the semiconductor substrate side, so that the influence of surface wiring or the like which is a problem in integration and mounting is small.

As described above, the collector-up structure is excellent in ultra-high speed and high integration, and can be expected as a power transistor because of its high f _max, but as described above, the emitter area is larger than the collector area. However, the current amplification factor becomes lower than that of the emitter-up structure. Further, there is a problem that C _BC increases due to carriers accumulated under the external base. In order to solve these problems, it is the first to suppress carrier injection from the emitter to the external base region. For example, n-pn AlGaAs / which has been most studied
In GaAsHBT, PN junction is formed in the wide band gap emitter layer by ion-implanting acceptor impurities such as Be, Mg, and C from above the external base,
The carrier injection to the external emitter-base junction can be suppressed by utilizing the difference in barrier potential between the intrinsic transistor portion and the hetero P-N junction.

However, the P-N junction formed in the AlGaAs wide emitter by the ion implantation method has a higher ideal coefficient n value which is a figure of merit of the P-N junction, as compared with the junction formed by the epitaxial growth method. There are many coupling current components. In the collector-up structure, the P-N junction below the external base is biased in the forward direction during transistor operation, and the leak current due to the recombination current increases in the high current density region, resulting in a marked decrease in transistor characteristics. In order for the transistor to operate normally even if the emitter-base junction is under forward bias, it is most effective to provide an electrically insulated high resistance barrier layer in the external emitter-base junction. This is a policy. In particular, wide bandgap high resistance semiconductor layers are
A high hetero barrier is generated for both holes, which is effective for suppressing carrier injection. For such a high resistance region, the method of forming an inert gas such as protons, oxygen, and argon by the ion implantation method is the most practically simple and highly reliable, but especially the high resistance region formed by the oxygen ion implantation is used. The layers have excellent thermal stability and are being used for device isolation. In this regard, for example, S.
A paper by J. Pearton et al.
stable high-resistivity AlGaAs by Oxygen-Implantat
ion] (Appl. Phys. Lett., 52.pp.395-397, 198
This is as disclosed in 8).

By the way, as described above, it is important not only to reduce C _BC but also to reduce R _B in order to improve f _max. However, when oxygen ion implantation is performed through the external base layer, the base resistance R is deteriorated due to defects due to radiation damage. _B is remarkably increased, and normal transistor operation is not exhibited. Therefore, it is indispensable to further introduce p-type impurities after the oxygen ion implantation to increase the surface concentration, and zinc diffusion is most effective for this purpose. In fact, the zinc diffusion after the oxygen ion implantation improves the base resistance to a considerable extent and makes the transistor operate normally. However, even if zinc diffusion is introduced into the external base layer, the effect of oxygen ion implantation still remains, and there is a limit to the reduction of R _B. Further, zinc has a larger diffusion coefficient than other p-type dopants, and excessive zinc diffuses into the intrinsic transistor region as well, deteriorating the transistor characteristics. Therefore, it is desirable that the zinc diffusion is the minimum necessary. Reliable,
In order to realize a higher speed transistor operation, it is necessary to further reduce R _B without using zinc diffusion.

[0008]

The above problems will be specifically described with reference to the drawings. FIG. 10 shows a conventional n-type collector-up structure in which a high-concentration p-GaAs external base layer diffused with zinc is formed after forming an AlGaAs external emitter layer having a high resistance by oxygen ion implantation.
It is a figure showing the section structure figure of pn type AlGaAs / GaAsHBT. On the semi-insulating GaAs substrate 1, Si-doped n-GaAs (Si doping concentration; 5 × 10 ¹⁸ cm
^-3 ) Buffer layer 2 0.7 μm, Si-doped N-AlG
aAs (Si doping concentration; 2 × 10 ¹⁸ cm ^{−3 to} 3 × 1)
0 ¹⁷ , Al-As composition: 0 to 0.3) 0.4 μm for the emitter layer 3 and 0.08 μm for the C-doped p-GaAs (C doping concentration; 2.5 × 10 ¹⁸ cm ⁻³ ) base layer 4.
Si-doped n-GaAs (Si doping concentration: 5 × 1
0 ¹⁶ cm ^{−3 to} 2 × 10 ¹⁷ ) The collector layer 10 is 0.5 μm,
Si-doped n-GaAs (Si doping concentration: 5 × 1
0 ¹⁸ cm ^-3 ) cap layer 11 of 0.1 μm was sequentially epitaxially grown by the molecular beam epitaxial growth (MBE) method, and oxygen ions were implanted at an accelerating voltage of 100 keV to increase the N-AlGaAs external emitter layer. Resistance, and zinc diffusion 55 on the external base
The surface concentration was increased by performing the open tube method at 0 ° C. for 3 minutes. After that, a collector electrode 13 of AuGe / Ni / Ti / Pt / Au, a non-alloy base electrode 14 of Ti / Pt / Au,
Emitter electrode 15 of AuGe / Ni / Ti / Pt / Au
Was provided and the element tube was separated to fabricate a transistor. The semiconductor processing technology such as mesa etching used a dry etching method.

FIG. 11 shows the conventional collector-up HBT shown in FIG. 10 with f _{T at} an element size of 2 μm × 10 μm and a collector current density of 2.5 × 10 ⁴ A / cm ² .
The dependence of f _{max on} the oxygen ion implantation dose amount is shown.
Black circles represent f _T and white circles represent f _max . Increasing the oxygen ion implantation dose promotes higher resistance of the N-AlGaAs outer emitter layer, and zinc-diffused high-concentration p-G
Carrier injection into the aAs external base layer 14 is suppressed, and C
_{As BC} is reduced, f _T increases and saturates to a value of approximately f _T = 50 GHz at an implant dose of 1.5 × 10 ¹⁴ cm ^-2 . On the other hand, f _max becomes R when the dose is exceeded.
_It begins to fall with increasing _B.

FIG. 12 shows the Transmission Line Model (T
Sheet resistance R _{S of} the high-concentration p-GaAs external base layer 14 subjected to oxygen ion implantation and zinc diffusion, obtained by the LM method.
And the dependency of the contact resistivity ρ _{C on} the oxygen implantation dose. It is obvious that both R _S and ρ _C increase with the increase of the implantation dose amount, and therefore, the decrease of the implantation dose amount of f _max of 1.5 × 10 ¹⁴ cm ⁻² or more shown in FIG. It can be clearly seen that this is due to the increase in external base resistance. When zinc diffusion is performed in GaAs without oxygen ion implantation under the same conditions, R _S is 260Ω / sq.
Therefore, even if the implantation dose amount shown in FIG. 11 is the smallest (5 × 10 ¹³ cm ⁻² ), R _S will be tripled. If the implantation dose is less than this, it is not possible to sufficiently suppress the carrier injection into the external emitter-base junction, which is the original purpose of introducing the oxygen ion implantation, and the transistor characteristics are deteriorated. After all, even if oxygen ion implantation and zinc diffusion are used, the high frequency characteristic f _max is limited, and the performance of the collector-up HBT has not been fully brought out under the present circumstances.

As described above, the resistance of the N-AlGaAs external emitter layer is increased by the conventional oxygen ion implantation,
In the method of forming the high-concentration p-GaAs extrinsic base layer by zinc diffusion, there is a limit to the reduction of R _B , and improvement in high frequency characteristics, especially f _max cannot be expected. Improvement of R _B is essential to bring out the potential of the collector-up HBT. At the same time, it is apparent that the same method as in the collector-up structure causes problems in the conventional method of forming the external base layer in the HBT having the emitter-up structure.

The present invention has been proposed in order to improve the above-mentioned drawbacks, and the parasitic leak current is sufficiently reduced, and the base resistance is greatly reduced, so that high frequency characteristics, especially f.
₍ EN) A method of manufacturing a heterojunction bipolar transistor having a collector-up structure that can improve _max .

[0013]

In order to achieve the above-mentioned object, the present invention is formed on a substrate by an emitter layer made of a first semiconductor layer having an n-type conductivity, and formed on the emitter layer. In forming a semiconductor laminated structure including a base layer made of a second semiconductor layer having a p-type conductivity type having a band gap smaller than that of the first semiconductor layer, a first insulating film is formed on the base layer. A step of selectively removing the first insulating film by an etching process using the deposited and patterned first photoresist pattern as a mask; and a step of removing the patterned first photoresist and the first insulating film. A step of removing a part or the whole of the base layer by an etching process using a mask to form a mesa structure, and a step of masking the patterned first photoresist and the first insulating film. Selectively forming a high-resistance region in the emitter layer made of the first semiconductor layer having the n-type conductivity by oxygen ion implantation, and after removing the first photoresist, A third semiconductor layer having a p-type conductivity type doped at an extremely high concentration by an epitaxial regrowth method using the first insulating film as a mask is used to increase the resistance of the third semiconductor layer by the oxygen ion implantation, and the third emitter layer and the first emitter layer. A second semiconductor layer, and a step of depositing the second insulating layer selectively so as to be in continuous contact with the base layer and having a height approximately the same as that of the first insulating film; A second insulating film is deposited on the external base layer made of a semiconductor layer and the first insulating film, and the second opening pattern formed so as to be inside the first photoresist pattern is used as a mask. Do Etching process to selectively remove the second insulating film and the first insulating film to expose the internal intrinsic base layer made of the second semiconductor layer, and the second insulating film and the second insulating film. By epitaxial regrowth using the first insulating film as a mask,
The fourth semiconductor layer having an n-type conductivity or the collector layer made of the undoped fourth semiconductor layer is selectively contacted only with the base layer made of the second semiconductor layer, and further A step of depositing the second insulating film so as to have the same height as that of the second insulating film; forming a collector electrode on the collector layer made of the fourth semiconductor layer and the second insulating film; The second insulating film is selectively removed by an etching process using a mask, and the third insulating film is removed.
And exposing the external base layer made of the semiconductor layer to form a base electrode in a self-aligned manner.

In order to solve the problems associated with the base resistance, it is necessary to completely eliminate the effect of oxygen ion implantation for increasing the resistance of the N-AlGaAs external emitter layer on the external base layer. For that purpose, the oxygen ion implantation for increasing the resistance is not performed through the external base layer, but the external base layer is removed by etching treatment in advance, and after the oxygen ion implantation, the selective growth technique is used to newly add ultra-high concentration. A GaAs layer doped with p-type impurities is buried. This method allows the formation of an external base layer that is completely unaffected by oxygen ion implantation. Also,
In the case of performing selective re-growth of the external base layer using a conventional epitaxial crystal grown in the order of emitter, base and collector, it is necessary to remove the collector layer and the external base layer by etching in advance. As the thickness of the collector layer increases, it becomes difficult to control etching. In addition, the protective film provided on the side surface of the collector mesa prevents contact between the side surface of the etched collector mesa and the regrown external base, which causes a problem that the internal base and the external base do not continuously contact with each other. On the other hand, if a similar regrowth method is performed using an epitaxial crystal grown up to the base layer, only the external base layer needs to be removed by an etching process in advance, so that the etching control is easy and the subsequent selective regrowth is performed. There is no problem in contact between the outer base layer and the inner base layer.

[0015]

The ultrahigh-concentration extrinsic base formed according to the present invention is not affected by oxygen ion implantation for increasing the resistance of the AlGaAs extrinsic emitter layer below it.
In addition, since it can be continuously and smoothly connected to the inner base layer, the contact resistance between the intrinsic base layer and the outer base can be reduced. In addition to this, since the collector layer is also epitaxially grown by the regrowth method, the base electrode can be formed extremely close to the collector mesa by the self-alignment technique using the collector electrode as a mask, and the photolithography technique is used. The resistance of the drawn-out region is drastically reduced as compared with the case where it is formed. Therefore, the overall base resistance is dramatically reduced as compared with the conventional method. Further, regarding the increase in resistance of the AlGaAs external emitter layer, the dose amount of oxygen ion implantation can be further increased, and a high resistance layer having excellent reliability can be formed. As a result, it is possible to provide a heterojunction bipolar transistor having a collector-up structure excellent in high frequency characteristics and reliability.

[0016]

Embodiments will be described below with reference to the drawings. It is needless to say that the embodiment is merely an example, and various modifications and improvements can be made without departing from the spirit of the present invention. 1 to 9 are views showing a manufacturing process of an npn collector up structure HBT according to the present invention, all of which are sectional structural views. In this embodiment, as a crystal material of a transistor, Al epitaxially grown on a semi-insulating GaAs substrate is used.
A GaAs / GaAs semiconductor crystal will be described as an example.

FIG. 1 shows that a Si substrate is formed on a semi-insulating GaAs substrate 1.
Doped n-GaAs (Si doping concentration; 5 × 10 ¹⁸
cm ^-3 ) Buffer layer 2 0.7 μm, Si-doped N-Al
GaAs (Si doping concentration; 3 × 10 ¹⁷ cm ^-3 , Al
-As composition; 0 to 0.3) 0.3 μm of the emitter layer 3,
C-doped p-GaAs (C doping concentration; 5 × 10 ¹⁹
cm ^-3 ) The base layer 4 is 0.05 μm in metalorganic pyrolysis (MO
The first silicon nitride film (Si ₃ N ₄ ) 5 is deposited by 0.15 μm by the plasma CVD method on the entire surface of the wafer sequentially epitaxially grown by the CVD method, and then patterned by the first photolithography. The Si ₃ N ₄ film 5 is etched by C ₂ F ₆ gas reactive ion etching (RIE) and SF ₆ gas RIE using the photoresist (about 1.1 μm thick) 6 as a mask to form the p-GaAs base layer 4. It shows the step of exposing. In this embodiment, the silicon nitride film 5 is deposited by the plasma CVD method, but it can also be deposited by the photo CVD method which causes less damage to the deposited semiconductor layer. In this embodiment, the MOCVD method is used to perform the epitaxial growth in order to increase the doping concentration of the base layer, but it is also possible to use the MOMBE method. The MONBE method uses a gas source as a raw material,
Method and MOCVD method are performed at a vacuum degree in the intermediate region (around 10 ^-5 Torr), so gas source MBE method, vacuum MOCVD method
Also called a chemical beam epitaxy (CBE) method.

FIG. 2 shows the exposed p-GaA using the photodiode 6 and the Si ₃ N ₄ film as a mask.
After removing the s base layer 4 by a dry etching method with a small amount of side etching, oxygen ions are implanted with the same mask to increase the resistance of the N-AlGaAs emitter layer 3,
It shows a step of selectively forming an external emitter layer 7 which becomes a barrier. In this example, RIE using electron cyclotron resonance (ECR) was used as the dry etching method. With the reaction gas chlorine Cl ₂ , this ECR
-Using the RIE device has the advantage that the etched semiconductor surface is less damaged. The acceleration voltage for oxygen ion implantation varies depending on the thickness of the emitter layer (because the resistance is increased over the entire area of the external emitter layer), but is set to 100 kev in this embodiment. The projective range R _P at this time is 0.
It is about 15 μm. Injection dose is 2 × 10 ¹⁴ cm
^{At -2} , the external emitter layer has a high resistance over the entire area by the injection condition as shown by 7 in the figure. Similar effects can be expected even if the implantation dose is larger than this value.

In FIG. 3, after removing the photoresist 6 and cleaning the surface of the outer emitter layer 7 implanted with oxygen ions,
Trimethylgallium (TMG),
C using As ₄ as a growth raw material at a growth temperature of 450 to 550 ° C.
It shows a step of re-growing the doped ultra-high-concentration p-GaAs outer layer 8 on the outer emitter layer 7 by 0.2 μm. The carrier concentration is controlled by controlling the As ₄ pressure while keeping the TMG supply amount constant. In this embodiment, the MOMBE method is used as the regrowth method, but MOCVD is used.
It is also possible to use the above method, whichever method is used.
No semiconductor layer is deposited on the i ₃ N ₄ film 5 and has excellent selectivity. Particularly, in the MOMBE method, the hole concentration exceeds 1 × 10 ²¹ cm ⁻³ by using C as the p-type dopant. Regarding this point, for example, a paper by T. Yamada et al. [Heavily Carbon Doped p-Type GaAsAnd GaAlAs G
rown Metalorganic Molecular Beam Epitaxy] (J. Cr
yst. Growth. 95, pp 145-149, 1989). Thus, even if the dopant is introduced into GaAs at an extremely high concentration, since C having an extremely small diffusion coefficient is used, there is no problem of diffusion into the emitter layer and the collector layer. In addition, re-grown p-Ga in the figure
The film thickness of the As external base layer 8 is set to be about the same as the combined thickness of the Si ₃ N ₄ film 5 and the intrinsic base layer 4.

FIG. 4 shows the p-GaAs external base layer 8 described above.
And a step of depositing a second Si ₃ N ₄ film 9 by 0.4 μm on the Si ₃ N ₄ film 5 by a plasma CVD method.

[0021] Figure 5, a second photolithography on the second Si ₃ N ₄ film 9 as a mask the patterned photoresist, second Si ₃ N ₄ film 9 and the first Si _This shows a step of exposing a p-GaAs intrinsic base layer 4 by etching a part of the ₃ N ₄ film 5 by C ₂ F ₆ gas RIE and SF ₆ gas RIE. The lateral width of the first Si ₃ N ₄ film 5 left on the side wall of the external base layer 8 by this etching is 0.degree. By the second photolithography and SF ₆ gas RIE (etching isotropically). Adjust to about 2 μm.

FIG. 6 shows that after the surface is cleaned on the exposed p-GaAs intrinsic base layer 4, trimethylgallium (TMG) and AS ₄ are used as a growth material by a Si-doped n-GaAs collector layer (doping concentration). Three
× 10 ¹⁶ cm ^-3 ) 10 0.4 μm, Si-doped high concentration n
-GaAs layer (doping concentration 5 × 10 ¹⁸ cm ^-3 ) 11 of 0.05 μm, Si-doped high-concentration n-InGaAs cap layer (doping concentration 2 × 10 ¹⁹ cm ^-3 , In-As composition 0.6) 12 It shows a step of regrowth in the order of 0.1 μm. When the InGaAs cap layer 12 was regrown, the growth temperature was 450 ° C., the raw materials were TMG, trimethylimidium (TMI) and As ₄ , and disilane (Si ₂ H ₆ ) was used as the dopan gas. The method of regrowth can of course be MOCVD. Generally, regrown pn junction characteristics have a high rate of recombination current.
The base-collector pn junction provided in GaAs is relatively good, and in normal transistor operation, the base-collector pn junction is reverse-biased and thus forward-biased. Increasing the recombination current is less important than the base-emitter pn junction characteristics. In addition, when applying to a power transistor, it is indispensable to increase the film thickness of the collector layer 10 in order to increase the collector breakdown voltage. In this case, the film thickness of the second Si ₃ N ₄ film 9 is increased. By adjusting the thickness, it is possible to make the heights of the second Si ₃ N ₄ film 9 and the regrown n-InGaAs cap layer 12 about the same.

In FIG. 7, a third photolithography is performed on the regrown n-InGaAs cap layer 12 and the second Si ₃ N ₄ film 9, and the collector electrode Ti / Pt / Au 13 is formed by the normal lift-off method. It shows a process of forming. In this embodiment, the collector electrode 13 is
Third photolithography is performed so as to spread outward by about 0.3 μm from the regrown n-InGaAs cap layer 12. The film thickness of the collector electrode used in this example is Ti 20 nm, Pt 20 nm, and Au 150 nm.

In FIG. 8, the second Si ₃ N ₄ film 9 is C ₂ F ₆ gas RIE using the collector electrode 13 as a mask.
And SF ₆ gas RIE are used to etch and p
After the -GaAs external base layer 8 is exposed, a step of forming the base electrode Pt / Ti / Pt / Au 14 in a self-aligned manner by an electron beam evaporation method is shown. As shown in the figure, SF ₆ -RI isotropically etched.
E By increasing the etching time, the second Si ₃ N
_By forming the T-shaped collector electrode / collector mesa structure by laterally etching the _four films 9, the base electrode can be easily formed in a self-aligned manner so that the collector electrode and the base electrode do not come into contact with each other. Base electrode film used in this example, Pt 10 nm, Ti 20 nm, Pt 50 nm, Au 15
It is 0 nm. Also, a Ti / Pt / Au non-alloy base electrode can be used.

In FIG. 9, fifth photolithography is performed to cover the semiconductor layer between the base electrode 14 and the collector electrode 13 with a photoresist, and then the external base layer 8 and oxygen ions are formed by a dry etching method. The implanted high resistance AlGaAs external emitter layer is removed, and n-G
The aAs buffer layer 2 is exposed, and the emitter electrode AuG is formed by the sixth photolithography and the normal lift-off method.
It shows a step of forming e / Ni / Ti / Pt / Au. The thickness of the emitter electrode used in this example is A
uGe85nm, Ni15nm, Ti100nm, Pt20n
m, Au 150 nm. Ohmic treatment at 360 ℃,
Performed in an N ₂ gas atmosphere. After that, a SiO ₂ interlayer insulating film is deposited by the plasma CVD method. After separating the elements, RIE is used to open holes (through holes) in the respective electrode parts.
Finally, wiring is applied to complete the element manufacturing process.

In the present invention, the resistance of the external AlGaAs emitter layer is increased by using oxygen ion implantation. However, the high resistance layer formed by ion implantation of another dopant species is
The effect is easily extinguished by the relatively high temperature regrowth process (500 to 550 ° C.). The reason is that the high resistance layer formed by ion implantation of a dopant other than oxygen ions is caused by damage due to radiation damage, and the damage recovers as the annealing temperature rises. On the other hand, the layer in which oxygen ions are implanted in the AlGaAs layer also recovers the high resistance due to radiation damage damage as the process temperature rises, but newly exhibits high resistance due to the deep level. The high resistance layer due to this deep level is
It is peculiar to oxygen ions doped in the AlGaAs layer, has outstanding thermal stability, and is effective not only in device performance but also in device reliability. In this regard, for example, a paper by SJ Pearton et al. [Fo
rmation of thethermally stable high-resistivity Al
GaAs by Oxygen Implantation) (Appl. Phys. Lett.,
52, pp395-397, 1988).

High resistance AlGaAs which is an external emitter layer
The layer (region corresponding to 7 in FIGS. 1 to 9) can also be formed by the selective regrowth method. In the process of FIG. 2, the photoresist 6 and the first Si ₃ N ₄ film 5 are used as masks for IC
By dry etching using the R-RIE method, the p-GaAs base layer 4 and the N-AlGaAs emitter layer 3 in the external region are selectively removed, and MONBE or MOC is used.
A structure similar to that shown in FIG. 3 can be formed by re-growing the undoped AlGaAs external emitter layer and the high-concentration external base layer in this order by the VD method. However, as a growth raw material, trimethyl aluminum (TMA), TM
Undoped AlGa using G, AS ₄ or Algin
When the As external emitter layer is grown, a large amount of C of the methyl group penetrates into the crystal and exhibits the behavior of a p-type dopant,
It is difficult to increase the resistance. Moreover, even if triethylaluminum (TEA), which is relatively hard to enter C, is used, high-resistance AlGaAs that can be achieved by the oxygen ion implantation method.
It is difficult to realize an external emitter layer (sheet resistance of about 10 ⁸ Ω / sq). In addition, in the regrowth method, undoped AlGa
It is difficult to control the film thickness of the As external emitter layer and the high-concentration p-GaAs external base layer, and the oxygen ion implantation that can form the high resistance layer easily and with good uniformity is advantageous in terms of throughput improvement and reliability. is there.

[0028]

As described in detail above, according to the present invention, in forming the external base region of the collector-up structure AlGaAs / GaAs heterojunction bipolar transistor, the hole concentration is 1 × 10 ²¹ cm ^-3 or more. Concentration p-G
By depositing the aAs external base layer on the AlGaAs external emitter layer whose resistance has been increased by oxygen ion implantation by the regrowth method, it is possible to form an ultra-high concentration external base layer that is not affected by oxygen ion implantation. Became. In particular,
The biggest problem in forming the extrinsic base layer by the regrowth method is to regrow it so as to be continuously connected to the intrinsic base layer and not in contact with the collector layer. Since the external base layer is regrown using the epitaxial crystal that has been grown up to the p-GaAs base layer in advance, the above problems are solved. Moreover, by adjusting the film thickness of Si ₃ N ₄ used as a mask material at the time of regrowth, even if the film thicknesses of the external base layer and the collector layer by regrowth are arbitrarily changed, the process steps shown in the present invention can be performed. Can be performed easily. As a result,
It becomes possible to form the base electrode in a self-aligned manner very close to the intrinsic base layer, and it becomes possible to significantly reduce the base resistance together with the formation of the ultra-high concentration external base.
This has the effect of improving the current amplification factor in the high collector current density region, improving the high frequency characteristics, especially f _max , and providing a bipolar transistor having a collector-up structure AlGaAs / GaAs heterojunction having excellent reliability.

For example, in the collector-up structure AlGaAs / GaAs HBT manufactured according to the present invention, 2 × 10.
With the element size of μm, the base resistance is reduced to about 5Ω, which is 1/20 of the conventional example, and as a result f _max = 200 GH
Is achieved, and the high-frequency characteristics are remarkably improved.
In the present embodiment, the AlGaAs / GaAs heterostructure material has been described, but the present invention does not select a crystal material, for example, InP / InGaAs, InAlAs / InGaA.
It is also applicable to III-V group compound semiconductors such as s and II-VI group compound semiconductors.

Further, according to the HBT manufacturing method of the present invention, the characteristics of the collector-up structure HBT device are remarkably improved, so that it is possible to expect the formation of an integrated structure simultaneously with the device of the emitter-up structure. That is, since the manufacturing method of the present invention can be applied to both the collector-up structure and the emitter-up structure, a logic circuit configuration combining these two elements can be effectively realized. For example, by integrating the transistors of both structures,
The performance of a logic circuit equivalent to I ² L / MTL, STL, ECL / CML can be significantly improved. Further, by configuring the conductivity types to be opposite, it is possible to configure a complementary logic circuit or the like. Furthermore, a light receiving element such as a PIN photodiode or APD, or an LE
It can also be applied to a method for manufacturing an optoelectronic integrated circuit (OEIC) by integrating it with a light emitting element such as a D or a laser diode. Furthermore, the HB according to the invention
It is also possible to realize an ultra-high frequency and high output power bipolar transistor by arranging these HBTs in parallel by the manufacturing method of T.

[Brief description of drawings]

FIG. 1 is an element cross-sectional structure diagram showing a manufacturing process of an npn type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 2 is an element cross-sectional structural view showing a manufacturing process of an npn type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 3 is an element cross-sectional structural diagram showing a manufacturing process of an npn collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 4 is an element cross-sectional structural diagram showing a manufacturing process of an npn collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 5 is an element cross-sectional structure diagram showing a manufacturing process of an npn type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 6 is an element cross-sectional structural view showing a manufacturing process of an npn collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 7 is an element cross-sectional structural view showing a manufacturing process of an npn type collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 8 is an element cross-sectional structural diagram showing a manufacturing process of an npn collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 9 is an element cross-sectional structural view showing a manufacturing process of an npn collector-up structure AlGaAs / GaAs HBT according to the present invention.

FIG. 10 is a device cross-sectional structural view of a conventional typical npn collector-up structure AlGaAs / GaAs HBT.

FIG. 11 is a characteristic showing the dependency of the current gain cutoff frequency f _T (GHz) and the maximum oscillation frequency f _max (GHz) on the oxygen ion implantation dose in a conventional typical collector-up structure HBT having a device size of 2 μm × 10 μm. It is a figure.

FIG. 12 shows the oxygen ion implantation dose dependency of the sheet resistance R _S and contact resistivity ρ _C of the C-doped p-type GaAs layer corresponding to the extrinsic base that has undergone zinc diffusion after oxygen ion implantation. FIG.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 Si-doped n-type GaAs buffer layer 3 Si-doped N-type AlGaAs emitter layer 4 C-doped p-type GaAs base layer 5 First plasma CVD silicon nitride film (Si
₃ N ₄ ) 6 Photoresist 7 AlGaAs external emitter region with high resistance by oxygen ion implantation 8 Super-high-concentration p-GaAs external base layer selectively regrown 9 Second plasma CVD silicon nitride film (Si
₃ N ₄ ) 10 Selectively regrown Si-doped n-type GaAs collector layer 11 Selectively regrown high-concentration Si-doped GaAs cap layer 12 Selectively regrown high-concentration Si-doped InGaAs cap layer 13 Ti / Pt / Au collector electrode 14 Pt / Ti / Pt / Au base electrode 15 AuGe / Ni / Ti / Pt / Au emitter electrode 16 Zinc-diffused high-concentration p-GaAs external base layer

Claims (1)

[Claims] 1. An emitter layer made of a first semiconductor layer having an n-type conductivity on a substrate, and a p-type emitter layer formed on the emitter layer and having a bandgap smaller than that of the first semiconductor layer. In forming a semiconductor laminated structure including a base layer formed of a second semiconductor layer having a conductivity type, a first insulating film is deposited on the base layer, and a patterned first photoresist pattern is used as a mask. Selectively removing the first insulating film by an etching process for etching, and a part or all of the base layer by an etching process using the patterned first photoresist and the first insulating film as a mask. Forming a mesa structure by removing the n-type conductivity type by oxygen ion implantation using the patterned first photoresist and the first insulating film as a mask. Selectively forming a high resistance region in an emitter layer made of a first semiconductor layer having: and an epitaxial regrowth method using the first insulating film as a mask after removing the first photoresist. By
The third semiconductor layer having a p-type conductivity type doped at an extremely high concentration is continuously brought into contact with only the external emitter layer whose resistance has been increased by the oxygen ion implantation and the base layer formed of the second semiconductor layer. Selectively, and so as to have the same height as that of the first insulating film; and on the external base layer made of the regrown third semiconductor layer and the first insulating film. A second insulating film is deposited on the first photoresist pattern, and the second insulating film and the first photoresist pattern are formed by an etching process using a second opening pattern formed inside the first photoresist pattern as a mask. Selectively removing the insulating film to expose the internal intrinsic base layer made of the second semiconductor layer, and epitaxial regrowth using the second insulating film and the first insulating film as masks, n-type guidance A second semiconductor layer having a mold or a collector layer made of an undoped fourth semiconductor layer selectively contacting only a base layer made of the second semiconductor layer, and the second insulating layer A step of depositing the same height as the film, and forming a collector electrode on the collector layer made of the fourth semiconductor layer and the second insulating film, and etching using the collector electrode as a mask Selectively removing the second insulating film by processing, exposing the external base layer made of the third semiconductor layer, and forming a base electrode in a self-aligned manner. Method of manufacturing up-structure heterojunction bipolar transistor.