JPH0883896A - Ohmic electrode for p-type compound semiconductor, bipolar transistor employing it, and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a p-type ohmic electrode having a low contact resistivity which can be formed under heat treatment conditions similar to those for n-type ohmic electrode. CONSTITUTION: Nickel (5nm thick) 14, titanium (5nm) 15, platinum(5nm) 16, titanium(30nm) 17, and platinum(100nm) 18 are deposited sequentially on a p-type GaAs layer 2. It is then heat treated at 400 deg.C for about 10min thus forming a p-type ohmic electrode 4 on the p-type GaAs layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-resistance ohmic electrode for a III-V group compound semiconductor having p-type conductivity, a bipolar transistor using this ohmic electrode, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Pt / Ti / Pt / Au electrodes have been attracting attention as low resistance ohmic electrodes for p-type high concentration GaAs layers (H. Okada et al., Japanese Jounal of Applied Phi).
sics Vol.30, 1991, pp.L558-L560). This ohmic electrode has a structure in which a Pt film, a Ti film, a Pt film, and an Au film are sequentially stacked on a p-type high concentration GaAs substrate. P
Since the Schottky barrier height of t is lower than that of p-type GaAs, in this structure, the lowermost Pt layer functions to reduce the contact resistance of the electrode. The Ti layer and Pt layer of the intermediate layer function to prevent Ga and As and the Au layer of the upper layer from mutually diffusing.

It has been reported that an extremely low base resistance can be obtained by heat treatment at 350 ° C. using the electrode having this structure as a base electrode of a bipolar transistor, and as a result, a bipolar transistor having excellent high frequency characteristics can be obtained. (Extended Abstracts of the 1993
International Conference on Solid State Devicesan
d Materials, pp.1062-1064).

An electrode having a Ni / Ti / Ag structure is also known as an electrode having a low contact resistance for n-type Si (Japanese Patent Laid-Open No. 62-234322).

[0005]

However, since the ohmic electrode described above is characterized in that ohmic contact having a low resistance can be formed by alloying at a relatively low temperature, the ohmic electrode described above has a thickness of about 35 mm.
When left at a temperature of 0 ° C. or higher, there was a problem that ohmic contact resistance increased. According to the experiments by the inventors, as shown in FIG. 10, the contact resistance of the Pt / Ti / Pt / Au electrode is minimized by the heat treatment at about 350 ° C., and the contact resistance is increased at the temperature higher than that. The reason is 400 ℃
It is considered that this is because a compound that increases the contact resistance such as PtAs ₂ is generated by the heat treatment for a while. In particular, when the p-type semiconductor layer forming the ohmic electrode is thin like the base layer of a heterojunction bipolar transistor (HBT), PtAs ₂ etc. are generated from the surface of the p-type semiconductor to a deep portion. As a result, the underlying p-type semiconductor layer becomes thin, and the contact resistance further increases.

Further, the following problems occur in the manufacture of bipolar transistors.

According to the experiments conducted by the inventors, the AuGe / Ni-based n-type ohmic electrode generally used as the collector electrode of the HBT has a minimum contact resistance at about 400 ° C. as shown in FIG. Therefore, in the manufacturing process of the HBT, the Pt / Ti / Pt / Au base electrode and A
In order to minimize the contact resistance of each of the uGe / Ni-based collector electrodes, it is necessary to form the collector electrode and heat-treat it at 400 ° C., and then form the base electrode and heat-treat it at 350 ° C. As a result, in the manufacturing process of the HBT, the collector electrode cannot be formed after the base electrode is formed, which reduces the degree of freedom of the process, and the heat treatment process of the base electrode and the collector electrode must be performed separately. There's a problem.

The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide a conventional AuG.
An ohmic electrode having a low contact resistance and a low contact resistance by a heat treatment near a temperature which is an optimum heat treatment condition for an e / Ni-based n-type ohmic electrode, a bipolar transistor using the ohmic electrode, and a method for manufacturing the same. Is provided.

[0009]

The ohmic electrode for a p-type compound semiconductor of the present invention is provided on a p-type III-V group compound semiconductor layer, and nickel ( Ni), titanium (Ti), and platinum (Pt) are contained as the main components, and as a result,
The above object is achieved.

Instead of platinum (Pt), palladium (P
d) may be included.

In the method for manufacturing an ohmic electrode for a p-type compound semiconductor according to the present invention, a metal layer containing nickel, platinum and titanium as main components is directly or thinly formed on the p-type III-V compound semiconductor layer. And a step of alloying a part of the metal layer and the p-type III-V compound semiconductor layer by heat treatment, which achieves the above object.

The metal layer includes a nickel layer, a titanium layer, and a platinum layer, and is a multilayer film having the platinum layer as an uppermost layer, and the thickness of the titanium layer is preferably 10 nm or less.

Palladium may be used instead of platinum.

In the alloying step, it is preferable to perform heat treatment at a temperature of 360 ° C to 460 ° C.

The bipolar transistor of the present invention includes a semiconductor laminated structure including at least one p-type III-V group compound semiconductor layer, and nickel, titanium, and titanium provided on the p-type III-V group compound semiconductor layer. It has an ohmic electrode for a p-type compound semiconductor containing platinum as a main component, and thereby the above object is achieved.

The semiconductor laminated structure further includes at least one n-type III-V group compound semiconductor layer, and the n-type I-type compound semiconductor layer.
An ohmic electrode for an n-type compound semiconductor, which is provided on the II-V group compound semiconductor layer and contains gold, germanium, and nickel as main components, may be further included.

Palladium may be contained instead of platinum.

In the method for manufacturing a bipolar transistor of the present invention, the first metal layer containing nickel, titanium, and platinum as main components is directly or through a thin layer on the p-type III-V group compound semiconductor layer. The method includes a forming step and a step of alloying the first metal layer and the p-type III-V group compound semiconductor layer by heat treatment, whereby the above object is achieved.

The first metal layer is a nickel layer, a platinum layer,
It is preferable that the multilayer film includes a titanium layer and the platinum layer is the uppermost layer, and the thickness of the titanium layer and the nickel layer is 10 nm or less.

Between the step of forming the first metal layer and the step of alloying, a second metal layer containing gold, germanium, and nickel as main components is added to the n-type group III-V compound semiconductor layer. The method may further include a step of forming the above directly or through a thin layer.

In the alloying step, the second metal layer and the n-type III-V group compound semiconductor layer may be alloyed at the same time.

Another method of manufacturing a bipolar transistor according to the present invention is the first n-type III-V group compound semiconductor layer, and the p layer stacked above the first n-type III-V group compound semiconductor layer. A part of a semiconductor laminated structure including a type III-V group compound semiconductor layer and a second n-type III-V group compound semiconductor layer stacked above the p-type III-V group compound semiconductor layer Etching from above the semiconductor laminated structure until the type III-V compound semiconductor layer is exposed, or leaving a thin semiconductor layer on the p-type III-V compound semiconductor layer, and the exposed p-type III A step of forming a first metal film containing nickel, titanium, and platinum or palladium on the group V compound semiconductor layer or on the thin semiconductor layer; and the first n-type group III-V compound semiconductor Layer exposed Up, or the the n-type group III-V
A step of simultaneously etching the first metal film and the p-type semiconductor layer while leaving a thin semiconductor layer on the group-group compound semiconductor layer, and the exposed first n-type III-V group compound-semiconductor layer, or A step of forming a second metal film containing gold, germanium and nickel on the thin semiconductor layer, the first metal film and the p-type III-V group compound semiconductor layer, and the second metal film and And a step of alloying the first n-type III-V compound semiconductor layer by heat treatment to simultaneously form a p-type ohmic electrode and an n-type ohmic electrode, respectively, thereby achieving the above object. It

After the step of forming the first metal film,
The method may further include forming a sidewall on the side surface of the semiconductor structure exposed by the etching, and forming a low resistance metal layer on the first metal film.

The low resistance metal layer may be formed by a plating method.

[0025]

[Function] A metal layer containing nickel, titanium and platinum is added
Formed directly or via a thin layer on a group III-V compound semiconductor layer and heat-treated so that nickel and titanium suppress the formation of high-resistance compounds such as PtAs ₂ or platinum is added in a p-type. It is considered that a low contact resistance is obtained between the ohmic electrode and the p-type semiconductor as a result of functioning to prevent deep diffusion into the type semiconductor. Furthermore, the Schottky barrier height of the alloy of nickel, titanium, and platinum with respect to the p-type semiconductor is considered to be lower than that of platinum alone.

Since the heat treatment temperature at which an ohmic contact having a low contact resistivity is formed is almost the same as the heat treatment condition for an n-type ohmic electrode containing gold, germanium and nickel, p
The heat treatment of the n-type ohmic electrode and the n-type ohmic electrode can be simultaneously performed once.

By applying this ohmic electrode to a bipolar transistor, the formation order of the n-type ohmic electrode and the p-type ohmic electrode can be arbitrarily determined, and the degree of freedom of the manufacturing method and the device structure is increased.

In the npn-type bipolar transistor, if the emitter layer is etched to expose the base layer, the base electrode is formed, and then the side wall covering the side surface of the emitter layer is formed, the emitter layer is formed on the base electrode. The low resistance layer can be formed without causing an electrical short circuit.

[0029]

EXAMPLES The present invention will be described below with reference to examples.

First, the ohmic electrode of the present invention and the method for manufacturing the same will be described.

FIG. 1 schematically shows a sectional structure of an electrode 7 using the ohmic electrode 4 according to the present invention. A p-type GaAs layer 2 is formed on a semi-insulating GaAs substrate 1, and a p-type ohmic electrode 4 is formed thereon.
The p-type ohmic electrode 4 is made of an alloy layer of nickel, titanium and platinum. p-type G below the p-type ohmic electrode 4
A diffusion layer 3 in which nickel, titanium, and platinum forming the p-type ohmic electrode 4 are diffused is formed in the aAs layer 2, and the p-type ohmic electrode 4 and the GaAs layer 2 are alloyed. A titanium layer 5 is formed on the p-type ohmic electrode 4, and a platinum layer 6 is further formed on the titanium layer 5.

The electrode 7 is formed, for example, by the following method.

As shown in FIG. 2A, semi-insulating GaA
The p-type GaAs layer 2 is epitaxially grown on the s substrate 1. If the semiconductor layer forming the ohmic electrode is a GaAs layer having p-type conductivity, the impurity concentration and the thickness may be arbitrarily determined according to the application. In this embodiment, p-type G
The aAs layer 2 has a thickness of 150 nm and a carrier concentration of 2 × 10 ¹⁹ cm ⁻³ . Further, a resist pattern 13 having an opening having a desired shape is formed on the p-type GaAs layer 2.

Next, as shown in FIG. 2B, a nickel film (thickness: 5 nm) 14 and a titanium film (5 n) are formed by electron beam evaporation so as to cover the entire semi-insulating GaAs substrate 1.
m) 15, platinum film (5 nm) 16, titanium film (30 n
m) 17 and a platinum film (100 nm) 18 are successively deposited. The nickel film 14, the titanium film 15, and the platinum film 16 form a metal multilayer film 21 that becomes the p-type ohmic electrode 4. Nickel film (5 nm) 14 and titanium film (5 nm) 1
5 is replaced, and a titanium film (5 nm) 15 is first formed on the p-type GaAs layer 2, and a nickel film (5 n) is formed thereon.
m) 14 and then a platinum film (5 nm) 16, a titanium film (30 nm) 17, and a platinum film (100 nm) 18 may be formed in this order. Further, since the titanium film (30 nm) 17 and the platinum film (100 nm) 18 function as pads, p
It is not always necessary as an ohmic electrode for a type compound semiconductor. Therefore, the nickel film 14, the titanium film 15, and the platinum film 16 are used as the ohmic electrode for the p-type compound semiconductor.
It suffices that the metal multi-layer film 21 including the above is formed so that the platinum film 16 is the uppermost layer.

If the nickel film 14 and the titanium film 15 are too thick, the platinum atoms in the platinum film 16 will not be able to enter the p-type GaAs layer 2 even by the heat treatment to be performed later.
The diffusion layer 3 shown in (c) may not be formed. Therefore, the thickness of the nickel film 14 and the titanium film 15 is preferably 1 nm to 50 nm, and preferably 2 nm to 10 nm.
Is more preferable.

After that, the resist pattern 13 is dissolved with acetone and lift-off is performed to pattern each metal film into a desired shape.

As shown in FIG. 2C, 400 ° C., 10
By performing heat treatment for a minute, the nickel film 14, the titanium film 15, and the platinum film 16 are alloyed to form the p-type ohmic electrode 4. In addition, the nickel film 14 and the titanium film 1
5, and nickel, titanium that constituted the platinum film 16,
And part of platinum diffuses into the p-type GaAs layer 2, and the diffusion layer 3
Is formed. The heat treatment temperature and time can be selected so that the required contact resistance can be obtained according to the characteristics required for the device to which the p-type ohmic electrode is applied. However, in order to form a p-type ohmic electrode having a low contact resistivity, the heat treatment temperature is preferably in the range of 360 ° C to 460 ° C, more preferably in the range of 370 ° C to 420 ° C. If the temperature is within this range, it is almost the same as the heat treatment temperature for forming the n-type ohmic electrode made of gold, germanium, and nickel, and the heat treatment for the n-type ohmic electrode and the heat treatment for the p-type ohmic electrode are performed. The heat treatments can be performed simultaneously at the same temperature.

A metal layer made of gold or the like may be provided on the uppermost Pt layer 18 for the purpose of lowering the resistance of the electrode itself.

The result of measuring the contact resistivity of the electrode 7 including the p-type ohmic electrode 4 thus produced is shown in FIG.
And shown in FIG. 3 and 4 show the relationship between the heat treatment time and the contact resistivity of the electrodes obtained by heat treatment at 350 ° C. and 400 ° C., respectively. For comparison, the results of the conventional ohmic electrode made of Pt / Ti / Pt are also shown.

As shown in FIG. 3, in the electrode 7 according to this example, a contact resistivity of about 3.8 × 10 ⁻⁷ Ω · cm ² was obtained by heat treatment at 350 ° C. for 10 minutes. The contact resistance hardly increases after the heat treatment for a long time. About 8
A contact resistivity of 4.2 × 10 ⁻⁷ Ω · cm ² can be obtained even after heat treatment for 0 minutes.

On the other hand, with the conventional Pt / Ti / Pt ohmic electrode, a contact resistivity of 3.6 × 10 ⁻⁷ Ω · cm ² can be obtained by heat treatment at 350 ° C. for 10 minutes, but for a longer time. Contact resistance increases when heat treatment is performed. When heat treated for about 80 minutes, about 7.0 × 10 ^-7 Ω ・
The contact resistivity increases to cm ² . This result indicates that the ohmic electrode of the present invention has high heat resistance.

The heat treatment at 400 ° C. makes the characteristics of the present invention more apparent. As shown in FIG. 4, the electrode 7 according to this example is subjected to heat treatment at 400 ° C. for 10 minutes to obtain a contact resistivity of about 2.1 × 10 ⁻⁷ Ω · cm ² . Contact resistance increases with heat treatment for a long time, but even after heat treatment for about 80 minutes, 5.6 × 10 ^-7 Ωcm ²
The contact resistivity of is obtained.

On the other hand, in the case of the conventional ohmic electrode made of Pt / Ti / Pt, the contact resistivity becomes about 7.0 × 10 ⁻⁷ Ω · cm ² by heat treatment at 400 ° C. for 10 minutes,
When heat treatment is performed for about 80 minutes, the contact resistivity increases to 8.4 × 10 ⁻⁷ Ω · cm ² .

Therefore, according to the electrode 7 of the present invention, 400
The contact resistance is minimized by heat treatment at about 0 ° C., and a contact resistivity lower than that of the conventional p-type ohmic electrode Pt / Ti / Pt / Au electrode can be achieved.

The electrode 7 according to this embodiment and the conventional Pt / T
FIG. 5 shows the result of the high temperature storage test conducted on the ohmic electrode made of i / Pt. FIG. 5 shows the electrode 7 according to this example obtained by heat treatment at 400 ° C. for 10 minutes, and 350 ° C.
The result shows that the conventional ohmic electrode obtained by heat treatment for 10 minutes was left at a temperature between 300 ° C and 400 ° C. In FIG. 5, the average deterioration time is defined as the average time for which the value of the contact resistivity increases by 50%.

As shown in FIG. 5, the electrode 7 according to the present embodiment.
The slope of the straight line showing the result of is almost equal to the slope of the straight line showing the result of the conventional ohmic electrode, and from these slopes, the activation energy of the deterioration reaction of the ohmic electrode is about 1.6.
It is estimated to be eV. This indicates that the electrode 7 according to the present example and the conventional ohmic electrode may be deteriorated by the same deterioration mechanism. However, when the two electrodes are compared at the same storage temperature, the electrode 7 of this example has a longer deterioration time than the conventional ohmic electrode. For example, the deterioration time of the electrode 7 of this example at 150 ° C. is 6.5 × 10 ⁶ hours, whereas that of the conventional ohmic electrode is 1.3 × 10 ⁶ hours, which is about 5 times longer. There is. Therefore, it is understood that the electrode 7 of this example is also excellent in terms of reliability.

From the above results, in the ohmic electrode of the present invention, nickel and titanium suppress the formation of high resistance compounds such as PtAs _{2 at} a temperature of about 400 ° C., or platinum diffuses deeply into the p-type semiconductor. It is considered that the contact resistance between the ohmic electrode of the present invention and the p-type semiconductor is low. Furthermore, it is considered that the alloy composed of nickel, titanium, and platinum has a lower Schottky barrier height with respect to the p-type semiconductor as compared with the case where only platinum is used.

In the above embodiment, as shown in FIG. 2B, the metal multi-layer film 21 is directly provided on the p-type GaAs layer 2, but the metal multi-layer film 21 is alloyed by heat treatment.
If nickel, titanium, and platinum of the above are diffused into the p-type GaAs layer 2 to form the diffusion layer 3 as shown in FIG. 2C, the metal multi-layer film 21 and the p-type GaAs layer 2 are separated from each other. A thin semiconductor layer may be interposed. For example, as shown in FIG. 2D, a thin semiconductor layer 19 is provided on the p-type GaAs layer 2, and a metal multilayer film 21 is formed on the semiconductor layer 19. After that, if heat treatment is performed, nickel, titanium, and platinum in the metal multilayer film 21 are removed from the semiconductor layer 19 as shown in FIG.
Through or through the semiconductor layer 19 into the p-type GaAs layer 2 to form the diffusion layer 3. In addition, the metal multilayer film 2
1 is alloyed to form a p-type ohmic electrode 4 on the p-type GaAs layer 2.

In the above embodiment, the ohmic electrode for the p-type compound semiconductor is the metal multilayer film including the nickel film, the titanium film, and the platinum film, and the platinum film is the uppermost layer. The platinum film is a homologous element. It may be replaced with a palladium film. Further, instead of forming the nickel film, the titanium film, and the platinum film, respectively, an alloy film made of nickel, titanium, and platinum may be formed. For example, FIG. 6 (a)
As shown in FIG. 6, an alloy film 22 made of nickel, titanium, and platinum is formed on the p-type GaAs layer 2 directly or via a thin semiconductor layer (not shown), and after lift-off, the structure shown in FIG. As shown, heat treatment may be performed to form the p-type ohmic electrode 4. The alloy film 22 may be deposited by evaporating each metal at the same time, or an alloy containing nickel, titanium, and platinum in the above proportions may be prepared in advance and the alloy may be vapor-deposited.

In addition to p-type GaAs, other p-type I
The p-type ohmic electrode of the present invention can be applied to a II-V semiconductor substrate. Al as a III-V semiconductor
GaAs, GaInAsP, AlGaInAs, AlG
aAsSb, InAsSbP, AlGaInP, GaA
It is preferable to use 1N or the like.

An example in which the p-type ohmic electrode of the present invention is used as the base electrode of a bipolar transistor will be described below.

As shown in FIG. 7, the bipolar transistor 41 of the present invention includes a semiconductor laminated structure 42 formed on a semi-insulating GaAs substrate 31. Semiconductor laminated structure 42
Is a collector contact layer 32 made of n ⁺ -GaAs
And a collector layer 33 made of n ⁻ -GaAs and p ⁺ -G
It includes a base layer 34 made of aAs, an emitter layer 35 made of n-AlGaAs, and an emitter contact layer 36 made of n ⁺ -InGaAs. Emitter layer 3
The AlGaAs forming 5 is the G forming the base layer 32.
It has a forbidden band width larger than aAs, and the bipolar transistor 41 has a heterojunction structure.

N is formed on a part of the collector contact layer 32.
A collector electrode 37 made of an alloy of gold, germanium, and nickel is formed as a type ohmic electrode. A base electrode 38 is formed as a p-type ohmic electrode on a part of the base layer 34. As described in the above embodiment, the base electrode 38 is made of an alloy of nickel, titanium, and platinum, and the diffusion layer 39 is formed in the base layer 34 below the base electrode 38. Further, an emitter electrode 40 is formed on the emitter contact layer 36.

A method of manufacturing the bipolar transistor 41 will be described with reference to FIGS. 8 (a) to 8 (f).

As shown in FIG. 8A, semi-insulating GaA
On the s substrate 31, a collector contact layer 32 made of n ⁺ -GaAs and a collector layer 3 made of n ⁻ -GaAs
3, p ⁺ -GaAs base layer 34, n-AlG
An emitter layer 35 made of aAs and an emitter contact layer 36 made of n ⁺ -InGaAs are sequentially epitaxially grown. Next, as shown in FIG. 8B, a tungsten silicide (WSi) film 57 is formed on the emitter contact layer 36 by a sputtering method, and then a resist pattern 58 is formed on the tungsten silicide (WSi) film 57 by photolithography. Form.

By etching the tungsten silicide film 57 by reactive ion etching (RIE) using the resist pattern 58 as a mask, FIG.
The electrode 59 is formed as shown in FIG. n ⁺ -InG
Since the height of the Schottky barrier formed by the contact between aAs and the tungsten silicide is small, the electrode 59 is joined to the emitter contact layer 36 with low contact resistance without heat treatment.

Then, the emitter contact layer 36 and the emitter layer 35 are etched by wet etching using the electrode 59 as a mask to expose the surface of the base layer 34. The emitter layer 3 without exposing the surface of the base layer 34
You may etch so that the thin semiconductor layer which consists of a part of 6 may remain. Since the emitter contact layer 36 and the emitter layer 35 are isotropically etched, the width W of the electrode 59 is reduced.
Compared to 1, the width W2 of the emitter contact layer 36 and the emitter layer 35 is smaller.

Then, as shown in FIG. 8D, nickel layer (thickness: 5 nm) / titanium layer (5 nm) / platinum layer (5 nm) / titanium layer (30 nm) / platinum layer (100 n).
m) is a semi-insulating GaAs substrate 3
1 is vapor-deposited by an electron beam method so as to cover the whole.

As shown in FIG. 8E, the resist pattern 61 is formed on the emitter contact layer 36 and the emitter layer 35.
And a part of the metal multilayer film 60 to be the base electrode are formed, and the metal multilayer film 60 and the base layer 34 are simultaneously etched by the ion milling method using the resist pattern 61 as a mask until the collector layer 33 is exposed. , A part of the collector layer 33 is etched.

As shown in FIG. 8F, after removing the resist pattern 61, the collector contact layer 32 is exposed by photolithography and wet etching.
A metal multilayer film 64 including a gold-germanium layer (thickness: 100 nm) / nickel layer (20 nm) / gold layer (200 nm) is formed by a lift-off method.

Finally, heat treatment is carried out once at 400 ° C. for 10 minutes to obtain the metal multilayer film 64 and the collector layer 33.
Are alloyed to form a collector electrode 37 made of an alloy of gold, germanium and nickel. At the same time,
The metal multilayer film 60 and the base layer 34 are alloyed to form a base electrode 38 made of an alloy of nickel, titanium, and platinum. Since the collector electrode 37 and the base electrode 38 are optimally alloyed at 400 ° C. as an n-type ohmic electrode and a p-type ohmic electrode, respectively, an extremely low contact resistance can be obtained for both the collector electrode 37 and the base electrode 38. The metal multilayer film 60 and the electrode 59 form the emitter electrode 40. Emitter contact layer 36 and electrode 59
Although this is also heated by this heat treatment, this heat treatment step is not particularly required because a good ohmic contact is formed between the emitter contact layer 36 and the electrode 59 by non-alloy ohmic contact.

In the method of manufacturing the bipolar transistor described above, after the metal multilayer film 60 to be the base electrode 38 is formed on the base layer 34, the metal multilayer film 60 and the base layer 34 are simultaneously etched using the resist pattern 61 as a mask. . Therefore, the base electrode 38 is
4 will be self-aligned. Therefore, the contact area between the base electrode 38 and the base layer 34 becomes maximum,
In addition, the base-collector capacitance can be reduced. As a result, a bipolar transistor having excellent high frequency characteristics can be manufactured. In addition, since the order of forming the collector electrode and the base electrode can be arbitrarily changed, the degree of freedom in designing the device structure is increased.

On the other hand, when manufacturing a bipolar transistor using a conventional Pt / Ti / Pt / Au base electrode, it is necessary to first perform a process with a high heat treatment temperature, so that the base layer is determined and the collector layer is formed. The collector electrode must be formed before the base electrode is formed. Therefore, it is very difficult to form the base electrode in a self-aligned manner with respect to the base layer, and a complicated process is required.

The bipolar transistor 41 may be provided with a low resistance metal layer 71 on the base electrode 38 for the purpose of reducing the resistance of the base electrode 38. In this case, it is preferable to cover the side surfaces of the emitter layer 35 and the emitter contact layer 36 with the insulating film 72.

As described with reference to FIG. 8D, after depositing the metal multilayer film 60 so as to cover the entire semi-insulating GaAs substrate 31, as shown in FIG. 9A, silicon oxide or the like is used. An insulating film 73 made of is deposited so as to cover the entire semi-insulating GaAs substrate 31. As shown in FIG. 9B, the insulating film 73 is etched by anisotropic etching until the surface of the metal multilayer film 60 is exposed and left as sidewalls 74 that cover the side surfaces of the emitter layer 35 and the emitter contact layer 36. .

Subsequently, as shown in FIG. 9C, a metal layer 71 made of gold is formed on the metal multilayer film 60 by a plating method using the metal multilayer film 60 as an electrode. After that, FIG.
As shown in (d), a resist pattern 61 is formed,
The gold layer 71, the metal multilayer film 60, and the base layer 34 are etched by the ion milling method, and the collector layer 33 is further formed.
To etch a part of. After that, the process described with reference to FIG. 8F is continuously performed.

According to this structure, the thick Au layer 71 is formed on the base electrode 38 without causing an electrical short circuit with the emitter layer 35, the emitter contact layer 36, or the emitter electrode 40.
It can be formed on the upper surface and the metal resistance of the base electrode can be reduced. Therefore, the effect is particularly great when the base electrode is miniaturized to reduce the base-collector capacitance.

Further, the high frequency characteristics of the high frequency device can be improved.

In the above embodiment, the emitter-up type structure in which the emitter is arranged at the upper part has been described, but the same can be applied to the collector-up type structure in which the collector is arranged at the upper part. Although the npn-type bipolar transistor has been described, the electrode of the present invention can be used as a collector or an emitter electrode in the pnp-type bipolar transistor.

Further, as is apparent from the above embodiments, in the bipolar transistor of the present invention, the n-type ohmic electrode and the p-type ohmic electrode of the present invention are not necessarily formed directly on the base layer, the emitter layer or the collector layer. Of course, if necessary, it may be formed in a contact layer provided in contact with these semiconductor layers.

Further, although the vertical type transistor has been described in the above embodiment, it is easily understood that the present invention can be applied to other compound semiconductor devices having a p-type ohmic electrode.

Since the ohmic electrode of the present invention has a lower Schottky barrier height than a p-type semiconductor, it has a higher Schottky barrier height than an n-type semiconductor and is a Schottky electrode having good characteristics. Therefore, this Ni, Ti, P
The metal layer containing t or Pd can be applied to the gate of the n-channel MESFET. In this case, it is necessary to perform heat treatment in order to diffuse platinum into the n-type semiconductor layer.

[0073]

According to the present invention, it has a low contact resistivity,
It is possible to obtain a highly reliable p-type ohmic electrode.

Further, in the manufacture of the bipolar transistor, the p-type ohmic electrode and the n-type ohmic electrode can be heat-treated at once and at the same temperature, so that the manufacturing process is simplified. Since the p-type ohmic electrode and the n-type ohmic electrode may be formed in any order,
A transistor having a free structure can be manufactured without being restricted by the manufacturing process. Further, by providing the low resistance layer on the p-type ohmic electrode which becomes the base electrode, the base resistance is further reduced, and the high frequency characteristics of the device operating at high speed are improved.

[Brief description of drawings]

FIG. 1 schematically shows the structure of an ohmic electrode of the present invention.

2 (a) to 2 (e) are cross-sectional views illustrating a method for manufacturing a p-type ohmic electrode according to the present invention.

FIG. 3 is a graph showing the relationship between the heat treatment time and the contact resistivity of the p-type ohmic electrode of the present invention and the conventional p-type ohmic electrode at 350 ° C.

FIG. 4 is a graph showing the relationship between heat treatment time and contact resistivity of a p-type ohmic electrode of the present invention and a conventional p-type ohmic electrode at 400 ° C.

FIG. 5 is a graph showing the relationship between the storage temperature and the average deterioration time of the p-type ohmic electrode of the present invention and the conventional p-type ohmic electrode.

6 (a) and 6 (b) are cross-sectional views for explaining manufacturing steps of another method for manufacturing the p-type ohmic electrode of the present invention.

FIG. 7 is a sectional view showing a structure of a bipolar transistor of the present invention.

8A to 8F are cross-sectional views illustrating a method of manufacturing the bipolar transistor shown in FIG.

9A to 9D are sectional views illustrating a method of forming a gold layer on the p-type ohmic electrode of the bipolar transistor shown in FIG. 7.

FIG. 10 is a graph obtained by experiments by the inventor of the present invention regarding the relationship between the heat treatment temperature and the contact resistivity of a conventional p-type ohmic electrode.

FIG. 11 is a graph obtained by experiments by the inventor of the present invention regarding the relationship between the heat treatment temperature and the contact resistivity of an n-type ohmic electrode.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 p-type GaAs layer 3 diffusion layer 4 p-type ohmic electrode 5 titanium layer 6 platinum layer 7 electrode

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/205 21/331 29/73 H01L 29/46 H 29/72

Claims (16)

[Claims] 1. A p-type III-V group compound semiconductor layer is provided on an interface with the p-type III-V group compound semiconductor,
Nickel (Ni), titanium (Ti), and platinum (Pt)
An ohmic electrode for a p-type compound semiconductor containing as a main component. 2. Palladium (P) instead of platinum (Pt)
The ohmic electrode for a p-type compound semiconductor according to claim 1, comprising d). 3. A step of forming a metal layer containing nickel, platinum, and titanium as main components on the p-type III-V compound semiconductor layer directly or via a thin layer, and the heat treatment to form the metal layer and the metal layer. A method of manufacturing an ohmic electrode for a p-type compound semiconductor, including a step of alloying a part of the p-type III-V compound semiconductor layer. 4. The metal layer includes a nickel layer, a titanium layer, and a platinum layer, and is a multilayer film having the platinum layer as an uppermost layer, and the titanium layer has a thickness of 10 nm or less.
The method for producing an ohmic electrode for a p-type compound semiconductor according to item 1. 5. The method for producing an ohmic electrode for a p-type compound semiconductor according to claim 3, wherein palladium is used instead of platinum. 6. In the alloying step, 360 ° C.
The method for manufacturing an ohmic electrode for a p-type compound semiconductor according to claim 3 or 4, wherein the heat treatment is performed at a temperature of 460 to 460 ° C. 7. A semiconductor laminated structure including at least one p-type III-V group compound semiconductor layer, provided on the p-type III-V group compound semiconductor layer, and containing nickel, titanium, and platinum as main components. A bipolar transistor having an ohmic electrode for a p-type compound semiconductor. 8. The semiconductor laminated structure further includes at least one n-type III-V compound semiconductor layer, is provided on the n-type III-V compound semiconductor layer, and mainly contains gold, germanium, and nickel. The bipolar transistor according to claim 7, further comprising an ohmic electrode for an n-type compound semiconductor contained as a component. 9. The bipolar transistor according to claim 7, which contains palladium instead of platinum. 10. A step of forming a first metal layer containing nickel, titanium, and platinum as a main component on the p-type III-V compound semiconductor layer directly or through a thin layer, and heat treatment And a step of alloying the metal layer of No. 1 and the p-type III-V compound semiconductor layer. 11. The first metal layer includes a nickel layer, a platinum layer, and a titanium layer, and is a multilayer film having the platinum layer as an uppermost layer, and the titanium layer and the nickel layer have a thickness of 10 nm.
The method for manufacturing a bipolar transistor according to claim 10, which is as follows. 12. An n-type III-type second metal layer containing gold, germanium, and nickel as main components between the step of forming the first metal layer and the step of alloying.
The method for producing a bipolar transistor according to claim 10, further comprising a step of forming the bipolar transistor directly or via a thin layer on the Group V compound semiconductor layer. 13. The method of manufacturing a bipolar transistor according to claim 12, wherein in the alloying step, the second metal layer and the n-type III-V compound semiconductor layer are also alloyed at the same time. 14. A first n-type III-V group compound semiconductor layer, a p-type III-V group compound semiconductor layer stacked above the first n-type III-V group compound semiconductor layer, and p
A second laminated layer above the type III-V compound semiconductor layer
A thin semiconductor until the p-type III-V compound semiconductor layer is exposed, or a part of the semiconductor laminated structure including the n-type III-V compound semiconductor layer is exposed. A step of etching from above the semiconductor laminated structure while leaving a layer, and a method including nickel, titanium, and platinum or palladium on the exposed p-type III-V compound semiconductor layer or the exposed thin semiconductor layer. Forming a metal film of No. 1 and until the first n-type III-V compound semiconductor layer is exposed, or leaving a thin semiconductor layer on the n-type III-V compound semiconductor layer. Simultaneously etching the metal film and the p-type semiconductor layer, and exposing the exposed first n-type III-V compound semiconductor layer,
Alternatively, a step of forming a second metal film containing gold, germanium, and nickel on the thin semiconductor layer, the first metal film, the p-type III-V group compound semiconductor layer, and the second metal Membrane and the first n-type III-V
The group compound semiconductor layer is alloyed by heat treatment,
Forming a bipolar ohmic electrode and an n-type ohmic electrode simultaneously. 15. A step of forming a sidewall on a side surface of the semiconductor structure exposed by the etching after the step of forming the first metal film, and a low resistance metal layer on the first metal film. The method for manufacturing a bipolar transistor according to claim 14, further comprising a step of forming. 16. The method of manufacturing a bipolar transistor according to claim 15, wherein the low resistance metal layer is formed by a plating method.