JP3470065B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and particularly to reliability, high frequency characteristics, manufacturing yield and integration suitable for application to ultra high speed and low power consumption digital circuits. The present invention relates to a heterojunction bipolar transistor integrated circuit excellent in in-plane uniformity and reproducibility of circuit characteristics and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a heterojunction bipolar transistor (hereinafter abbreviated as HBT), a semiconductor material having a band gap larger than that of a base is used for an emitter.
High current gain without lowering the emitter injection efficiency even if the impurity concentration of the base layer is increased, and thus the base resistance can be kept low. Have many.

In particular, when a III-V group compound semiconductor is used,
Its excellent electron transport characteristics, the range of combinations of heterostructures can be expanded by the selection of materials, and the co-integration with not only electronic devices but also optical devices is possible, thus increasing the advantages. Further, among these, InP / InG lattice-matched to a semi-insulating InP substrate having a higher thermal conductivity than GaAs.
In the aAs heterostructure, it is easy to surface the base layer by selective wet etching. Since the surface recombination current of the InGaAs base layer is lower than that of GaAs, the size effect is small and a fine dimension element having a high current gain is obtained. It has excellent characteristics such as easy realization, low turn-on voltage, and high electron mobility of InGaAs. It also has excellent in-plane uniformity of turn-on voltage and high mutual conductance (gm).・ High potential as an integrated circuit for low power consumption.

Generally, in the production of compound semiconductor integrated circuits, it is important to select an element passivation film, to flatten the element, and to provide a load resistance, a base insulation for arranging a MIM capacitor (metal-insulator-metal capacitor), wiring, etc. Membrane selection. In particular, since the load resistance is accompanied by heat generation, high thermal conductivity and reliability are required for the material of the base insulating film, and the film thickness control is easy and the plasma CVD method (plasma chemical vapor deposition method) with few pinholes or A thin SiO ₂ film or Si ₃ N ₄ film deposited by sputtering is often used.

In the GaAs-based HBT, element isolation is performed by increasing the resistance of the high-concentration GaAs subcollector layer by an ion implantation method using an inert gas such as oxygen or argon, and the adhesion with GaAs is excellent. A SiO ₂ film is deposited as a passivation film to form a load resistor, lower wiring, MI
By arranging the M capacitor or the like, an integrated circuit having excellent reliability and reproducibility of characteristics can be realized.

On the other hand, in InP-based HBT, since InGaAs is a narrow bandgap material, it is difficult to increase the resistance of the subcollector layer by an inert gas ion implantation method such as GaAs. The thick subcollector layer must be completely removed by etching.

In addition to this, sputtering method and plasma CV
When a SiO ₂ film, a Si ₃ N ₄ film, or the like is deposited by the D method, an abnormal surface leak current is generated on the surface of the InP / InGaAs semiconductor due to plasma damage during the deposition, and the device characteristics are significantly deteriorated. Therefore, in order to avoid this, an organic film such as benzocyclobutene or polyimide is formed by spin coating (spin coating method), and it is used as an element passivation film.

The HBT element having a mesa step of at least 1 μm or more by the coating of this organic film is covered with the organic film whose surface is substantially flattened, and the semi-insulating InP substrate surface other than the element part is also covered with the thick organic film. Be seen. However, these organic films have a thermal conductivity that is lower than that of SiO ₂ by an order of magnitude, and are four times or more thicker. Therefore, if load resistors or wirings are arranged on these organic films, heat generated by the load resistors is generated. Is less likely to diverge, and the element characteristics change due to the rise in the HBT junction temperature, and in extreme cases, the resistance value of the load resistor changes. Therefore, in order to prevent such a change in element characteristics and a change in resistance value, the load resistor and wiring should be made of GaA.
As in the case of the s-based HBT, it is desirable to integrate on the substrate via an inorganic insulating film such as SiO ₂ . However, a further problem here is that the adhesion between the InP substrate exposed by the element isolation etching and these inorganic materials such as SiO ₂ is extremely poor. Si that is prepared by subjecting the InP substrate to normal pretreatment such as wet etching and then depositing it by sputtering or plasma CVD
The O ₂ film is likely to be peeled from the substrate during the subsequent process involving stress such as thermal history and insulating film deposition, and there is a concern that the circuit yield may be reduced.

Since the InAlAs buffer layer formed on the InP substrate to maintain the lattice matching has good adhesiveness with the inorganic material such as SiO ₂ , this is used to improve the adhesiveness between the InP substrate and the inorganic material. Can be used for.
However, this buffer layer usually exhibits n-type conductivity even in the undoped state, and it is difficult to exhibit high resistance sufficient for isolation between elements. In order to put this method into practical use, , InAlAs buffer layer It is necessary to solve the problem of high resistance.

In order to explain the problems of the InP-based HBT integrated circuit manufactured by the conventional method, I
FIG. 8 shows a schematic sectional view of an integrated circuit including nP / InGaAs HBT during a manufacturing process.

FIG. 8A shows an InGaAs HBT having an emitter electrode 1, a base electrode 2 and a collector electrode 3.
(Corresponding to the portion surrounded by the broken line in FIG. 1) is formed on the semi-insulating InP substrate 5 having the undoped InP buffer layer 4, and the subcollector layer 6 and the undoped InP buffer layer 4 are sequentially etched. Then, the first benzocyclobutene film 7 is coated on the HBT and the semi-insulating InP substrate 5, and the surface is flattened by curing (hardening treatment). The surface is sputtered with SiO ₂ A film 8 is deposited, and a load resistor 9 made of WSiN is formed on the film 8 by a sputtering method and reactive ion etching (hereinafter abbreviated as RIE).
Load resistor electrode 1 made of Ti / Pt / Au
0, lower layer wiring 11, MIM capacitor lower layer metal 12,
The state formed by vapor deposition and the lift-off method is shown.

In FIG. 8B, S is formed by plasma CVD on the entire surface of the wafer on which the structure shown in FIG. 8A is formed.
It shows a state in which the i ₃ N ₄ film 13 is deposited and the MIM capacitor cap metal 14 is formed by the vapor deposition of Ti / Pt / Au and the lift-off method.

FIG. 8 (c) shows that the benzocyclobutene is further coated and cured to form a second coating.
The benzocyclobutene film 15 of FIG.

After that, the load resistor electrode 10 and the lower layer wiring 1
1. Lower layer metal 12 and cap metal 1 of MIM capacitor
4, contact through holes are opened in the emitter electrode 1, the base electrode 2, and the collector electrode 3, and upper layer wiring made of Ti / Pt / Au is formed by vapor deposition and the lift-off method.

As can be seen from FIG. 8C, the load resistor 9 accompanied by heat generation has a low thermal conductivity and is a composite film of a thick benzocyclobutene film 7 (thickness of at least 1 μm or more) and a SiO ₂ film 8. It is located on the top of the building and it is relatively difficult to dissipate the generated heat. In addition to this, as can be seen from FIG. 8C, the insulating multilayer film is thickly deposited (thickness of at least 2 μm or more) as a whole on the emitter electrode 1 which needs to have a particularly fine dimension. It is difficult to open fine contact through holes by dry etching.

[0016]

The problem to be solved by the present invention is that the heat generated by the load resistor can be efficiently dissipated to the substrate side, and the contact through hole to the emitter electrode can be formed. An HBT integrated circuit having a structure in which the etching depth required for formation is shallower than that of the conventional technique,
It is an object of the present invention to provide a method for manufacturing such an HBT integrated circuit in a state where the uniformity and reproducibility of the integrated circuit characteristics on the wafer surface are good and with a high yield.

[0017]

The above problems can be solved by including a step of increasing the adhesion between the semiconductor substrate and the inorganic insulating film in the step of manufacturing the HBT integrated circuit.

In the present invention, the following first and second methods are used as means for improving the above-mentioned adhesion.

The first method is electron cyclotron resonance reactive ion etching (hereinafter abbreviated as ECR-RIE) using a mixed gas of a halogen gas and an inert gas,
This is a method using subsequent wet etching.
That is, the surface of the semiconductor substrate before the formation of the inorganic insulating film is etched by the ECR-RIE and then wet-etched to form the inorganic insulating film on the surface of the semiconductor substrate after such etching treatment. In this case, InA
The lAs buffer layer is removed by the ECR-RIE and does not hinder the isolation between elements.

The characteristics of ECR-RIE are a plasma generation source utilizing electron cyclotron resonance capable of generating high density plasma with a reaction gas pressure as low as 0.1 to 1 mTorr, and a bias potential to the substrate by applying high frequency to the substrate. Is given, the ion energy incident on the substrate can be optimized. Therefore, a normal parallel plate type RI
The plasma density is higher than that of E, and uneven portions are formed on the surface of the etched semiconductor substrate. A mechanism for improving the adhesiveness is conceivable in which the contact area with the inorganic insulating film such as SiO ₂ deposited on the irregularities by the sputtering method is increased and the adhesiveness with the semiconductor substrate is improved. However, this ion etching alone causes a minute leak current due to damage on the surface of the semiconductor substrate.To prevent this, an additional treatment of etching the substrate surface by about 50 nm with a diluted hydrochloric acid wet etching solution. Is required.

In the second method, the InAlAs buffer layer is not removed, and the resistance of the layer is increased by the combination of the oxygen ion implantation step and the high temperature annealing step of the base layer so as not to hinder the isolation between elements. At the same time, it is a method of using as an intermediate layer for enhancing the adhesiveness between the substrate and the inorganic insulating film.

In the embodiment of the present invention, a passive element including a load resistor is formed on the inorganic insulating film formed by the above method. In the HBT integrated circuit having such a structure, the heat generated by the load resistor can be efficiently dissipated to the substrate side through the thin (for example, 300 nm thick) inorganic insulating film having high thermal conductivity. Therefore, it is possible to prevent a change in element characteristics due to an increase in element temperature.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION InP /
The present invention is not limited to this, although it will be described by way of examples relating to InGaAs HBT integrated circuits.

Example 1 First, an example using the first method will be described.

InP / InGaAs in this embodiment
An outline of the cross-sectional structure of the HBT integrated circuit is shown in FIG. In FIG. 1, 1 is an emitter electrode, 2 is a base electrode, 3 is a collector electrode, 4 is an undoped InP buffer layer, 5 is a semi-insulating InP substrate, 6 is a subcollector layer, 7 is a first benzocyclobutene film, 8 is a SiO ₂ film, 9 is a load resistor, 1
Reference numeral 0 is a load resistor electrode, 11 is a lower layer wiring, 12 is a MIM capacitor lower layer metal, 13 is a Si ₃ N ₄ film, 14 is a MIM capacitor cap metal, 15 is a second benzocyclobutene film, and 16 is an upper layer wiring. . In the figure, InP / having emitter electrode 1, base electrode 2 and collector electrode 3
The InGaAs HBT is surrounded by a broken line.

InP / InGaAs HB shown in FIG.
The T integrated circuit is shown in FIG.
nGaAs HBT integrated circuit (hereinafter referred to as conventional example)
As is clear from comparison with S, the interposition between the load resistor 9 and the semi-insulating InP substrate 5 is thin (for example, 300 nm) in this embodiment, and S having a high thermal conductivity is used.
Although only the iO ₂ film 8 is used, in the conventional example, S
The iO ₂ film 8 and the benzocyclobutene film 7 having a large thickness (for example, 1.5 μm) and a low thermal conductivity are overlapped with each other. Therefore, in the case of the present embodiment, the heat generated by the load resistor 9 diffuses into the InP substrate 5 more quickly than in the case of the conventional example, and causes the change in the element characteristics due to the rise in the element temperature. Does not mean Further, when the contact through hole for making contact with each electrode of the HBT in the integrated circuit is opened by dry etching, the depth of dry etching is smaller in the embodiment of the present invention than in the conventional example. As a result, the thickness of the second benzocyclobutene film (15 in FIG. 8C) is shallow, and the dry etching for the opening is facilitated by that amount as compared with the conventional example.

InP / InG according to the present invention shown in FIG.
The aAs HBT integrated circuit can be manufactured with a high manufacturing yield by the method for manufacturing a semiconductor integrated circuit according to the present invention, and the in-plane uniformity and reproducibility of element performance at that time are both excellent. Further, the HBT integrated circuit manufactured in this manner is excellent in both reliability and high frequency characteristics.

The InP according to the present invention shown in FIG. 1 will be described below.
Main steps of manufacturing the / InGaAs HBT integrated circuit by the method for manufacturing a semiconductor integrated circuit according to the present invention will be described in detail.

FIG. 2 is a diagram for explaining the steps from the step of forming the first benzocyclobutene film to the step of forming the SiO ₂ film, with reference to sectional views of the integrated circuit.

FIG. 2A shows a state in which the first benzocyclobutene film 7 is formed on the substrate after the HBT is formed. This HBT was manufactured by the following method.
That is, the reduced pressure M is formed on the Fe-doped semi-insulating InP substrate 5.
AndoV InP by OVPE (MOCVD) method
Buffer layer 4, n ⁺ -InGaAs subcollector layer 6 containing high-concentration n-type impurities for forming ohmic resistance in the collector, collector layer composed of InP and InGaAs, high-concentration carbon (C) acceptor impurity doping The p ⁺ InGaAs base layer, the n-InP emitter layer doped with the n-type impurity, and the n ⁺ -InGaAs emitter cap layer doped with the high-concentration n-type impurity for forming an ohmic resistance in the emitter are sequentially epitaxially grown. To produce a HBT laminated structure.

Next, after exposing the C-doped InGaAs base layer by selective emitter mesa etching, high temperature annealing for recovering the C acceptor hole concentration passivated by hydrogenation during epitaxial growth was performed and activated. A base electrode 2 made of Pt / Ti / Au is formed on the outer base layer, and an emitter electrode 1 made of Ti / Pt / Au is formed on the n ⁺ -InGaAs emitter cap layer by vapor deposition and lift-off, respectively. After that, p ⁺ -
N exposed by selective mesa etching of InGaAs base layer and InGaAs / InP collector layer
^A collector electrode 3 made of Ti / Pt / Au is formed on the ⁺ -InGaAs subcollector layer by vapor deposition and a lift-off method.

Further, for element isolation, the n ⁺ -InGaAs subcollector layer 6 between elements is removed by selective wet etching to expose the undoped InP buffer layer 4. Then, the first benzocyclobutene film 7 is formed on the entire surface of the wafer by spin coating and curing at 250 ° C., and the state shown in FIG. The first benzocyclobutene film 7 acts as a passivation film for the HBT manufactured by the above method. Benzocyclobutene is excellent in flatness, and the surface of the first benzocyclobutene film 7 is almost flat, and when forming wiring on this surface, it is possible to avoid occurrence of defects such as disconnection of wiring. The use of benzocyclobutene as the organic passivation film material is effective in improving the manufacturing yield.

FIG. 2B shows a portion of the HBT of the first benzocyclobutene film 7 which is irrelevant to the passivation, and is exposed by the undoped In.
It shows a state in which the P buffer layer has been removed and a process for improving the adhesion with SiO ₂ has been performed on the substrate. In this case, the benzocyclobutene film was removed by a method in which the wafer was subjected to resist patterning covering the HBT element portion and at least benzocyclobutene outside the element portion was removed by etching with SF ₆ -RIE. The thickness of the benzocyclobutene film 7 in this case is about 1.5 μm.
A method of removing the undoped InP buffer layer exposed by removing the film and performing a treatment for improving the adhesion with SiO ₂ on the semi-insulating InP substrate 5 is a feature of the present invention. The method is as follows.

First, using an ECR-RIE with a chlorine / argon (C1 ₂ / Ar) mixed gas, Andove InP is used.
After removing the buffer layer (thickness 100 nm) by etching
The P substrate 5 is also slightly (about 50 nm) etched.
Even if the etching is finished at the time when the Andove InP buffer layer is removed, the surface of the semi-insulating InP substrate 5 is already in the etched state, so that the adhesion of the surface to SiO ₂ is already improved. However, since the Andove InP buffer layer exhibits n-type conductivity, the InP substrate 5 is slightly etched as described above to ensure the removal of the buffer layer in order to completely separate the elements. Is preferred. In the above etching, a microwave of 500 W and a high frequency for bias application of 25 W were used.

Next, the In etched by the above method
The surface of the P substrate is wet-etched to a depth of about 50 nm using a diluted hydrochloric acid / phosphoric acid wet etching solution in order to remove damage on the surface of the InP substrate due to etching.

By combining such two kinds of etching treatments, it is possible to improve the adhesion between the substrate and the inorganic insulating film such as SiO ₂ deposited on the substrate by the sputtering method or the plasma CVD method. Become.

FIG. 2C shows a state in which an underlaying SiO ₂ film 8 is deposited to a thickness of 300 nm on the entire surface of the InP substrate 5 including the first benzocyclobutene film 7 which is a device passivation film by a sputtering method. Shows.

FIG. 3 is a diagram for explaining, from a step of depositing WSiN, which is a material of a resistor, to a step of forming a metal pattern such as a lower layer wiring, by a sectional view of an integrated circuit.

FIG. 3 (a) shows that, on the SiO ₂ film 8,
It shows a state in which a continuous WSiN thin film for load resistance is deposited by a sputtering method. The thin WSiN film used in this embodiment has a thickness of 100 nm.

FIG. 3B shows a step of forming a load resistor 9 by performing resist patterning on the WSiN thin film and etching away the unnecessary WSiN thin film by SF ₆ -RIE. Since the underlying SiO ₂ film 8 has a low etching rate with respect to SF ₆ -RIE, the WSiN film can be over-etched (the SiO ₂ film 8 is hardly etched even if the etching is excessive to some extent, and practically no etching is performed). It will not cause any problems).

In FIG. 3C, the lower layer wiring 11, the MIM capacitor lower layer metal 12, the load resistor 9 are formed on the SiO ₂ film 8.
Shown above is a state in which the load resistor electrode 10 is formed simultaneously by vapor deposition of a Ti / Pt / Au laminated metal and the lift-off method. The total thickness of Ti / Pt / Au laminated metal is 2
It is 60 nm.

FIG. 4 is a diagram for explaining the steps from the Si ₃ N ₄ film deposition step to the surface flattening step with benzocyclobutene by means of a sectional view of an integrated circuit.

In FIG. 4A, plasma CVD is performed on the SiO ₂ film 8 and the laminated metal pattern arranged thereon.
₃ shows a state in which the Si ₃ N ₄ film 13 is entirely deposited by the method.

In FIG. 4B, the MIM capacitor cap metal 14 is formed on the Si ₃ N ₄ film 13 deposited on the MIM capacitor lower layer metal 12 by the vapor deposition of Ti / Pt / Au laminated metal and the lift-off method. It shows the state.
The total thickness of the Ti / Pt / Au laminated metal is 400 nm.

In FIG. 4C, a second benzocyclobutene film 15 is coated on the entire surface of the wafer to reduce the cross capacitance between the lower layer wiring 11 and the upper layer wiring (16 in FIG. 1), and the curing is performed. The ring is shown, and the unnecessary portion is removed by etching using SF ₆ -RIE.

FIG. 5 is a diagram for explaining the step of forming a contact through hole in the lower layer wiring and the like and the step of forming a contact through hole in the emitter electrode and the like with reference to sectional views of an integrated circuit.

In FIG. 5A, resist opening patterning is performed on the lower layer wiring 11, the load resistor electrode 10 and the MIM capacitor cap metal 14 to form the second benzocyclobutene film 15 and the Si ₃ N ₄ film 13. It shows a state in which contact through holes are formed for each of them by removing with SF ₆ -RIE.

In FIG. 5B, after resist opening patterning is further performed on the emitter electrode 1, the collector electrode 3 and the base electrode 2, the Si ₃ N ₄ film 13 and the Si ₃ N ₄ film 13 are formed by C ₂ F ₆ -RIE. The state where the SiO ₂ film 8 is removed by etching the first benzocyclobutene film 7 by SF ₆ -RIE to form contact through holes on each electrode is shown (to the base electrode 2). The contact through holes are in a different cross section, so they are not shown here).

On the integrated circuit in the state shown in FIG. 5B, the upper wiring 16 (shown in FIG. 1) made of Ti / Pt / Au having a thickness of 1.3 μm is formed by vapor deposition and lift-off method. Therefore, In according to the present invention shown in FIG.
Obtain a P / InGaAs HBT integrated circuit.

(Embodiment 2) Next, an embodiment using the second method will be described.

InP / InGaAs in this embodiment
The main part of the method for manufacturing the HBT integrated circuit is shown by the schematic sectional views of FIGS. 6 and 7.

FIG. 6 shows InP / I on a semi-insulating InP substrate.
It shows a state in which an nGaAs HBT (enclosed by a broken line in the drawing) is formed. This InP / InGaAs HBT was manufactured by the following method. That is, the reduced pressure MOVPE (MOCV) is formed on the Fe-doped semi-insulating InP substrate 17.
Undoped InAlAs buffer layer 1 by the D) method
8. n ⁺ -InGaAs subcollector layer 1 containing high-concentration n-type impurities for forming ohmic resistance in collector
9, n ⁺ -InP collector layer 20 and undoped InGaA
s collector layer 21 and p ⁺ -InGaA doped with high concentration carbon acceptor impurities
s base layer 22, N-In doped with n-type impurities
A PBT emitter layer 23 and an n ⁺ -InGaAs emitter cap layer 24 containing a high concentration n-type impurity for forming an ohmic resistance in the emitter were sequentially epitaxially grown to form an HBT laminated structure.

Next, by selective mesa etching, n ⁺ -In
GaAs emitter cap layer 24, N-InP emitter layer 23, carbon-doped p ⁺ -InGaAs base layer 22, undoped InAlAs / N ⁺ InP collector layer (21 /
20) is partially removed to expose the emitter, base and collector ohmic layers. Furthermore, n ⁺ -InG
The aAs sub-collector layer 19 is subjected to inter-element isolation mesa etching to expose the undoped InAlAs buffer layer 18, and the state shown in FIG. 6 is obtained.

FIG. 7 shows the underlay S from the oxygen ion implantation step.
Processes up to the iO ₂ film deposition process are shown in sectional views of the device.

FIG. 7A shows n ⁺ -InG in FIG.
aAs emitter cap layer 24, N-InP emitter layer 23, carbon-doped p ⁺ -InGaAs base layer 22, undoped InAlAs / N ⁺ InP collector layer (21, 2)
0) and the resist 25 for protecting the n ⁺ -InGaAs subcollector layer 19 are patterned, and then oxygen ions are implanted into the InAlAs buffer layer 18 exposed by the inter-device isolation mesa etching.

In FIG. 7B, after removing the resist 25 with an organic solvent, high temperature dehydrogenation annealing is performed to recover the carrier concentration of the carbon-doped p ⁺ -InGaAs base layer, and then the emitter, base, The state where the collector electrodes (1, 2, 3) are formed by vapor deposition and lift-off method is shown. This high-temperature dehydrogenation anneal increases the resistance of the InAlAs buffer layer into which the oxygen ions have been implanted, and does not hinder the isolation between elements.

In this embodiment, the resistance of the InAlAs buffer layer is increased by high temperature dehydrogenation annealing of the base layer, but such high resistance can also be achieved by a general high temperature annealing process.

In order to realize the state shown in FIG. 7C, first, the first benzocyclobutene film 7 is applied to the entire surface of the wafer by spin coating, and InP /
It is used as a passivation film on the semiconductor surface of InGaAs HBT. After that, resist patterning for protecting the element portion is performed, at least the benzocyclobutene film outside the element portion is removed by etching with SF ₆ -RIE, and the resistance of InAl is increased by the oxygen ion implantation and high temperature annealing.
The As buffer layer 18 is exposed. Then, SiO ₂ is deposited on the entire surface of the wafer including the benzocyclobutene film by the sputtering method to obtain the state shown in FIG. 7C. The benzocyclobutene used in this example is excellent in flatness and can avoid troubles such as disconnection of wiring in the wiring process and is practically useful.

In this embodiment, the InAlAs buffer layer 18 is used.
Although an example in which oxygen ions are used to increase the resistance of I was shown, even if ion implantation of an inert element such as helium (He) or argon (Ar), which is expected to have the same effect, is used, I
Higher resistance of the nAlAs buffer layer 18 can be realized.

The state shown in FIG. 7C corresponds to the state shown in FIG. 2C in the first embodiment, and the subsequent steps in this embodiment are the same as those in the first embodiment. It is possible to carry out.

In Examples 1 and 2 described above, since the treatment for improving the adhesion between the InP substrate and the SiO ₂ film is performed, there is no defect that the SiO ₂ film peels from the substrate during the process. As a result, this integrated circuit can be manufactured with a high manufacturing yield. Further, since the load resistor is formed on the substrate via the thin SiO ₂ film having high thermal conductivity, the deposition condition of the resistor is likely to be uniform within the wafer surface, and is easy to control. Therefore, the in-plane uniformity and reproducibility of the characteristics of the manufactured integrated circuit are improved. Further, in this integrated circuit, the heat generated by the load resistor is thin and has high thermal conductivity.
_Since it easily diffuses into the substrate through the _two films, there is no problem of fluctuations in device characteristics due to temperature rise of the device, and this integrated circuit has high performance and high reliability.

Further, the present invention not only has a remarkable effect in the above-mentioned embodiment, but generally, the adhesiveness between the semiconductor substrate (for example, InP substrate) and the inorganic insulating film is insufficient, which causes a defect. The same effect can be obtained for such an integrated circuit manufacturing process.

[0063]

As described above, by implementing the present invention, it is possible to solve the problems of the prior art by providing an ultra-high speed / low power consumption HBT integrated circuit having high performance and high reliability. The wafer can be manufactured and provided by a manufacturing method which has excellent in-plane uniformity and reproducibility of the wafer and has a high manufacturing yield.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an InP / InGaAs HBT integrated circuit according to the present invention.

2 (a) to (c) are InP / I in Example 1. FIG.
in the manufacturing process of the nGaAs HBT integrated circuit diagrams illustrating the cross-sectional view of a step of the integrated circuit from the step of forming the first benzocyclobutene film to the SiO ₂ film formation.

3 (a) to (c) are InP / I in Example 1. FIG.
It is a figure explaining the process from the deposition process of WSiN which is a material of a resistor to the metal pattern formation process of a lower layer wiring etc. in the manufacturing process of a nGaAs HBT integrated circuit by sectional drawing of an integrated circuit.

4 (a) to (c) are InP / I in Example 1. FIG.
Si ₃ N ₄ during manufacturing process of nGaAs HBT integrated circuit
It is a figure explaining the process from a film deposition process to the surface planarization process by benzocyclobutene with the cross-sectional view of an integrated circuit.

5 (a) and 5 (b) are InP / I in Example 1. FIG.
It is a figure explaining the contact through-hole formation process to a lower layer wiring etc. and the contact through-hole formation process to an emitter electrode etc. in the manufacturing process of an nGaAs HBT integrated circuit by the cross-sectional view of an integrated circuit.

FIG. 6 is a graph showing the result of Example 2 on a semi-insulating InP substrate.
It is a figure which shows the state which formed nP / InGaAs HBT.

7A to 7C are diagrams showing steps from the oxygen ion implantation step to the underlay SiO ₂ film deposition step in the _second embodiment.

8 (a) to 8 (c) show InP /
It is a figure explaining the main process of manufacturing an InGaAs HBT integrated circuit by the sectional view of an integrated circuit.

[Explanation of symbols]

1 ... Emitter electrode, 2 ... Base electrode, 3 ... Collector electrode, 4 ... Undoped InP buffer layer, 5 ... Semi-insulating property I
nP substrate, 6 ... Sub-collector layer, 7 ... First benzocyclobutene film, 8 ... SiO ₂ film, 9 ... Load resistor, 10 ...
Load resistor electrode, 11 ... Lower layer wiring, 12 ... MIM capacitor lower layer metal, 13 ... Si ₃ N ₄ film, 14 ... MIM capacitor cap metal, 15 ... Second benzocyclobutene film, 16 ... Upper layer wiring, 17 ... Half Insulating InP substrate, 18
... undoped InAlAs buffer layer, 19 ... n ⁺ -In
GaAs sub-collector layer, 20 ... N ⁺ -InP collector layer, 21 ... Undoped InGaAs collector layer, 22 ...
p ⁺ -InGaAs base layer, 23 ... N-InP emitter layer, 24 ... n ⁺ -InGaAs emitter cap layer, 25
... resist.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 29/205 29/737 (56) References JP-A-5-212871 (JP, A) JP-A-7-202124 (JP, A) JP-A-5-55202 (JP, A) JP-A-10-50720 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/06

Claims (4)

(57) [Claims] 1. A semiconductor integrated circuit in which an active element and a passive element are integrated on a semiconductor substrate, the semiconductor being the active element.
Surface is all parts except contact through hole opening
Directly covered with an organic passivation film at
In addition, the organic passivation film is covered with an inorganic insulating film.
The passive element is integrated on the semiconductor substrate via only the inorganic insulating film. 2. A method of manufacturing a semiconductor integrated circuit according to claim 1 Symbol placement, the semiconductor substrate is a semiconductor substrate having a buffer layer, after forming the active element in the buffer layer, on to the semiconductor substrate The organic passivation film is formed, the organic passivation film at the passive element formation planned site is removed, and the buffer layer at the site is subjected to electron cyclotron resonance reactive ion etching using a mixed gas of a halogen gas and an inert gas. Removing, wet etching the surface of the semiconductor substrate exposed at the site, forming the inorganic insulating film on the semiconductor substrate including the site, and forming the passive element on the inorganic insulating film at the site. A method of manufacturing a semiconductor integrated circuit, comprising: 3. The method of manufacturing a semiconductor integrated circuit according to claim 2 , wherein the mixed gas of the halogen gas and the inert gas is a mixed gas of chlorine gas and argon gas. 4. A manufacturing method of a semiconductor integrated circuit according to claim 2 or 3, wherein the use of hydrochloric acid etchant in the wet etching.