CN112259459A - Gallium nitride-based electronic device and manufacturing method thereof - Google Patents

Gallium nitride-based electronic device and manufacturing method thereof Download PDF

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CN112259459A
CN112259459A CN202011128395.5A CN202011128395A CN112259459A CN 112259459 A CN112259459 A CN 112259459A CN 202011128395 A CN202011128395 A CN 202011128395A CN 112259459 A CN112259459 A CN 112259459A
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forming
gate
ohmic contact
layer
mark
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郭富强
黄森
王鑫华
魏珂
刘新宇
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

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Abstract

The present disclosure is a gallium nitride-based electronic device and a method of fabricating the same, the method comprising: forming an Al (In, Ga) N/GaN heterostructure on a substrate; forming a passivation layer on the Al (In, Ga) N/GaN heterostructure; manufacturing a groove-shaped mark on the passivation layer; etching the passivation layer by using the groove-shaped mark as an alignment mark to form a gate groove and depositing a gate medium; making a metal mark by using the groove-shaped mark as an alignment mark; forming an ohmic contact layer by using the metal mark as an alignment mark; isolating; a gate metal is deposited over the gate dielectric. The method adopts the groove-shaped mark, avoids the pollution of metal to the medium growth before the high-temperature gate medium deposition, improves the gate medium deposition process to 500-1000 ℃, obviously improves the reliability of the gate, and ensures that the GaN-based device can be manufactured on an Au-containing process line or a complementary metal oxide semiconductor process line or two process lines by double selection of a high-temperature Au-containing ohmic alloy technology and a low-temperature Au-free ohmic technology.

Description

Gallium nitride-based electronic device and manufacturing method thereof
Technical Field
The disclosure belongs to the technical field of semiconductor devices, and relates to a gallium nitride-based electronic device and a manufacturing method thereof.
Background
The GaN-based metal insulator semiconductor high electron mobility transistor (MIS/MOS-HEMT) has the excellent characteristics of high output power density, high frequency and high voltage, high temperature resistance, radiation resistance and the like, and has great application potential in the application fields of GaN-based power electronic devices, microwave devices and the like.
At present, most of gallium nitride-based enhanced devices are manufactured by adopting a gate-last process, and the manufacturing process flow comprises the following steps: firstly, forming a source ohmic contact electrode and a drain ohmic contact electrode; then depositing and annealing the gate dielectric; and finally forming the Schottky gate electrode. However, such processes can only deposit gate dielectrics by low temperature techniques such as Plasma Enhanced Chemical Vapor Deposition (PECVD) or Atomic Layer Deposition (ALD) processes, where the deposition temperature is below 350 ℃, resulting in more defects in the gate dielectric, e.g., PECVD-SiNX、ALD-Al2O3Isodielectric, but they all suffer from a number of problems, low temperature PECVD-SiNXBecause of the high H content, the high temperature capability, the compactness, the element chemical ratio and the element purity are poor, and the Al grown by ALD has good performance2O3The Time-dependent dielectric Breakdown (TDDB) property is poor due to a large amount of defects such as Al-Al and Al-O-H. These defects seriously affect the stability and long-term reliability of GaN-based electronic devices.
While the gate dielectric is deposited at high temperature, e.g. PEALD-SiNX、LPCVD-SiNX、RTCVD-SiNXAnd because the growth temperature is higher (500 ℃ -1000 ℃), the defects are fewer, and the method is very suitable for manufacturing a GaN-based device with high grid reliability. However, the use of the high-temperature gate dielectric requires adjustment of the process flow, so that the GaN-based device can be manufactured on an Au-containing process line or a Complementary Metal Oxide Semiconductor (CMOS) process line, and the two processes can be combined, namely, the CMOS process is adopted for carrying out the former process, and then the latter process is manufactured on the Au-containing process line,the respective advantages of low ohmic contact resistance of Au-containing process and high reliable gate dielectric of CMOS process are fully utilized, and a process foundation is laid for manufacturing high-performance GaN-based electronic devices.
Disclosure of Invention
In view of the above, the present disclosure is directed to a gallium nitride-based electronic device and a method for fabricating the same, which at least partially solve at least one of the above problems.
In order to achieve the above object, as one aspect of the present disclosure, there is provided a method of fabricating a gallium nitride-based electronic device, including:
forming an Al (In, Ga) N/GaN heterostructure on a substrate;
forming a passivation layer on the Al (In, Ga) N/GaN heterostructure;
manufacturing a groove-shaped mark on the passivation layer;
etching the passivation layer by using the groove-shaped mark as an alignment mark to form a gate groove;
forming a gate dielectric in the gate trench and on the passivation layer;
making a metal mark by using the groove-shaped mark as an alignment mark;
forming an ohmic contact layer by using the metal mark as an alignment mark;
isolating the manufactured device; and
a gate metal is formed on the gate dielectric.
As another aspect of the present disclosure, there is also provided a gallium nitride-based electronic device obtained by the above-described manufacturing method.
Based on the above technical solution, the gallium nitride-based electronic device and the manufacturing method thereof of the present disclosure have at least one or a part of the following advantages over the prior art:
1. the gallium nitride-based electronic device and the manufacturing method thereof are realized by the high-electron-mobility transistor device based on the gate-first process and compatible with the high-temperature (700-900 ℃) ohmic alloy technology and the low-temperature (300-700 ℃) gold-free ohmic technology and the manufacturing method thereof, metal does not need to be introduced when the gate medium is deposited by opening the etching groove-shaped mark, the gate medium is deposited first, the high-quality gate medium can be obtained by high-temperature technology deposition, and the reliability of the device is favorably guaranteed.
2. According to the gallium nitride-based electronic device and the manufacturing method thereof, the groove shape without metal and the metal marking are adopted, the groove shape marking is used for avoiding the pollution of the metal to the medium growth before the high-temperature gate medium deposition, the gate medium deposition process can be improved to 500-1000 ℃ from the traditional temperature below 350 ℃, and the reliability of the gate can be obviously improved.
3. According to the gallium nitride-based electronic device and the manufacturing method thereof, high temperature and low temperature are provided for ohmic contact, and double selection of Au-containing and Au-free processes is achieved, so that the flexibility of the processes is expanded. The process can realize the simultaneous manufacture of the GaN-based enhanced electronic device on the Au-containing process line and the CMOS process line, fully utilizes the respective advantages of the low ohmic contact resistance of the Au-containing process and the high reliable gate dielectric of the CMOS process, and lays a process foundation for the manufacture of the high-performance GaN-based electronic device.
4. According to the gallium nitride-based electronic device and the manufacturing method thereof, the high-temperature gate medium is compatible with a high-temperature Au-containing ohmic alloy technology and a low-temperature Au-free ohmic alloy technology, ohmic contact resistance is effectively reduced, a mainstream Au-containing ohmic contact GaN device process and a Si-CMOS process are compatible, a GaN-based power electronic device with high reliability and low on-resistance can be manufactured, and feasible schemes are provided for industrialization.
Drawings
For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings, wherein the device structures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. In the drawings:
FIG. 1 is a flow chart of a method of fabricating a gallium nitride-based electronic device according to an embodiment of the present disclosure;
FIG. 2 is a process flow diagram for fabricating gallium nitride-based electronic devices in accordance with an embodiment of the present disclosure;
fig. 3 is a schematic structural view of a gallium nitride-based electronic device fabricated corresponding to the various process steps in fig. 2.
Description of reference numerals:
1-a substrate; 2-a GaN layer; a 3-Al (In, Ga) N layer; 4-a passivation layer; 5-groove-shaped marking; 6-a gate dielectric; 7-metal marking; an 8-ohmic contact layer; 9-gate metal.
Detailed Description
Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings and examples to assist those skilled in the art in fully understanding the objects, features and effects of the present disclosure. Exemplary embodiments of the present disclosure are illustrated in the drawings, but it should be understood that the present disclosure can be embodied in other various forms and should not be limited to the embodiments set forth herein. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure. In addition, the various embodiments provided below of the present disclosure and technical features in the embodiments may be combined with each other in any manner.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, when used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components. All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
The invention discloses a GaN-based electronic device and a manufacturing method thereof, wherein a high-quality gate dielectric grown at high temperature is applied to the device, the reliability of the device is improved, meanwhile, the GaN-based enhanced electronic device is manufactured on an Au-containing process line and a CMOS process line, and the respective advantages of the low ohmic contact resistance of the Au-containing process and the high-reliability gate dielectric of the CMOS process are fully utilized, so that the process foundation is laid for manufacturing the high-performance GaN-based electronic device.
As shown in fig. 1, fig. 1 is a flow chart of a method of fabricating a gallium nitride-based electronic device according to an embodiment of the present disclosure, the method comprising:
forming an Al (In, Ga) N/GaN heterostructure on a substrate;
forming a passivation layer on the Al (In, Ga) N/GaN heterostructure;
manufacturing a groove-shaped mark on the passivation layer;
etching the passivation layer by using the groove-shaped mark as an alignment mark to form a gate groove;
forming a gate dielectric in the gate trench and on the passivation layer;
making a metal mark by using the groove-shaped mark as an alignment mark;
forming an ohmic contact layer by using the metal mark as an alignment mark;
isolating the manufactured device; and
a gate metal is formed on the gate dielectric.
In some embodiments of the present disclosure, the step of forming an Al (In, Ga) N/GaN heterostructure, the Al (In, Ga) N serving as a barrier layer, includes at least one of the group consisting of an AlGaN barrier layer, an AlInN barrier layer, or an AlInGaN barrier layer.
In some embodiments of the present disclosure, in the step of forming a passivation layer, the passivation layer is SiN, AlN or SiO2A single dielectric layer made of any one of the above materials, or SiN, AlN or SiO2At least two of them are superposed to form a composite dielectric layer; the method for forming the passivation layer comprises a chemical vapor deposition method, an atomic layer deposition method or a plasma enhanced chemical vapor deposition method.
In some embodiments of the present disclosure, in the step of forming the gate dielectric, the material adopted by the gate dielectric includes SiN, SiO2At least one of AlON, AlSiO, AlSiN or SiON, and the thickness of the gate dielectric is 5-30 nm, such as 5 nm, 10 nm, 15 nm, 20 nm, or 30 nm.
In some embodiments of the present disclosure, in the step of forming the gate dielectric, the growth temperature of the gate dielectric is 500 to 1000 ℃, for example, 500 ℃, 600 ℃, 700 ℃, 800 ℃, 900 ℃, 1000 ℃.
In some embodiments of the present disclosure, the method of forming the gate dielectric includes atomic layer deposition, chemical vapor deposition, rapid thermal chemical vapor deposition, molecular beam epitaxy, or metal organic chemical vapor deposition.
In some embodiments of the present disclosure, in the step of forming an ohmic contact layer, the ohmic contact layer includes an ohmic contact layer containing gold or an ohmic contact layer not containing gold.
In some embodiments of the present disclosure, when the ohmic contact layer is an ohmic contact layer containing gold, the temperature at which the ohmic contact layer is formed is 700 ℃ to 900 ℃, for example, 700 ℃, 750 ℃, 800 ℃, 850 ℃, 900 ℃.
In some embodiments of the present disclosure, all of the fabrication steps of the gallium nitride-based electronic device are completed on a gold-containing process line; alternatively, it is done on a CMOS process line before the step of growing the gate dielectric is done, and on a gold-containing process line after the step of growing the gate dielectric is done.
In some embodiments of the present disclosure, when the ohmic contact layer is a gold-free ohmic contact layer, the temperature at which the ohmic contact layer is formed is 300 ℃ to 700 ℃, for example, may be 300 ℃, 400 ℃, 500 ℃, 600 ℃, 700 ℃; all the manufacturing steps of the gallium nitride-based electronic device are completed on a complementary metal oxide semiconductor process line.
In some embodiments of the present disclosure, the isolation method employed in the isolating step includes mesa isolation or implant isolation.
In some embodiments of the present disclosure, in the step of forming the gate metal, the gate metal is made of a material selected from the group consisting of Ni/Au, Pt/Ti/Au, Al/Ni/Au or TiN.
The present disclosure also discloses a gallium nitride-based electronic device obtained by the above-mentioned manufacturing method.
The gallium nitride-based electronic device and the method for manufacturing the same proposed by the present disclosure are described in detail below with reference to fig. 2 to 3, so as to better understand the technical solution of the present disclosure and the achieved beneficial effects.
Referring to fig. 2-3, the present embodiment provides a method for fabricating a gallium nitride-based electronic device, including:
step 1: a substrate 1 is provided.
Step 2: growing a GaN layer 2 and an Al (In, Ga) N layer 3 on a substrate 1 respectively to form an Al (In, Ga) N/GaN heterostructure;
the Al (In, Ga) N barrier layer may be an AlGaN or AlInN ternary alloy barrier layer, or an AlInGaN quaternary alloy barrier layer, and specifically includes at least one of the group consisting of an AlGaN barrier layer, an AlInN barrier layer, and an AlInGaN barrier layer.
And step 3: growing a passivation layer 4 on the Al (In, Ga) N/GaN heterostructure, as shown In figure 3 (a);
wherein, the passivation layer 4 is SiN, AlN or SiO2A single dielectric layer made of any one of the above materials, or SiN, AlN or SiO2At least two of them are superposed to form a composite dielectric layer; the growth passivation layer 4 may be deposited using chemical vapor deposition (LPCVD), Atomic Layer Deposition (ALD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) methods.
And 4, step 4: making a groove mark 5 on the passivation layer 4, as shown in fig. 3 (b), the groove mark 5 may be a cross mark; the depth of the channel shaped markings 5 is greater than 150 nm.
And 5: etching a gate groove on the passivation layer 4 by taking the groove-shaped mark 5 as an alignment mark, and growing a high-temperature gate dielectric 6 in the gate groove and on the passivation layer, as shown in (c) of fig. 3;
wherein, the high-temperature gate dielectric 6 can be SiN or SiO2AlON, AlSiO, AlSiN or SiON, adopting ALD, LPCVD, Rapid Thermal Chemical Vapor Deposition (RTCVD), Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD) technology to grow, the growth temperature is 500-1000 ℃, and the thickness is between 5 and 30 nanometers.
Step 6: the groove-shaped mark 5 is used as an alignment mark to manufacture a metal mark 7, the metal mark 7 is used as a layout alignment mark in the subsequent layout, and the metal mark 7 can also be a cross mark;
and 7: etching the Al (In, Ga) N layer 3 and the passivation layer 4 on two sides of the gate dielectric 6 to form an ohmic contact groove, and forming an Au-containing or Au-free ohmic contact layer 8 In the ohmic contact groove; as shown in (d) of FIG. 3;
wherein, the Au-containing ohmic contact adopts a lift-off process and an alloying process with the temperature of 700 ℃ to 900 ℃; the Au-free ohmic contact adopts lift-off process and alloying process with the temperature of 300-700 ℃; if the Au-containing ohmic contact is adopted, all the manufacturing steps of the gallium nitride-based electronic device can be completed on an Au-containing process line; or the gate dielectric and the preceding steps are completed in a CMOS process line, and the subsequent steps of the gate dielectric are completed in an Au-containing process line; if the Au-free ohmic contact is adopted, all the manufacturing steps of the gallium nitride-based electronic device can be completed in a CMOS process line.
And 8: and carrying out isolation operation on the obtained device, wherein the isolation adopts mesa isolation or implantation isolation.
And step 9: depositing gate metal 9 on the gate dielectric 6 after the isolation operation to obtain a structure shown as (e) in fig. 3, namely manufacturing the gallium nitride-based electronic device; the gate metal is made of any one of the group consisting of Ni/Au, Pt/Ti/Au, Al/Ni/Au or TiN.
It should be noted that while the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that the present disclosure is not limited to the above-described embodiments, and that various changes and modifications may be made therein without departing from the spirit and scope of the present disclosure, and it is intended to cover such changes and modifications as fall within the scope of the appended claims and their equivalents.
In particular, various combinations and/or combinations of the features recited in the various embodiments and/or claims of the present disclosure may be made without departing from the spirit or teachings of the present disclosure, even if such combinations or combinations are not expressly recited in the present disclosure. All such combinations and/or associations are within the scope of the present disclosure. Accordingly, the scope of the disclosure is to be determined not only by the appended claims, but also by the equivalents thereof.

Claims (10)

1. A method for fabricating a gallium nitride-based electronic device, comprising:
forming an Al (In, Ga) N/GaN heterostructure on a substrate;
forming a passivation layer on the Al (In, Ga) N/GaN heterostructure;
manufacturing a groove-shaped mark on the passivation layer;
etching the passivation layer by using the groove-shaped mark as an alignment mark to form a gate groove;
forming a gate dielectric in the gate trench and on the passivation layer;
making a metal mark by using the groove-shaped mark as an alignment mark;
forming an ohmic contact layer by using the metal mark as an alignment mark;
isolating the manufactured device; and
a gate metal is formed on the gate dielectric.
2. The method of claim 1, wherein the step of forming the Al (In, Ga) N/GaN heterostructure includes using Al (In, Ga) N as a barrier layer, and including at least one of the group consisting of an A1GaN barrier layer, an AlInN barrier layer, and an AlInGaN barrier layer.
3. The method according to claim 1, wherein in the step of forming the passivation layer, the passivation layer is SiN, A1N or SiO2A single dielectric layer made of any one of the above materials, or SiN, AlN or SiO2At least two of them are superposed to form a composite dielectric layer; the method for forming the passivation layer comprises a chemical vapor deposition method, an atomic layer deposition method or a plasma enhanced chemical vapor deposition method.
4. The manufacturing method according to claim 1, wherein in the step of forming the gate dielectric, the gate dielectric is made of a material including SiN and SiO2At least one of the group consisting of AlON, AlSiO, AlSiN or SiON; thickness of the gate dielectricFrom 5 to 30 nm.
5. The method according to claim 1, wherein in the step of forming the gate dielectric, the growth temperature of the gate dielectric is 500 to 1000 ℃.
6. The method of claim 1 or 5, wherein the gate dielectric is formed by atomic layer deposition, chemical vapor deposition, rapid thermal chemical vapor deposition, molecular beam epitaxy, or metal organic chemical vapor deposition.
7. The method according to claim 1, wherein in the step of forming the ohmic contact layer, the ohmic contact layer comprises an ohmic contact layer containing gold or an ohmic contact layer containing no gold;
when the ohmic contact layer is a gold-containing ohmic contact layer, the temperature for forming the ohmic contact layer is 700-900 ℃; wherein, all the manufacturing steps of the gallium nitride-based electronic device are completed on a gold-containing process line; or, the step of growing the gate dielectric is completed on the complementary metal oxide semiconductor process line before the step of growing the gate dielectric is completed, and the step of growing the gate dielectric is completed on the gold-containing process line after the step of growing the gate dielectric is completed;
when the ohmic contact layer is a gold-free ohmic contact layer, the temperature for forming the ohmic contact layer is 300 ℃ to 700 ℃; all the manufacturing steps of the gallium nitride-based electronic device are completed on a complementary metal oxide semiconductor process line.
8. The method of claim 1, wherein the isolation method used in the isolation step comprises mesa isolation or implant isolation.
9. The method according to claim 1, wherein in the step of forming the gate metal, the gate metal is made of a material selected from the group consisting of Ni/Au, Pt/Ti/Au, Al/Ni/Au, and TiN.
10. A gallium nitride-based electronic device obtained by the fabrication method according to any one of claims 1 to 9.
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