CN110289310A - Transistor, gate structure and preparation method thereof - Google Patents
Transistor, gate structure and preparation method thereof Download PDFInfo
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- CN110289310A CN110289310A CN201910582914.6A CN201910582914A CN110289310A CN 110289310 A CN110289310 A CN 110289310A CN 201910582914 A CN201910582914 A CN 201910582914A CN 110289310 A CN110289310 A CN 110289310A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000002161 passivation Methods 0.000 claims abstract description 101
- 238000000034 method Methods 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 230000008021 deposition Effects 0.000 claims abstract description 16
- 238000000926 separation method Methods 0.000 claims abstract description 15
- 238000002513 implantation Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 1
- 229910002601 GaN Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 241000196324 Embryophyta Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 241000209140 Triticum Species 0.000 description 1
- 235000021307 Triticum Nutrition 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000586 desensitisation Methods 0.000 description 1
- 235000013312 flour Nutrition 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The application provides a kind of transistor, gate structure and preparation method thereof, and gate structure includes a wafer；One first passivation layer；One alignment mark layer, is provided with the window of grid trench etch end point determination；One second passivation layer；One implantation separation layer, is set on the wafer and defines active region；One gate trench layer, a part are set within the active region, and another part is provided with the window of grid trench etch end point determination and is located at except active region；One gate metal layer is set on the gate trench layer.The preparation method of gate structure includes obtaining a wafer, and deposition generates the first passivation layer on it；Alignment mark layer is prepared in the specific position of the first passivation layer one side；Deposition generates the second passivation layer on the first passivation layer；Active region is defined in the second passivation layer；Source electrode and drain electrode is prepared in active region；Gate trench layer and gate metal layer are prepared in active region.Solve the problem of that etch process causes device performance to reduce in the prior art.
Description
Technical field
This application involves a kind of semiconductor structures more particularly to a kind of transistor, gate structure and preparation method thereof.
Background technique
In existing gallium nitride device, main in gate etch process there are two disadvantages: using dry etching grid ditch
Slot unavoidably introduces plasma bombardment, and increasing interfacial state reduces the performance of gallium nitride device；It is inserted into etch stop layer, every
It is bombarded from Dry etch plasma, but etch stop layer reduces passivation effect, reduces device performance.
Summary of the invention
To solve the problems, such as that above-mentioned etch process in the prior art causes device performance to reduce, the application provides a kind of half
Conductor gate structure, in an embodiment, the gate structure includes: a wafer；One first passivation layer, is set to the wafer
On；One alignment mark layer is set to the one side of first passivation layer, while alignment mark layer is provided with grid trench etch end
The window of point detection；One second passivation layer is set on first passivation layer；One implantation separation layer, is set to the crystalline substance
On circle and define active region；One gate trench layer, a part are set within the active region, and another part is provided with grid
The window of trench etch end point determination is simultaneously located at except active region；One gate metal layer is set on the gate trench layer.
In an embodiment, the first passivation layer material is silicon nitride, and the target thickness of generation is
In an embodiment, the percentage that the window area of the grid trench etch end point determination accounts for wafer area is greater than 5%.
In an embodiment, the second passivation layer material is silicon nitride, and the target thickness of generation is
The embodiment of the present application also provides a kind of preparation method of gate structure, which is characterized in that the described method includes:
A wafer is obtained, deposition generates the first passivation layer on it；
Alignment mark layer is prepared in the first passivation layer one side；
Deposition generates the second passivation layer on first passivation layer；
On the wafer, active region is defined by being implanted into separation layer；
Gate trench layer is prepared in the active region；
Gate metal layer is prepared in the active region.
In an embodiment, gate trench layer is prepared in the active region, comprising:
After second passivation layer generates, gate trench position passivation layer thickness is the first passivation layer thickness and the second passivation
The passivation layer of the sum of thickness degree, grid trench etch end point determination position has thickness same as the second passivation layer.
The embodiment of the present application also provides a kind of transistor, including gate structure described in claim 1-4, further includes: an Europe
Nurse contact layer is set within the active region that the implantation separation layer defines, source electrode and drain electrode, source is provided on ohmic contact layer
Pole drains in the side of gate metal layer in the other side of gate metal layer.
The embodiment of the present application also provides a kind of preparation method of transistor, which is characterized in that the described method includes: step
One: obtaining a wafer, deposition generates the first passivation layer on the wafer；Step 2: in first passivation layer side wheat flour
Standby alignment mark layer；Step 3: deposition generates the second passivation layer on first passivation layer；Step 4: the wafer it
On, active region is defined by being implanted into separation layer；Step 5: source electrode and drain electrode is prepared in the active region；Step 6: in the master
Dynamic area prepares gate trench floor；Step 7: gate metal layer is prepared in the active region.
It is raw by plasma enhanced chemical vapor deposition method on the wafer in step 1 in an embodiment
At the first passivation layer；In step 2, alignment area and grid trench etch end point determination region are defined in the alignment mark layer；By
Processing procedure is removed by photoetching, etching and photoresist, defines alignment area and grid trench etch end point determination regional graphics；In step 3:
The second passivation layer is generated by plasma enhanced chemical vapor deposition method on first passivation layer；Grid trench etch is whole at this time
The passivation layer thickness of point detection position covering is the second passivation layer thicknessIt is thin compared with gate trench positionIn step 4: removing processing procedure by photoetching, ion implantation and photoresist, define active region；In step 5:
The ohmic contact layer defines source region and drain region；Processing procedure is removed by photoetching, etching, vapor deposition and photoresist, defines source
Polar region domain and drain region figure；By annealing process so that source electrode and drain electrode forms Ohmic contact in ohmic contact layer；In step
In rapid six: defining gate trench region in the gate trench layer；Processing procedure is removed by photoetching, etching or photoresist, defines grid
Groove figure；And in gate etch process, end point determination mode etching gate trench is enabled to preset thickness, that is, etches away grid
The thickness of trench etch end point determination；In step 7: defining gate metal region in the gate metal layer；By photoetching, wet
Method etch process removes the gate trench layer of remaining preset thickness；Processing procedure is removed by vapor deposition, photoresist, forms grid gold
Belong to layer.
The present invention realizes grid ditch by the way that grid trench etch end point detection windows are arranged in alignment mark layer and gate trench layer
Groove layer etches into the end point determination mode of predetermined thickness, and the damage of dry etching has been isolated.The invention has the following advantages that
One, what the present invention innovated devises double layer passivation layer structure, can select optimal desensitization scheme in the first passivation layer, mention
Rise device performance；
Two, during gate trench layer, it is precisely controlled the thickness of gate trench layer residue passivation layer, it is dry that ICP has been isolated
The bombardment of method etching process plasma；
Three, process flow of the invention is simple, is convenient for large-scale serial production, reduces production cost；
Four, the thickness of gate trench layer residue passivation layer is controllable in the present invention, is applicable to different wafer difference line widths
Product is widely used.
Detailed description of the invention
Fig. 1 is a kind of preparation flow figure of gate structure provided by the present application；
Fig. 2 is a kind of semiconducting gate structure provided by the present application；
Fig. 3 is a kind of flowage structure schematic diagram of grid electrode of semiconductor provided by the present application；
Fig. 4 is a kind of preparation flow figure of transistor arrangement provided by the embodiments of the present application；
Fig. 5 is a kind of transistor arrangement provided by the embodiments of the present application.
Wherein, gate structure 10, wafer 900, the first passivation layer 100, alignment mark layer 200, the second passivation layer 300, plant
Enter separation layer 400, source electrode 500, drain electrode 550, gate trench layer 600, gate metal layer 650, transistor 20.
Specific embodiment
Fig. 1 is a kind of preparation flow figure of gate structure provided by the present application, comprising:
S100: obtaining a wafer 900, and deposition generates the first passivation layer 100 on it；
S200: alignment mark layer 200 is prepared in the specific position of 100 one side of the first passivation layer；
S300: deposition generates the second passivation layer 300 on the first passivation layer 100；
S400: active region is defined by implantation separation layer 400 on the second passivation layer 300；
S600: gate trench layer 600 is prepared in active region；
S650: gate metal layer 650 is prepared in active region.
Fig. 2 is that the application provides a kind of semiconducting gate structure 10, is prepared by above-mentioned steps S100-S650
Gate structure 10 includes: a wafer 900；In the present embodiment, the material of wafer is unlimited, can be gallium nitride or GaAs.
One first passivation layer 100 is set on the wafer 900.
One alignment mark layer 200 is set to the one side of first passivation layer 100, while alignment mark layer 200 is arranged
There is the window of grid trench etch end point determination；When subsequent technique needs grid trench etch end point determination, this window operation can be passed through.
One second passivation layer 300 is set on first passivation layer 100.
One implantation separation layer 400, is set on the wafer 900 and defines active region (in the knot of general transistor
In structure, grid, source electrode and drain electrode are all located in active region, and alignment mark layer is located at except active region).
One gate trench layer 600, a part are set within the active region, and another part is provided with grid trench etch terminal
The window of detection is simultaneously located at except active region.
One gate metal layer 650 is set on the gate trench layer 600.
In an embodiment, the material of first passivation layer 100 is silicon nitride, and the target thickness of generation is
In an embodiment, the percentage that the window area of the grid trench etch end point determination accounts for wafer area is greater than 5%.
Because being unfavorable for grid trench etch end point determination if window is too small, influencing the accuracy of testing result.
In an embodiment, the material of second passivation layer 200 is silicon nitride, and the target thickness of generation is
Fig. 3 is that the application provides a kind of flowage structure schematic diagram of gate structure, which comprises
A wafer 900 is obtained, deposition generates the first passivation layer 100 on it.
Alignment mark layer 200 is prepared in 100 one side of the first passivation layer；In the present embodiment, alignment mark layer 200
The Cutting Road position that the first passivation layer 100 is set, in this way, will not other occupied space, structure setting is more ingenious.
Deposition generates the second passivation layer 300 on first passivation layer 100.
On the wafer 900, active region is defined by implantation separation layer 400.
Gate trench layer 600 is prepared in the active region.
Gate metal layer 650 is prepared in the active region.
In an embodiment, gate trench layer 600 is prepared in the active region, comprising:
After second passivation layer 300 generates, gate trench position passivation layer thickness be the first passivation layer 100 thickness with
The sum of the thickness of second passivation layer 200, the passivation layer of grid trench etch end point determination position have same as the second passivation layer 200
Thickness.
In the present embodiment, the first passivation layer 100 with a thickness ofSecond passivation layer, 200 thicknessThe passivation layer thickness of grid trench etch end point determination position is 200 thickness of the second passivation layerCompared with
Gate trench position is thin
Fig. 5 is a kind of transistor provided by the embodiments of the present application, including gate structure described in claim 1-4, is also wrapped
Include: an ohmic contact layer is set within the active region that the implantation separation layer 400 defines, is arranged on ohmic contact layer active
Pole 500 and drain electrode 550, source electrode 500 is in the side of gate metal layer 650 (grid), and drain electrode 550 is in 650 (grid of gate metal layer
Pole) the other side.
Fig. 4 the embodiment of the present application also provides a kind of preparation method specific flow chart of transistor, which is characterized in that the side
Method includes: S100: obtaining a wafer 900, deposition generates the first passivation layer 100 on the wafer 900；S200: described
One passivation layer, 100 one side prepares alignment mark layer 200；S300: deposition generates the second passivation on first passivation layer 100
Layer 300；S400: on the wafer 900, active region is defined by implantation separation layer 400；S500: in the active region system
Standby source electrode 500 and drain electrode 550；S600: gate trench layer 600 is prepared in the active region；S650: grid are prepared in the active region
Pole metal layer 650.
In an embodiment, in step 1, by plasma enhanced chemical vapor deposition method on the wafer 900
Generate the first passivation layer 100, in the present embodiment, the first passivation layer 100 with a thickness ofIn step 2, described
Alignment mark layer 200 defines alignment area and grid trench etch end point determination region；Processing procedure is removed by photoetching, etching and photoresist,
Define alignment area and grid trench etch end point determination regional graphics；In step 3: on first passivation layer 100 by etc.
Gas ions enhance chemical vapour deposition technique and generate the second passivation layer 300,300 thickness of the second passivation layerGrid at this time
The passivation layer thickness of trench etch end point determination position covering is 300 thickness of the second passivation layerCompared with gate trench position
It sets thinIn step 4: removing processing procedure by photoetching, ion implantation and photoresist, define active region；In step 5
In: source region and drain region are defined in the ohmic contact layer；Processing procedure is removed by photoetching, etching, vapor deposition and photoresist, it is fixed
Adopted source region and drain region figure；By annealing process so that source electrode 500 and drain electrode 550 form ohm in ohmic contact layer
Contact；In step 6: defining gate trench region in the gate trench layer 600；It removes and makes by photoetching, etching or photoresist
Journey defines gate trench figure；And in gate etch process, enables end point determination mode and etch gate trench to default thickness
Degree, that is, etch away the thickness of grid trench etch end point determination；In step 7: defining gate metal in the gate metal layer 650
Region；By photoetching, wet etching processing procedure, the gate trench layer 600 of remaining preset thickness is removed；By vapor deposition, photoresist
Processing procedure is removed, gate metal layer 650 is formed.
During above-mentioned realization, gate trench layer 600 is provided with the window of grid trench etch end point determination, can isolate grid
Pole is during the preparation process because dry etching gate trench introduces the influence of plasma bombardment.
Claims (9)
1. a kind of gate structure, which is characterized in that the gate structure includes:
One wafer；
One first passivation layer, is set on the wafer；
One alignment mark layer is set to the one side of first passivation layer, while alignment mark layer is provided with grid trench etch end
The window of point detection；
One second passivation layer is set on first passivation layer；
One implantation separation layer, is set on the wafer and defines active region；
One gate trench layer, a part are set within the active region, and another part is provided with grid trench etch end point determination
Window is simultaneously located at except active region；
One gate metal layer is set on the gate trench layer.
2. gate structure according to claim 1, which is characterized in that the first passivation layer material is silicon nitride, is generated
Target thickness be
3. gate structure according to claim 1, which is characterized in that the window area of the grid trench etch end point determination accounts for
The percentage of wafer area is greater than 5%.
4. gate structure according to claim 1, which is characterized in that the second passivation layer material is silicon nitride, is generated
Target thickness be
5. a kind of preparation method of gate structure, which is characterized in that the described method includes:
A wafer is obtained, deposition generates the first passivation layer on it；
Alignment mark layer is prepared in the first passivation layer one side；
Deposition generates the second passivation layer on first passivation layer；
On the wafer, active region is defined by being implanted into separation layer；
Gate trench layer is prepared in the active region；
Gate metal layer is prepared in the active region.
6. according to the method described in claim 5, it is characterized in that, preparing gate trench layer in the active region, comprising:
After second passivation layer generates, gate trench position passivation layer thickness is the first passivation layer thickness and the second passivation thickness
The passivation layer of the sum of degree, grid trench etch end point determination position has thickness same as the second passivation layer.
7. a kind of transistor, which is characterized in that including gate structure described in claim 1-4, further includes: an ohmic contact layer,
It is set within the active region that the implantation separation layer defines, source electrode and drain electrode is provided on ohmic contact layer, source electrode is in grid
The side of metal layer drains in the other side of gate metal layer.
8. a kind of preparation method of transistor as claimed in claim 7, which is characterized in that the described method includes:
Step 1: obtaining a wafer, and deposition generates the first passivation layer on the wafer；
Step 2: alignment mark layer is prepared in the first passivation layer one side；
Step 3: deposition generates the second passivation layer on first passivation layer；
Step 4: on the wafer, active region is defined by being implanted into separation layer；
Step 5: source electrode and drain electrode is prepared in the active region；
Step 6: gate trench layer is prepared in the active region；
Step 7: gate metal layer is prepared in the active region.
9. according to the method described in claim 8, it is characterized in that,
In step 1, the first passivation layer is generated by plasma enhanced chemical vapor deposition method on the wafer；
In step 2, alignment area and grid trench etch end point determination region are defined in the alignment mark layer；By photoetching, erosion
It carves and photoresist removes processing procedure, define alignment area and grid trench etch end point determination regional graphics；
In step 3: generating the second passivation by plasma enhanced chemical vapor deposition method on first passivation layer
Layer；The passivation layer thickness of grid trench etch end point determination position covering at this time is the second passivation layer thicknessCompared with grid
Grooved position is thin
In step 4: removing processing procedure by photoetching, ion implantation and photoresist, define active region；In step 5: in the Europe
Nurse contact layer defines source region and drain region；Processing procedure is removed by photoetching, etching, vapor deposition and photoresist, defines source region
With drain region figure；By annealing process so that source electrode and drain electrode forms Ohmic contact in ohmic contact layer；
In step 6: defining gate trench region in the gate trench layer；Processing procedure is removed by photoetching, etching or photoresist,
Define gate trench figure；And in gate etch process, enabling end point determination mode etching gate trench to preset thickness, i.e.,
Etch away the thickness of grid trench etch end point determination；
In step 7: defining gate metal region in the gate metal layer；By photoetching, wet etching processing procedure, removal is surplus
The gate trench layer of remaining preset thickness；Processing procedure is removed by vapor deposition, photoresist, forms gate metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910582914.6A CN110289310A (en) | 2019-06-29 | 2019-06-29 | Transistor, gate structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910582914.6A CN110289310A (en) | 2019-06-29 | 2019-06-29 | Transistor, gate structure and preparation method thereof |
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| Publication Number | Publication Date |
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| CN110289310A true CN110289310A (en) | 2019-09-27 |
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| CN201910582914.6A Pending CN110289310A (en) | 2019-06-29 | 2019-06-29 | Transistor, gate structure and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112259459A (en) * | 2020-10-20 | 2021-01-22 | 中国科学院微电子研究所 | Gallium nitride-based electronic device and manufacturing method thereof |
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| US20070018199A1 (en) * | 2005-07-20 | 2007-01-25 | Cree, Inc. | Nitride-based transistors and fabrication methods with an etch stop layer |
| US20140239346A1 (en) * | 2013-02-26 | 2014-08-28 | Freescale Semiconductor, Inc. | Mishfet and schottky device integration |
| US20170317202A1 (en) * | 2012-06-26 | 2017-11-02 | Nxp Usa, Inc. | Semiconductor device with selectively etched surface passivation |
| CN109755308A (en) * | 2017-11-08 | 2019-05-14 | 世界先进积体电路股份有限公司 | The manufacturing method of semiconductor structure and high electron mobility transistor |
-
2019
- 2019-06-29 CN CN201910582914.6A patent/CN110289310A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0214533A (en) * | 1988-07-01 | 1990-01-18 | Asahi Glass Co Ltd | Manufacture of thin-film active element; liquid-crystal element |
| US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
| US20070018199A1 (en) * | 2005-07-20 | 2007-01-25 | Cree, Inc. | Nitride-based transistors and fabrication methods with an etch stop layer |
| US20170317202A1 (en) * | 2012-06-26 | 2017-11-02 | Nxp Usa, Inc. | Semiconductor device with selectively etched surface passivation |
| US20140239346A1 (en) * | 2013-02-26 | 2014-08-28 | Freescale Semiconductor, Inc. | Mishfet and schottky device integration |
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| CN112259459A (en) * | 2020-10-20 | 2021-01-22 | 中国科学院微电子研究所 | Gallium nitride-based electronic device and manufacturing method thereof |
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Application publication date: 20190927 |