CN111640797A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN111640797A
CN111640797A CN202010489498.8A CN202010489498A CN111640797A CN 111640797 A CN111640797 A CN 111640797A CN 202010489498 A CN202010489498 A CN 202010489498A CN 111640797 A CN111640797 A CN 111640797A
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layer
opening
barrier layer
gate dielectric
etching
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蒋洋
于洪宇
汪青
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Zhuhai Ga Future Technology Co ltd
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Southern University of Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor device, which comprises the following steps: oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer; forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer; alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening; oxidizing the etched barrier layer with the preset depth at the first opening to form a second gate dielectric layer; and forming a grid electrode covering the second grid dielectric layer. The embodiment of the invention realizes the accurate control of the etching depth of the barrier layer, can effectively avoid the phenomenon that the barrier layer is over-etched or under-etched, can effectively reduce the surface roughness of the etched barrier layer, improves the saturation current of a semiconductor device and reduces the electric leakage of a grid electrode.

Description

Method for manufacturing semiconductor device
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
Semiconductor (semiconductor) refers to a material having a conductive property between a conductor (semiconductor) and an insulator (insulator) at normal temperature, and has been widely used in various social fields due to controllability of the conductive property, wherein a GaN High Electron Mobility Transistor (HEMT) device is a hot point of research.
In the preparation process of the GaN HEMT device, the barrier layer of the GaN HEMT device is usually required to be etched to realize an enhancement type device or a depletion type device, but the traditional etching method is often difficult to accurately control the etching depth, the phenomenon of over-etching or incomplete etching is easily caused, the surface obtained by etching is rough, and the saturation current of the device can be reduced. There is also a method for implementing an enhancement device by using fluorine ion implantation, but the fluorine ion implantation technology has strong ion energy and is easy to cause great damage to the device, and meanwhile, fluorine ions have poor thermal stability at high temperature and are easy to influence the reliability of the device, thereby reducing the performance and service life of the device and being not beneficial to wide application.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for manufacturing a semiconductor device, so as to achieve accurate control of an etching depth, reduce roughness of an etched surface, and improve performance of the semiconductor device.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer;
forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer;
alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening;
oxidizing the etched barrier layer with the preset depth at the first opening to form a second gate dielectric layer;
and forming a grid electrode covering the second grid dielectric layer.
Further, before forming the metal electrode on the surface of the barrier layer of the semiconductor epitaxial wafer, the method further comprises the following steps:
sequentially growing a buffer layer, a channel layer, a space isolation layer and a barrier layer on a substrate to form a semiconductor epitaxial wafer;
defining an ohmic contact pattern of a metal electrode on the surface of a barrier layer of the semiconductor epitaxial wafer through photoetching operation;
and forming a metal electrode in the ohmic contact pattern region by metal evaporation and metal stripping.
Further, the metal electrode includes a source electrode and a drain electrode, and the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer is oxidized to form a first gate dielectric layer, including:
defining a gate dielectric region on the surface of the barrier layer of the semiconductor epitaxial wafer through photoetching operation, wherein the gate dielectric region is a region between the source electrode and the drain electrode;
and placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer in the gate dielectric region to form a first gate dielectric layer.
Further, forming a first opening in the passivation layer to expose a portion of the first gate dielectric layer includes:
defining a first opening pattern on the surface of the passivation layer through photoetching operation;
and placing the semiconductor epitaxial wafer in etching equipment, and introducing first etching gas into the etching equipment to etch away the passivation layer in the first opening pattern region to form a first opening exposing the first gate dielectric layer.
Further, alternately performing dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening, including:
placing the semiconductor epitaxial wafer in etching equipment, and introducing second etching gas into the etching equipment to etch away the first gate dielectric layer exposed at the first opening so as to expose the barrier layer at the first opening;
and alternately carrying out dry oxidation and wet etching processes on the barrier layer exposed from the first opening until the position of the barrier layer corresponding to the first opening is etched to a preset depth.
Further, alternately performing dry oxidation and wet etching processes on the barrier layer exposed by the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening, including:
placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer at the first opening to form an oxide layer;
placing the semiconductor epitaxial wafer with the oxide layer formed in a corrosive solution to remove the oxide layer;
and determining the etching depth of the position of the barrier layer corresponding to the first opening after the oxide layer is removed, and repeating the two steps until the etching depth reaches the preset depth.
Further, the oxidizing gas is oxygen gas of 40sccm, and the corrosive solution is a diluted hydrochloric acid solution.
Further, after forming a gate covering the second gate dielectric layer, the method further includes:
defining a source electrode pad opening pattern on the surface of the passivation layer of the source electrode and a drain electrode pad opening pattern on the surface of the passivation layer of the drain electrode through photoetching operation;
placing the semiconductor device in etching equipment, introducing first etching gas into the etching equipment, etching the passivation layer of the source pad opening pattern region to form a second opening exposing part of source metal, and etching the passivation layer of the drain pad opening pattern region to form a third opening exposing part of drain metal;
and forming a source electrode pad at the second opening through metal evaporation and metal stripping, and forming a drain electrode pad at the third opening.
Furthermore, the etching equipment is inductively coupled plasma-reactive ion etching equipment.
Further, the first etching gas is SF6/Ar, the second etching gas is Cl2/Ar。
According to the manufacturing method of the semiconductor device, provided by the embodiment of the invention, the barrier layer is etched through the dry oxidation and wet etching processes, so that the accurate control of the etching depth of the barrier layer is realized, the phenomenon that the barrier layer is over-etched or is not completely etched can be effectively avoided, the surface roughness of the etched barrier layer can be effectively reduced, the saturation current of the semiconductor device is improved, and the electric leakage of the grid electrode is reduced.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;
fig. 3A is a schematic structural diagram of a semiconductor epitaxial wafer according to a second embodiment of the present invention;
fig. 3B is a schematic structural diagram of a semiconductor epitaxial wafer for forming an isolation region according to a second embodiment of the present invention;
fig. 3C is a schematic structural diagram of a semiconductor epitaxial wafer for forming a metal electrode according to a second embodiment of the present invention;
fig. 3D is a schematic structural diagram of a semiconductor epitaxial wafer for forming a passivation layer according to a second embodiment of the present invention;
fig. 3E is a schematic structural diagram of a semiconductor epitaxial wafer for forming a first opening according to a second embodiment of the present invention;
fig. 3F is a schematic structural diagram of a semiconductor epitaxial wafer for forming a second gate dielectric layer according to a second embodiment of the present invention;
fig. 3G is a schematic structural diagram of a gate-forming semiconductor epitaxial wafer according to a second embodiment of the present invention;
fig. 3H is a schematic structural diagram of a semiconductor epitaxial wafer for forming pad openings according to a second embodiment of the present invention;
fig. 3I is a schematic structural diagram of a semiconductor device etched by half-etching according to a second embodiment of the present invention;
fig. 3J is a schematic structural diagram of a semiconductor device etched by using a full-process according to an alternative embodiment of the second embodiment of the present invention;
fig. 4A is a schematic structural diagram of a semiconductor epitaxial wafer for forming a metal electrode according to a third embodiment of the present invention;
fig. 4B is a schematic structural diagram of a semiconductor epitaxial wafer for forming a passivation layer according to a third embodiment of the present invention;
fig. 4C is a schematic structural diagram of a semiconductor epitaxial wafer for forming a gate pad according to a third embodiment of the present invention;
fig. 4D is a schematic structural diagram of a semiconductor device adopting non-recovery etching according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.
Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first opening may be referred to as a second opening, and similarly, a second opening may be referred to as a first opening, without departing from the scope of the present application. Both the first opening and the second opening are openings, but they are not the same opening. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "plurality", "batch" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Example one
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which is applicable to manufacturing a high-power semiconductor device made of materials such as gallium nitride. As shown in fig. 1, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:
and S110, oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer.
Specifically, the semiconductor epitaxial wafer corresponds to a semi-finished semiconductor device, and the structure of the semiconductor epitaxial wafer generally includes, in order on a substrate: buffer layer, electron channel layer and barrier layer. The gate dielectric region is defined on the surface of the barrier layer and is a region needing to be oxidized, and the barrier layer of the gate dielectric region is oxidized to form the first gate dielectric layer. The gate dielectric layer is also called an insulating oxide layer, so that the leakage current of the semiconductor device can be reduced, and the withstand voltage of the semiconductor device can be improved.
And S120, forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer.
Specifically, after the first gate dielectric layer is formed by oxidizing the barrier layer, a passivation layer is formed on the surface of the first gate dielectric layer, and the passivation layer can play a role in protection and prevent external impurity particles from entering the semiconductor device. Optionally, a passivation layer may be formed on the surface of the semiconductor epitaxial wafer after the first gate dielectric layer is formed, so that the coverage of the passivation layer is wider.
After the passivation layer is formed, a first opening for exposing a part of the first gate dielectric layer is formed on the passivation layer in an etching mode, namely, a pattern region of the first opening is defined first, and then the passivation layer of the pattern region of the first opening is etched in the etching mode, so that the first gate dielectric layer covered by the passivation layer at the first opening is exposed. The metal electrode is generally formed at the first opening, so the size of the first opening can be determined according to the size of the metal electrode to be formed.
And S130, alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the exposed barrier layer based on the first opening until the position of the barrier layer corresponding to the first opening is etched to a preset depth.
Specifically, the first gate dielectric layer at the first opening is etched, so that the barrier layer covered by the first gate dielectric layer at the first opening is exposed, and then the barrier layer exposed at the first opening is subjected to dry oxidation and wet etching alternately. The dry oxidation process is to oxidize the barrier layer exposed at the first opening by oxidizing gas so as to form an oxide layer at the first opening; the wet etching process is to remove the oxide layer at the first opening by using an etching solution to expose the barrier layer, so that the barrier layer can be continuously oxidized.
Each time the dry oxidation and wet etching processes are carried out, the depth of the oxide layer on the barrier layer is equivalent to the depth of the oxide layer etched on the barrier layer, therefore, the barrier layer can reach a certain etching depth by alternately carrying out the dry oxidation and wet etching processes on the barrier layer, namely, the etching depth of the barrier layer can be controlled by controlling the times of the dry oxidation and wet etching processes. Generally, the etching depth achieved by carrying out the dry oxidation and wet etching processes once is smaller, such as 5nm, so that the etching depth of the barrier layer can be accurately controlled, and the phenomenon that the barrier layer is over-etched or under-etched can be avoided.
And when the etching depth of the barrier layer reaches the preset depth, stopping the dry oxidation and wet etching processes to complete the etching of the barrier layer.
And S140, oxidizing the barrier layer etched at the first opening by the preset depth to form a second gate dielectric layer.
Specifically, when the barrier layer is etched to a predetermined depth, the barrier layer is still exposed at the first opening, and therefore, the barrier layer at the first opening needs to be oxidized for the first time, so that the second gate dielectric layer is formed at the first opening. The second gate dielectric layer and the first gate dielectric layer formed by oxidation can be used as barrier layers of the barrier layers to prevent oxygen plasmas from directly bombarding the surfaces of the barrier layers, so that the surface roughness of the etched barrier layers can be effectively reduced, the saturation current of the device is improved, and the electric leakage of the grid electrode is reduced.
And S150, forming a grid electrode covering the second grid dielectric layer.
Specifically, the gate electrode covering the second gate dielectric layer is formed by filling a metal material into the second opening, so that the second gate dielectric layer at the second opening is covered by the metal material to form a metal electrode, which is generally referred to as a gate electrode. Optionally, a gate covering the second gate dielectric layer may be formed by metal evaporation and metal stripping, a gate pattern region is defined on the surface of the passivation layer, the gate pattern region includes a first opening, a gate metal is deposited by metal evaporation, and finally, the gate is fabricated by metal stripping.
According to the manufacturing method of the semiconductor device, provided by the embodiment of the invention, the barrier layer is etched through the dry oxidation and wet etching processes, so that the accurate control of the etching depth of the barrier layer is realized, the phenomenon that the barrier layer is over-etched or under-etched can be effectively avoided, the surface roughness of the etched barrier layer can be effectively reduced, the saturation current of the semiconductor device is improved, and the grid electrode leakage is reduced.
Example two
Fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, which further details the above embodiment. As shown in fig. 2, a method for manufacturing a semiconductor device according to a second embodiment of the present invention includes:
s201, growing a buffer layer, a channel layer, a space isolation layer and a barrier layer on the substrate in sequence to form the semiconductor epitaxial wafer.
In the embodiment of the invention, a space isolation layer is added between the channel layer and the barrier layer to form a heterojunction structure of the semiconductor epitaxial wafer, and the heterojunction structure can greatly increase the electron mobility and is mostly used in high-speed components.
For example, taking the fabrication process of the GaN HEMT device as an example, the epitaxial wafer structure of the GaN HEMT device with the heterojunction is shown in fig. 3A. A buffer layer 302, a channel layer 303, a space isolation layer 304, and a barrier layer 305 are once grown on a substrate 301 to form a GaN HEMT heterojunction structure. Wherein, the selection of the substrate can be one or more of GaN (gallium nitride), Si (monocrystalline silicon), SiC (silicon carbide) and sapphire; the buffer layer 302 is made of GaN material, and the thickness of the buffer layer 302 is selected to be 1um-5 um; the channel layer 303 is made of i-GaN material, and the thickness of the channel layer is selected to be 0.3um-1 um; the space isolation layer 304 is made of AlN (aluminum nitride) material, and the thickness of the space isolation layer is selected to be 0.5nm-3 nm; the barrier layer 305 may be one of AlGaN and InAlN, and has a thickness selected from 15nm to 25nm, wherein if the barrier layer 305 is AlGaN, the Al composition is between 15% to 35%, and if the barrier layer 305 is InAlN, the Al composition is between 35% to 55%.
Further, after the semiconductor epitaxial wafer is formed, an isolation region may be formed on the semiconductor epitaxial wafer, and the isolation region functions to prevent leakage between devices when a plurality of semiconductor devices are used simultaneously. The semiconductor epitaxial wafer is firstly cleaned to remove impurity dust on the surface of the semiconductor epitaxial wafer. And then, sequentially carrying out steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the cleaned semiconductor epitaxial wafer, and defining an isolation region of the GaN HEMT device. Finally, the semiconductor epitaxial wafer is placed in a transmission cavity of ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) Etching equipment, Etching gas is introduced into the ICP-RIE Etching equipment, the channel layer 303, the space isolation layer 304 and the barrier layer 305 are etched, and the etched part forms an isolation region. The etching gas here may be BCl3/Cl2Etching gas is used for etchingThe depth is 300-500 nm. And after the etching is finished, cleaning the semiconductor epitaxial wafer to remove residues adsorbed by the etching, for example, carrying out ultrasonic cleaning on the semiconductor epitaxial wafer for 5min by acetone, ultrasonic cleaning on isopropanol for 10min, washing with deionized water for 10min, and finally drying by nitrogen. The structure of the semiconductor epitaxial wafer after the isolation region is formed is shown in fig. 3B.
And S202, defining an ohmic contact pattern of a metal electrode on the surface of the barrier layer of the semiconductor epitaxial wafer through photoetching operation.
Specifically, the photolithography operation includes steps of spin coating, prebaking, photolithography, developing, and postbaking, that is, the steps of spin coating, prebaking, photolithography, developing, and postbaking are sequentially performed on the cleaned semiconductor epitaxial wafer, and an ohmic contact pattern of the metal electrode is defined on the surface of the barrier layer of the semiconductor epitaxial wafer. The size of the ohmic contact pattern of the metal electrode is determined according to the size of the metal electrode to be generated. Generally, the metal electrode herein refers to a source electrode and a drain electrode in the GaN HEMT device, and the ohmic contact pattern of the metal electrode includes a source electrode ohmic contact pattern and a drain electrode ohmic contact pattern.
Further, after defining the source ohmic contact pattern and the drain ohmic contact pattern, a de-oxidation cleaning operation may be performed on the semiconductor epitaxial wafer to remove an oxide layer formed on the surface of the semiconductor device by placing the semiconductor device in air, for example, the semiconductor epitaxial wafer after defining the source ohmic contact pattern and the drain ohmic contact pattern is immersed in a diluted hydrochloric acid solution (wherein the ratio of hydrochloric acid to water is HCl: H)2O is 1: 4) and (3) neutralizing for 3min, removing an oxide layer on the surface of the semiconductor epitaxial wafer, then washing for 15min by using deionized water, and finally drying by using nitrogen.
And S203, forming a metal electrode in the ohmic contact pattern region through metal evaporation and metal stripping, wherein the metal electrode comprises a source electrode and a drain electrode.
Specifically, the ohmic contact pattern of the metal electrode includes a source ohmic contact pattern and a drain ohmic contact pattern, the metal electrode formed in the source ohmic contact pattern region is a source, and the metal electrode formed in the drain ohmic contact pattern region is a drain. Common metal evaporation methods include magnetron sputtering, electron beam evaporation, thermal evaporation and electroplating.
When the operation of the step is carried out, the semiconductor epitaxial wafer processed in the step is immediately placed into a transmission cavity of evaporation equipment, so that the semiconductor epitaxial wafer is prevented from being further oxidized and the ohmic contact effect is prevented from being influenced. In the selection of the material of the metal electrodes of the source and drain, a metal having gold such as Ti/Al/Ti/Au may be selected, or Ti may be selectedxAlyGold-free metals such as TiN. When the metal electrode is Ti/Al/Ti/Au with gold, the corresponding thickness of the metal film layer is 20nm/110nm/40nm/50nm, and when the metal electrode is Ti without goldxAlyIn the case of/TiN, the thickness of the corresponding metal film layer is 60-80nm/60 nm.
And after finishing metal evaporation, immersing the semiconductor epitaxial wafer evaporated with the ohmic metal into a dimethyl sulfoxide solution, and realizing metal stripping in a water bath heating mode at the temperature of 60-80 ℃. And after stripping, washing for 10min by isopropanol, washing for 10min by deionized water, and finally drying by nitrogen.
Further, the semiconductor epitaxial wafer after the metal stripping is at 1000sccm N2Thermal annealing was performed in a (nitrogen) atmosphere, where sccm is a gas mass flow unit expressed in Standard milliliters per Minute (Standard cubiccenter determinator per Minute). The annealing conditions for the gold ohmic metal were: annealing at 830-850 deg.C for 30-45 s, and the annealing condition of non-gold ohmic metal is as follows: annealing at 850-950 deg.C for 60 s. The ohmic contact effect of the annealed metal electrode is better. The structure of the GaN HEMT device after forming the source 313 and the drain 314 is shown in fig. 3C.
And S204, defining a gate dielectric region on the surface of the barrier layer of the semiconductor epitaxial wafer through photoetching operation, wherein the gate dielectric region is a region between the source electrode and the drain electrode.
Specifically, the semiconductor epitaxial wafer processed in the above steps is sequentially subjected to steps of spin coating, pre-baking, photoetching, developing, post-baking and the like, and a gate dielectric region is defined on the surface of the barrier layer of the semiconductor epitaxial wafer, wherein the gate dielectric region is a region between the source electrode and the drain electrode.
S205, placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer of the gate dielectric region to form a first gate dielectric layer.
Specifically, the semiconductor epitaxial wafer processed in the above step is placed in an etching device, and an oxidizing gas is introduced into the etching device to oxidize the barrier layer in the gate dielectric region, so that the first gate dielectric layer is formed as an oxide layer formed after the oxidation of the barrier layer.
Further, the etching apparatus may be an ICP-RIE etching apparatus with an oxidizing gas of 40sccm O2(oxygen). As shown in FIG. 3D, the semiconductor epitaxial wafer processed by the above steps is placed in a transmission cavity of an ICP-RIE etching device at 40sccmO2The gate dielectric region is oxidized in the etching gas to form a first gate dielectric layer 306. The oxidation depth of the barrier layer can be controlled by regulating parameters such as ICP (inductively coupled plasma) and RF (radio frequency) power, oxidation time, gas flow and the like.
And S206, forming a passivation layer covering the first gate dielectric layer, and defining a first opening pattern on the surface of the passivation layer through photoetching operation.
Specifically, the passivation layer may be formed by a common dielectric deposition method, such as: plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and the like. The material of the passivation layer is Si3N4(silicon nitride). Preferably, as shown in fig. 3D, the semiconductor epitaxial wafer processed in the above step is placed in a plasma enhanced chemical vapor deposition device to evaporate a layer of 150nm Si3N4 A passivation layer 307. The passivation layer 307 shown in fig. 3D covers the entire surface of the semiconductor epitaxial wafer, and the protection effect is better. And then, sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the semiconductor epitaxial wafer with the passivation layer formed, and defining a first opening pattern on the surface of the passivation layer.
S207, placing the semiconductor epitaxial wafer in etching equipment, and introducing first etching gas into the etching equipment to etch the passivation layer in the first opening pattern region to form a first opening exposing the first gate dielectric layer.
Specifically, as shown in fig. 3E, the semiconductor epitaxial wafer processed in the above step is placed in a transmission cavity of an ICP-RIE etching apparatus, a first etching gas is introduced into the transmission cavity, and the passivation layer 307 in the first opening pattern region is etched in the first etching gas, so as to form a first opening 308 exposing the first gate dielectric layer 306. Preferably, the first etching gas is SF6/Ar。
S208, placing the semiconductor epitaxial wafer in etching equipment, and introducing second etching gas into the etching equipment to etch away the first gate dielectric layer exposed at the first opening so as to expose the barrier layer at the first opening.
Specifically, the first gate dielectric layer included at the first opening is etched by the second etching gas to violently force the barrier layer at the first opening, so that the barrier layer can be conveniently subjected to dry oxidation and wet etching processes in the follow-up process. Illustratively, the semiconductor epitaxial wafer processed in the above steps is placed in a transmission cavity of an ICP-RIE etching apparatus, a second etching gas is introduced into the transmission cavity, and the first gate dielectric layer 306 exposed at the first opening 308 is etched in the second etching gas, so that the barrier layer 305 is exposed. Preferably, the second etching gas is Cl2/Ar。
S209, alternately carrying out dry oxidation and wet etching processes on the barrier layer exposed from the first opening until the position of the barrier layer corresponding to the first opening is etched to a preset depth.
Specifically, the dry oxidation process is to oxidize the exposed barrier layer at the first opening by oxidizing gas so as to form an oxide layer at the first opening; the wet etching process is to remove the oxide layer at the first opening by using an etching solution to expose the barrier layer, so that the barrier layer can be continuously oxidized.
Further, the step of alternately performing the dry oxidation and the wet etching processes specifically includes S2091 to S2093 (not shown in the figure).
S2091, placing the semiconductor epitaxial wafer into etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer at the first opening to form an oxide layer.
Specifically, the oxidation of the barrier layer at the first opening to form the oxide layer is a dry oxidation process. Illustratively, the semiconductor epitaxial wafer processed by the steps is placed in a transmission cavity of an ICP-RIE etching device, and oxygen is introduced into the transmission cavity at a flow rate of 40sccm O2The oxidation of the barrier layer 305 at the first opening 308 is performed in the etching gas to form an oxide layer on the surface of the barrier layer 305.
Further, different oxidation depths can be achieved by adjusting ICP and RF parameters, which mainly include: ICP power, RF power, chamber pressure, oxidation time, oxygen flow, etc. The ICP power has the function of ionizing oxygen into plasma to determine the concentration of the oxygen plasma; the RF power is used for forming bias voltage and allowing the oxygen plasma to fall to the surface of a device in the etching equipment, and the size of the RF power determines the falling speed and the penetration depth of the oxygen plasma into the sample; the chamber pressure can be used to adjust the etching uniformity, the larger the chamber pressure, the better the etching uniformity, but the larger the chamber pressure, the longer the mean free path of ions, and the smaller the etching rate.
For example, in the selection of the process parameters, the ICP power can be selected from 100W to 450W; the RF power can select 20W-80W; the oxygen flow can be selected to be 20sccm-80 sccm; the chamber pressure can be selected to be 5mTorr-20 mTorr; the oxidation time can be selected from 1min-5 min. Preferably, ICP power is 100W, RF power is 40W, oxygen flow is 40sccm, chamber pressure is 15mTorr, and oxidation time is 3 min.
S2092, placing the semiconductor epitaxial wafer with the oxide layer formed in a corrosive solution to remove the oxide layer.
Specifically, the wet etching process is to remove the oxide layer at the first opening by using a corrosive solution, which is a solution capable of removing the oxide layer, typically an acidic solution, such as a hydrochloric acid solution, to expose the barrier layer. For example, the semiconductor epitaxial wafer after the formation of the oxide layer is immersed in a diluted hydrochloric acid solution (in which hydrochloric acid and water are mixed)The proportion is as follows: HCl: h2O is 1: 4) and (5) neutralizing for 3min, removing the oxide layer at the first opening, then washing for 15min by using deionized water, and finally drying by using nitrogen.
S2093, determining the etching depth of the barrier layer corresponding to the position of the first opening after the oxide layer is removed, and repeating the steps S2091-S2092 until the etching depth reaches the preset depth.
Specifically, one dry oxidation process and one wet etching process can be collectively referred to as an oxidation etching period, and each oxidation etching period is equivalent to etching the barrier layer by the depth of an oxide layer, so that the etching depth of the barrier layer can be controlled by controlling the number of the oxidation etching periods. Generally, the etching depth of one oxidation etching period is smaller, and is usually less than 5nm, so that the etching depth of the barrier layer can be accurately controlled, and the phenomenon that the barrier layer is over-etched or under-etched can be avoided. And when the etching depth of the barrier layer does not reach the preset depth, repeating the dry oxidation and wet etching processes on the semiconductor epitaxial wafer until the etching depth of the barrier layer reaches the preset depth. Illustratively, in this embodiment, half-stress etching is used, i.e., the etching depth of the barrier layer 305 is half the thickness of the barrier layer 305.
S210, oxidizing the barrier layer etched at the first opening by a preset depth to form a second gate dielectric layer.
Specifically, when the barrier layer is etched to a predetermined depth, the barrier layer is still exposed at the first opening, and therefore, the barrier layer at the first opening needs to be oxidized for the first time, so that the second gate dielectric layer is formed at the first opening. The second gate dielectric layer and the first gate dielectric layer formed by oxidation can be used as barrier layers of the barrier layers to prevent oxygen plasmas from directly bombarding the surfaces of the barrier layers, so that the surface roughness of the etched barrier layers can be effectively reduced, the saturation current of the device is improved, and the electric leakage of the grid electrode is reduced.
Illustratively, as shown in FIG. 3F, the semiconductor epitaxial wafer processed by the above steps is placed in a transmission cavity of an ICP-RIE etching device at 40sccm O2The barrier layer 3 at the first opening 308 in the etch gas05 and the barrier layer 305 material AlGaN is oxidized to form a second gate dielectric layer 309.
And S211, forming a grid electrode covering the second grid dielectric layer.
Specifically, the gate electrode covering the second gate dielectric layer is formed by filling a metal material into the second opening, so that the second gate dielectric layer at the second opening is covered by the metal material to form a metal electrode, which is generally referred to as a gate electrode. Optionally, a gate covering the second gate dielectric layer may be formed by metal evaporation and metal stripping, a gate pattern region is defined on the surface of the passivation layer, the gate pattern region includes a first opening, a gate metal is deposited by metal evaporation, and finally, the gate of the semiconductor device is fabricated by metal stripping.
Illustratively, as shown in fig. 3G, the semiconductor epitaxial wafer processed in the above steps is first subjected to spin coating, pre-baking, photolithography, development, post-baking, and the like in sequence, so as to define a gate pattern region on the surface of the passivation layer 307, where the gate pattern region includes the first opening 308. And then, the semiconductor epitaxial wafer is placed into an electron beam evaporation device to deposit the grid metal. And finally, immersing the semiconductor epitaxial wafer with the evaporated grid metal in a dimethyl sulfoxide solution, stripping the metal in a water bath heating mode at the temperature of 60-80 ℃, and after stripping, sequentially washing the semiconductor epitaxial wafer with isopropanol for 10min, washing the semiconductor epitaxial wafer with deionized water for 10min, and drying the semiconductor epitaxial wafer with nitrogen, so that a grid 310 covering the second grid dielectric layer 309 is formed at the first opening 308. The grid metal can be Ti/Au, and the thickness of the corresponding metal film layer is 40nm/100 nm.
S212, defining a source electrode pad opening pattern on the surface of the passivation layer of the source electrode and defining a drain electrode pad opening pattern on the surface of the passivation layer of the drain electrode through photoetching operation.
Specifically, the pad is usually disposed on three metal electrodes of the semiconductor device, so that the corresponding metal electrodes can be more conveniently connected to the semiconductor device during use or testing. In this embodiment, the pad of the gate is already formed in the process of manufacturing the gate, so that the source pad and the drain pad need to be manufactured. And sequentially carrying out glue homogenizing, prebaking, photoetching, developing, postbaking and the like on the semiconductor device processed in the step, and defining a source pad opening graph and a drain pad opening graph, wherein the source pad opening graph is positioned on the surface of the passivation layer at the source electrode, and the drain pad opening graph is positioned on the surface of the passivation layer at the drain electrode.
S213, placing the semiconductor device in etching equipment, introducing a first etching gas into the etching equipment, etching the passivation layer of the source pad opening pattern region to form a second opening exposing part of the source metal, and etching the passivation layer of the drain pad opening pattern region to form a third opening exposing part of the drain metal.
Specifically, the passivation layer in the source pad opening pattern region and the passivation layer in the drain pad opening pattern region are etched away by the first etching gas, so that a second opening exposing a part of the source metal is formed at the source pad opening pattern, and a third opening exposing a part of the drain metal is formed at the drain pad opening pattern. Illustratively, as shown in FIG. 3H, the semiconductor device processed by the above steps is placed in a transmission cavity of an ICP-RIE etching device at SF6Or etching the passivation layer 307 at the source pad opening pattern and the passivation layer 307 at the drain pad opening pattern in an Ar etching gas to form the second opening 311 and the third opening 312, respectively. And after etching is finished, cleaning the semiconductor device for 5min by acetone, cleaning for 10min by isopropanol, cleaning for 10min by deionized water, and finally drying by nitrogen.
And S214, forming a source electrode pad at the second opening through metal evaporation and metal stripping, and forming a drain electrode pad at the third opening.
Specifically, the preparation method of the pad is the same as that of the metal electrode, and the pad is also prepared by metal evaporation and metal stripping, which is not described in detail herein. For example, as shown in fig. 3I, the semiconductor device processed in the above steps is sequentially subjected to spin coating, pre-baking, photolithography, developing, post-baking, and the like, a source pad pattern is defined on the surface of the passivation layer 307 covering the source 313, and a drain pad pattern is defined on the surface of the passivation layer 307 covering the drain 314, where the source pad pattern includes the second opening 311, and the drain pad pattern includes the third opening 312. Then putting the semiconductor device into an electron beam evaporation device for evaporation of pad metal, wherein the pad metal can be Ti/Al/Ti/Au, and the thickness of the corresponding metal film layer is 20nm/110nm/40nm/50 nm. And finally, immersing the semiconductor device with plated pad metal in a dimethyl sulfoxide solution, stripping the metal in a water bath heating mode at the temperature of 60-80 ℃, washing the metal for 10min by isopropanol and 10min by deionized water in sequence after stripping is finished, and finally drying the metal by blowing with nitrogen to form a source pad315 and a drain pad 316.
In this embodiment, half-process etching is adopted, that is, the etching depth of the barrier layer 305 is half the thickness of the barrier layer 305, in an alternative embodiment, as shown in fig. 3J, full-process etching may also be adopted, that is, the barrier layer 305 is completely etched, and finally, the second gate dielectric layer 309 is formed on the space isolation layer 304, because the material of the space isolation layer 304 is AlN, which is more difficult to oxidize than the barrier layer 305(AlGaN), the space isolation layer 304 may serve as an oxidation self-stop layer under the condition of full-process, so as to prevent the over-etching. The etching depth of the barrier layer 305 and the formation position of the second gate dielectric layer 309 are different in the full-etch and half-etch, and the other preparation steps and methods are the same, and are not described herein again.
According to the manufacturing method of the semiconductor device, provided by the embodiment of the invention, the barrier layer is etched through the dry oxidation and wet etching processes, so that the accurate control of the etching depth of the barrier layer is realized, the phenomenon that the barrier layer is over-etched or is not completely etched can be effectively avoided, the surface roughness of the etched barrier layer can be effectively reduced, the saturation current of the semiconductor device is improved, and the grid electrode leakage is reduced. By manufacturing the metal electrode pad, the semiconductor device is more convenient to connect in use or test.
EXAMPLE III
The third embodiment of the invention provides a manufacturing method of an etching-free semiconductor device, namely a manufacturing method of a non-recovery GaNHEMT depletion mode device.
Referring to fig. 4A, the structure of the semiconductor epitaxial wafer is the same as that in the above-described embodiment, including: substrate 301, buffer layer 302, channel layer 303, space isolation layer 304, and barrier layer 305. First, a source 313 and a drain 314 are formed on the semiconductor epitaxial wafer, and the barrier layer 305 in the gate dielectric region on the surface of the semiconductor epitaxial wafer is oxidized to form the first gate dielectric layer 306, wherein the forming manner of the source 313, the drain 314 and the first gate dielectric layer 306 is the same as that in the above embodiment, and reference may be specifically made to steps S201 to S205, which are not described herein again.
Then, a gate 310 is formed on the first gate dielectric layer 306, specifically: sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the semiconductor epitaxial wafer processed in the step, and defining a grid electrode graph of a device; placing the semiconductor epitaxial wafer into an electron beam evaporation device to deposit device grid metal Ti/Au (the thickness of a corresponding metal film layer is 40nm/100 nm); immersing the semiconductor epitaxial wafer with the evaporated grid metal into a dimethyl sulfoxide solution, and realizing metal stripping in a water bath heating mode at the temperature of 60-80 ℃; and after stripping, washing for 10min by isopropanol, washing for 10min by deionized water and drying by nitrogen in sequence.
Next, depositing a passivation layer 307 on the surface of the semiconductor epitaxial wafer, referring to fig. 4B, specifically: placing the semiconductor epitaxial wafer processed in the step into plasma enhanced chemical vapor deposition equipment for evaporating and coating a layer of 150nm Si3N4 A passivation layer 307.
Next, a gate opening is formed on the surface of the passivation layer of the gate, and a gate pad is prepared at the gate opening, referring to fig. 4C. Forming a gate opening on a surface of a passivation layer of a gate specifically includes: sequentially carrying out the steps of spin coating, pre-baking, photoetching, developing, post-baking and the like on the semiconductor epitaxial wafer processed in the step, and defining a grid pad opening pattern; placing the semiconductor epitaxial wafer in a transmission cavity of ICP-RIE etching equipment at SF6Etching the passivation layer on the surface in the/Ar etching gas to form a gate opening; and cleaning the etched semiconductor epitaxial wafer with acetone for 5min, cleaning with isopropanol for 10min, washing with deionized water for 10min, and finally drying with nitrogen.
The preparation of the gate pad at the gate opening specifically comprises: sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the semiconductor epitaxial wafer processed in the step, and defining a grid pad graph; placing the semiconductor epitaxial wafer into an electron beam evaporation device to deposit the grid metal Ti/Au (the thickness of the corresponding metal film layer is 40nm/100nm) of the E-mode device; immersing the semiconductor epitaxial wafer with the evaporated E-mode device grid metal in a dimethyl sulfoxide solution, and realizing metal stripping in a water bath heating mode at the temperature of 60-80 ℃; and after stripping, washing for 10min by isopropanol, washing for 10min by deionized water, and finally drying by nitrogen to form the grid pad 401.
Finally, forming a source pad and a drain pad, referring to fig. 4D, specifically including: sequentially carrying out steps of spin coating, pre-baking, photoetching, developing, post-baking and the like on the semiconductor epitaxial wafer processed in the step, and defining a source electrode pad opening pattern and a drain electrode pad opening pattern; placing the semiconductor epitaxial wafer in a transmission cavity of ICP-RIE etching equipment at SF6Etching the passivation layer 307 at the source pad opening pattern and the passivation layer 307 at the drain pad opening pattern in an/Ar etching gas to form a source pad opening and a drain pad opening respectively; cleaning the etched and opened semiconductor epitaxial wafer with acetone for 5min, cleaning with isopropanol for 10min, washing with deionized water for 10min, and drying with nitrogen; sequentially carrying out the steps of spin coating, prebaking, photoetching, developing, postbaking and the like on the semiconductor epitaxial wafer processed in the step, and defining a source electrode pad graph and a drain electrode pad graph; placing the semiconductor epitaxial wafer into an electron beam evaporation device to deposit pad metal Ti/Al/Ti/Au (the thickness of a corresponding metal film layer is 20nm/110nm/40nm/50 nm); immersing the semiconductor epitaxial wafer with plated pad metal in a dimethyl sulfoxide solution, and realizing metal stripping in a water bath heating mode at the temperature of 60-80 ℃; and after stripping, sequentially washing for 10min by isopropanol, washing for 10min by deionized water, and finally drying by nitrogen to form a source pad315 and a drain pad 316.
The third manufacturing method of the semiconductor device provided by the embodiment of the invention realizes the manufacturing of the GaN HEMT depletion device, and the first gate dielectric layer is formed by oxidizing the lower part of the grid electrode of the semiconductor device, so that the electric leakage of the device is greatly reduced, the performance of the device is improved, the manufacturing method is simple, and the manufacturing cost is effectively reduced.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:
oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer;
forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer;
alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening;
oxidizing the etched barrier layer with the preset depth at the first opening to form a second gate dielectric layer;
and forming a grid electrode covering the second grid dielectric layer.
2. The method of claim 1, wherein before forming the metal electrode on the surface of the barrier layer of the semiconductor epitaxial wafer, further comprising:
sequentially growing a buffer layer, a channel layer, a space isolation layer and a barrier layer on a substrate to form a semiconductor epitaxial wafer;
defining an ohmic contact pattern of a metal electrode on the surface of a barrier layer of the semiconductor epitaxial wafer through photoetching operation;
and forming a metal electrode in the ohmic contact pattern region by metal evaporation and metal stripping.
3. The method of claim 2, wherein the metal electrode comprises a source electrode and a drain electrode, and wherein oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form the first gate dielectric layer comprises:
defining a gate dielectric region on the surface of the barrier layer of the semiconductor epitaxial wafer through photoetching operation, wherein the gate dielectric region is a region between the source electrode and the drain electrode;
and placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer in the gate dielectric region to form a first gate dielectric layer.
4. The method of claim 3, wherein forming a first opening in the passivation layer that exposes a portion of the first gate dielectric layer comprises:
defining a first opening pattern on the surface of the passivation layer through photoetching operation;
and placing the semiconductor epitaxial wafer in etching equipment, and introducing first etching gas into the etching equipment to etch away the passivation layer in the first opening pattern region to form a first opening exposing the first gate dielectric layer.
5. The method of claim 4, wherein alternately performing dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a predetermined depth at a position corresponding to the first opening, comprises:
placing the semiconductor epitaxial wafer in etching equipment, and introducing second etching gas into the etching equipment to etch away the first gate dielectric layer exposed at the first opening so as to expose the barrier layer at the first opening;
and alternately carrying out dry oxidation and wet etching processes on the barrier layer exposed from the first opening until the position of the barrier layer corresponding to the first opening is etched to a preset depth.
6. The method of claim 5, wherein alternately performing a dry oxidation and a wet etching process on the barrier layer exposed by the first opening until the barrier layer is etched to a predetermined depth at a position corresponding to the first opening, comprises:
placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer at the first opening to form an oxide layer;
placing the semiconductor epitaxial wafer with the oxide layer formed in a corrosive solution to remove the oxide layer;
and determining the etching depth of the position of the barrier layer corresponding to the first opening after the oxide layer is removed, and repeating the two steps until the etching depth reaches the preset depth.
7. The method of claim 6, wherein the oxidizing gas is oxygen at 40 seem and the corrosive solution is a diluted hydrochloric acid solution.
8. The method of claim 7, further comprising, after forming a gate overlying the second gate dielectric layer:
defining a source electrode pad opening pattern on the surface of the passivation layer of the source electrode and a drain electrode pad opening pattern on the surface of the passivation layer of the drain electrode through photoetching operation;
placing the semiconductor device in etching equipment, introducing first etching gas into the etching equipment, etching the passivation layer of the source pad opening pattern region to form a second opening exposing part of source metal, and etching the passivation layer of the drain pad opening pattern region to form a third opening exposing part of drain metal;
and forming a source electrode pad at the second opening through metal evaporation and metal stripping, and forming a drain electrode pad at the third opening.
9. The method of any of claims 3-8, wherein the etching apparatus is an inductively coupled plasma-reactive ion etching apparatus.
10.The method of claim 5, wherein the first etch gas is SF6/Ar, the second etching gas is Cl2/Ar。
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