CN112466941A - Preparation method of E/D-mode GaN HEMT integrated device - Google Patents
Preparation method of E/D-mode GaN HEMT integrated device Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
- H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
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Abstract
The embodiment of the invention discloses a preparation method of an E/D-mode GaN HEMT integrated device. The preparation method comprises the steps of firstly forming at least two GaN HEMT heterojunction structures on a substrate, wherein each heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked, and a source electrode ohmic contact electrode and a drain electrode ohmic contact electrode are formed on one side, far away from the substrate, of each heterojunction structure. And then, forming a first grid opening on one side of the heterojunction structure far away from the substrate in a dry oxidation-wet etching repeated circulation mode, forming a first grid at the first grid opening, forming a second grid opening and a second grid, and forming a source electrode and a drain electrode, so that compatibility of the D-mode GaN HEMT device and the E-mode GaN HEMT device in material and process is realized, and integration of enhancement type devices and depletion type devices is realized.
Description
Technical Field
The embodiment of the invention relates to the technical field of GaN HEMT devices, in particular to a preparation method of an E/D-mode GaN HEMT integrated device.
Background
Gallium nitride (GaN) materials have wide forbidden bandwidth, high breakdown electric field, high thermal conductivity, high electron saturation rate and higher radiation resistance, and have wide application prospects in high-temperature, high-frequency, radiation-resistant and high-power semiconductor devices.
At present, all High Electron Mobility Transistor (HEMT) devices of AlGaN/GaN structures are depletion type HEMT devices (D-mode GaN HEMTs) of GaN structures, how to realize enhancement type HEMT devices (E-mode GaN HEMTs) of GaN structures, how to realize compatibility of enhancement type HEMT devices of GaN structures and depletion type HEMT devices of GaN structures in materials and processes, and therefore integration of enhancement type devices and depletion type devices is a problem which needs to be solved urgently at present.
Disclosure of Invention
The embodiment of the invention provides a preparation method of an E/D-mode GaN HEMT integrated device, which is used for realizing the compatibility of an enhancement type device and a depletion type device of an AIGaN/AlN/GaN structure in terms of materials and processes, thereby realizing the integration of the enhancement type device and the depletion type device of the AIGaN/AlN/GaN structure.
The embodiment of the invention provides a preparation method of an E/D-mode GaN HEMT integrated device, which comprises the following steps:
forming at least two GaN HEMT heterojunction structures on a substrate; the heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked;
forming a source electrode ohmic contact electrode and a drain electrode ohmic contact electrode on one side of the heterojunction structure far away from the substrate;
forming a first grid opening on one side of the heterojunction structure far away from the substrate in a dry oxidation-wet etching repeated circulation mode;
forming a first gate at the first gate opening;
forming a second gate opening and a second gate;
and forming a source electrode and a drain electrode.
Optionally, the forming the first gate opening on the side of the heterojunction structure away from the substrate by using a dry oxidation-wet etching repeated cycle method includes:
dry oxidation in oxygen plasma;
and carrying out wet etching in hydrochloric acid solution.
Optionally, after forming the source ohmic contact electrode and the drain ohmic contact electrode on the side of the heterojunction structure away from the substrate, the method further comprises:
and forming a first passivation layer on one side of the heterojunction structure far away from the substrate.
Optionally, the forming the first gate opening on the side of the heterojunction structure away from the substrate by using a dry oxidation-wet etching repeated cycle method includes:
and etching the first passivation layer on one side of the heterojunction structure far away from the substrate, and etching the barrier layer and the space isolation layer in a dry oxidation-wet etching repeated circulation mode to form a first gate opening.
Optionally, forming the second gate opening comprises:
the first passivation layer is etched to form a second gate opening.
Optionally, the forming the first gate opening on the side of the heterojunction structure away from the substrate by using a dry oxidation-wet etching repeated cycle method includes:
etching the barrier layer and the space isolation layer on one side of the heterojunction structure far away from the substrate in a dry oxidation-wet etching repeated circulation mode to form a first opening;
forming a first dielectric layer, wherein the first dielectric layer is positioned between the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode;
forming a second passivation layer;
the second passivation layer at the first opening is etched to form a first gate opening.
Optionally, forming the second gate opening comprises:
the second passivation layer is etched to form a second gate opening.
Optionally, the forming the first gate opening on the side of the heterojunction structure away from the substrate by using a dry oxidation-wet etching repeated cycle method includes:
etching the first passivation layer on one side of the heterojunction structure far away from the substrate, and etching the barrier layer by adopting a dry oxidation-wet etching repeated circulation mode to form a second opening;
and oxidizing the space isolation layer at the second opening into a second dielectric layer to form a first gate opening.
Optionally, forming the second gate opening comprises:
etching the first passivation layer to form a third opening;
and oxidizing part of the barrier layer at the third opening into a third dielectric layer to form a second grid opening.
Optionally, the material of the second dielectric layer and the material of the third dielectric layer both comprise aluminum oxide.
The preparation method of the E/D-mode GaN HEMT integrated device comprises the steps of firstly forming at least two GaN HEMT heterojunction structures on a substrate, wherein each heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked, and a source electrode ohmic contact electrode and a drain electrode ohmic contact electrode are formed on one side, far away from the substrate, of each heterojunction structure. And then, forming a first grid opening on one side of the heterojunction structure far away from the substrate in a dry oxidation-wet etching repeated circulation mode, forming a first grid at the first grid opening, forming a second grid opening and a second grid, and forming a source electrode and a drain electrode, so that compatibility of the D-mode GaN HEMT device and the E-mode GaN HEMT device in material and process is realized, and integration of enhancement type devices and depletion type devices is realized.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a GaN HEMT heterojunction structure according to an embodiment of the invention;
FIG. 3 is a schematic view of isolating one of the GaN HEMT heterojunction structures of FIG. 2 into two GaN HEMT heterojunction structures;
fig. 4 is a schematic structural diagram of forming a source ohmic contact electrode and a drain ohmic contact electrode on a heterojunction structure according to a first embodiment of the present invention;
FIG. 5 is a schematic view of a heterojunction structure with a first gate opening formed therein according to an embodiment of the invention;
fig. 6 is a schematic diagram of a heterojunction structure with a first gate formed thereon according to an embodiment of the invention;
FIG. 7 is a schematic view of a heterojunction structure with a second gate opening formed therein according to an embodiment of the invention;
fig. 8 is a schematic view of a heterojunction structure with a second gate formed thereon according to an embodiment of the invention;
fig. 9 is a schematic diagram of a heterojunction structure with source and drain electrodes formed thereon according to an embodiment of the invention;
fig. 10 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a second embodiment of the present invention;
fig. 11 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a third embodiment of the present invention;
fig. 12 is a schematic structural diagram of forming a first opening on a heterojunction structure according to a third embodiment of the present invention;
fig. 13 is a schematic structural diagram of forming a first dielectric layer on a heterojunction structure according to the third embodiment of the present invention;
fig. 14 is a schematic structural diagram of forming a second passivation layer on the heterojunction structure according to the third embodiment of the present invention;
fig. 15 is a schematic structural diagram of a first gate opening formed after etching a second passivation layer at the first opening according to a third embodiment of the present invention;
fig. 16 is a schematic diagram of a heterojunction structure with a first gate formed thereon according to a third embodiment of the present invention;
FIG. 17 is a schematic structural view of a second gate opening formed by etching a second passivation layer as provided in the third embodiment of the present invention;
FIG. 18 is a schematic illustration of a heterojunction structure for forming a second gate as provided in the third embodiment of the present invention;
fig. 19 is a schematic view of a heterojunction structure with source and drain electrodes formed according to a third embodiment of the invention;
fig. 20 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a fourth embodiment of the present invention;
FIG. 21 is a schematic structural diagram of a fourth embodiment of the present invention in which a second opening is formed in the heterojunction structure;
FIG. 22 is a schematic structural diagram of a fourth embodiment of the present invention in which a second dielectric layer is formed on the heterojunction structure;
fig. 23 is a schematic view of a heterojunction structure with a first gate formed thereon according to a fourth embodiment of the present invention;
fig. 24 is a schematic structural view of a third dielectric layer formed on the heterojunction structure according to the fourth embodiment of the present invention;
fig. 25 is a schematic structural diagram of forming a second gate on the heterojunction structure according to the fourth embodiment of the present invention;
fig. 26 is a schematic view of a heterojunction structure with source and drain electrodes according to the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background, how to realize an enhancement mode device (E-mode GaN HEMT) of AlGaN/GaN structure, and how to realize integration of the enhancement mode device and the depletion mode device of AlGaN/GaN structure are problems that need to be solved at present. The existing method for preparing an enhancement device with an AlGaN/GaN structure comprises concave gate etching or fluorine ion implantation and the like. The concave gate etching method has poor process repeatability and poor controllability, so that the etching depth is difficult to accurately master, the phenomenon of over-etching or incomplete etching can occur, and large etching damage can be introduced in the etching process, so that the etched surface is rough, the saturation current of a device is reduced, and the grid leakage of the device is increased; the uniformity of the fluorine ion implantation method is poor, and the thermal stability of fluorine ions at high temperature is not high, so that the reliability of the device is easily influenced, and the performance and the service life of the device are influenced. In view of this, the embodiment of the invention provides a method for manufacturing an E/D-mode GaN HEMT integrated device.
Example one
Fig. 1 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to an embodiment of the present invention, as shown in fig. 1, the method includes:
s10, forming at least two GaN HEMT heterojunction structures on the substrate; the heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked.
In this embodiment, the material of the substrate may include at least one of gallium nitride (GaN), silicon (Si), silicon carbide (SiC), and sapphire, and the substrate can support the GaN HEMT heterojunction structure. The GaN HEMT heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked and grown.
The GaN layer is in direct contact with the substrate, and the thickness of the GaN layer can be 1um to 5 um.
The spatial separation layer is capable of confining a two-dimensional electron gas (2-DEG) generated between the GaN layer and the barrier layer to an interface of the barrier layer and the GaN layer (and the channel layer). The material of the space isolation layer may be AlN, and the thickness of the space isolation layer may be 0.5nm to 3 nm.
The barrier layer can be made of AlGaN or InAlN, and the thickness of the barrier layer can be 15nm to 25nm, wherein the composition of Al in the AlGaN material can be 0.15 percent to 0.35 percent, and the composition of Al in the InAlN material can be 0.35 percent to 0.55 percent.
Optionally, the GaN HEMT heterojunction structure comprises a GaN layer, an i-GaN layer, a space isolation layer and a barrier layer which are sequentially stacked and grown. Wherein, the i-GaN layer is the channel layer, and the thickness of the i-GaN layer can be 0.3um to 1 um.
Forming at least two GaN HEMT heterojunction structures on a substrate, wherein the at least two GaN HEMT heterojunction structures can be formed on the substrate individually without mutual interference, or can be formed on the substrate individually, and the formed GaN HEMT heterojunction structure is isolated into at least two GaN HEMT heterojunction structures by using a gas etching method; part of the GaN HEMT heterojunction structure is used for preparing an enhancement device, and part of the GaN HEMT heterojunction structure is used for preparing a depletion device.
For example, a GaN HEMT heterojunction structure is formed, wherein the thickness of the GaN layer is 1um to 5um, the thickness of the i-GaN layer is 0.3um to 1um, the spatial isolation layer is an AlN layer, the thickness of the spatial isolation layer is 0.5nm to 3nm, the barrier layer is an AlGaN layer or an InAlN layer, and the thickness of the barrier layer is 15nm to 25 nm. On the formed GaN HEMT heterojunction structure, boron trichloride (BCl) is adopted3) Or chlorine (Cl)2) And etching at least one isolation region with the depth of 300nm to 500nm, wherein the at least one isolation region isolates the original GaN HEMT heterojunction structure into at least two GaN HEMT heterojunction structures. In addition, the GaN HEMT heterojunction structure with the etched isolation region can be cleaned. For example, the cleaning is completed by ultrasonic cleaning with acetone for 5 minutes, ultrasonic cleaning with isopropanol for 10 minutes, rinsing with deionized water for 10 minutes, and finally blowing with nitrogen.
Exemplarily, fig. 2 is a schematic diagram of a GaN HEMT heterojunction structure according to an embodiment of the present invention, as shown in fig. 2, a GaN HEMT heterojunction structure 20 is disposed on a substrate 10, and the GaN HEMT heterojunction structure 20 includes a GaN layer 21, a space isolation layer 22, and a barrier layer 23, which are sequentially stacked and grown. Fig. 3 is a schematic diagram of isolating one of the GaN HEMT heterojunction structures of fig. 2 into two GaN HEMT heterojunction structures, by etching an isolation region 200 as in fig. 3 on one of the GaN HEMT heterojunction structures of fig. 2, the one of the GaN HEMT heterojunction structures of fig. 2 being isolated by the isolation region 200 of fig. 3 into the GaN HEMT heterojunction structure 201 and the GaN HEMT heterojunction structure 202 of fig. 3. The present embodiment illustratively selects the GaN HEMT heterojunction structure 201 for fabricating an enhancement mode device and the GaN HEMT heterojunction structure 202 for fabricating a depletion mode device.
And S11, forming a source ohmic contact electrode and a drain ohmic contact electrode on the side of the heterojunction structure far away from the substrate.
Specifically, each heterojunction structure includes one source ohmic contact electrode and one drain ohmic contact electrode thereon. The material of the ohmic contact electrode can be gold material or non-gold material. The alloy material is Ti/Al/Ti/Au for example, and the non-alloy material is TixAly/TiN for example, wherein the thickness of Ti/Al/Ti/Au can be 20nm/110nm/40nm/50nm, and the thickness of TixAly/TiN can be 60nm/60nm to 80nm/60 nm.
In this embodiment, the source ohmic contact electrode and the drain ohmic contact electrode may be formed by sequentially performing the following steps: and (3) sequentially carrying out glue homogenizing, prebaking, photoetching, developing and postbaking on the heterojunction structure to define a source electrode ohmic contact electrode pattern and a drain electrode ohmic contact electrode pattern. And (3) immersing the heterojunction structure defining the active electrode ohmic contact electrode pattern and the drain electrode ohmic contact electrode pattern in a dilute hydrochloric acid solution to remove the oxide on the surface of the heterojunction structure, wherein the immersion time is 3 minutes, the ratio of the hydrochloric acid solution to water is 1:4, and after the heterojunction structure with the oxide on the surface removed is washed by deionized water for 15 minutes, drying by blowing nitrogen. The sample dried by nitrogen is placed in a transmission cavity of evaporation equipment, so that the heterojunction structure dried by nitrogen is prevented from being oxidized again to influence the preparation effect of the ohmic contact electrode, and evaporation is carried out to form an ohmic contact electrode layer. Immersing the heterojunction structure coated with the ohmic contact electrode layer in a dimethyl sulfoxide solution, and sequentially heating in a water bath at 60-80 ℃ to realize metal stripping, isopropanol washing for 10 minutes, deionized water washing for 10 minutes and nitrogen drying to form a source ohmic contact electrode and a drain ohmic contact electrode. Forming a heterojunction structure with source and drain ohmic contact electrodes in nitrogen (N)21000sccm) atmosphere to obtain a source electrode ohmic contact electrode and a drain electrode ohmic contact electrode with better effect, wherein the ohmic contact electrode with gold material can be annealed at 830-850 ℃ for 30-40 seconds, and the ohmic contact electrode without gold material can be annealed at 850-950 ℃ for 60 seconds.
Exemplarily, fig. 4 is a schematic structural view of a source ohmic contact electrode and a drain ohmic contact electrode formed on a heterojunction structure according to an embodiment of the present invention, and as shown in fig. 4, one source ohmic contact electrode 30 and one drain ohmic contact electrode 40 are formed on each heterojunction structure.
And S12, forming a first gate opening on the side of the heterojunction structure far away from the substrate by adopting a dry oxidation-wet etching repeated circulation mode.
Specifically, a first gate opening is formed on the heterojunction structure for fabricating the enhancement mode device, and the first gate opening may be located between the source and drain ohmic contact electrodes to form the first gate between the source and drain ohmic contact electrodes.
In this embodiment, the first gate opening is formed sequentially by the following steps: and sequentially carrying out glue homogenizing, pre-baking, photoetching, developing and post-baking on the heterojunction structure which is formed with the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode and used for preparing the enhancement device to define a first grid opening graph. And forming a first gate opening at the first gate opening pattern by adopting a dry oxidation-wet etching repeated circulation mode on the heterojunction structure defined with the first gate opening pattern.
The manner of the dry oxidation-wet etching repeated cycle provided in this embodiment can be understood as follows: and sequentially carrying out dry oxidation, wet etching, dry oxidation, wet etching and dry oxidation … …. Dry oxidation is understood to mean that the material at the target etching site is oxidized into oxide by means of oxygen plasma oxidation, for example, the oxide is oxidized into oxide by means of oxygen plasma oxidation, and wet etching is understood to mean that the oxide at the target etching site after dry oxidation is dissolved and removed by a solution, for example, an acidic solution, preferably, a strong acidic solution, so as to achieve etching of the target etching site. In this embodiment, the etching depth of one etching period may reach 5nm, and the etching depth of the first gate opening determines the number of etching periods used.
Accordingly, in the embodiment, a dry oxidation-wet etching repeated cycle manner is adopted, since the oxidation uniformity of dry oxidation and the controllability of the oxidation depth range of dry oxidation are good, the unoxidized part can be used as a stop layer of wet etching, so that the controllability of the etching depth and the etching range is higher, the etching depth of the first gate opening can be accurately controlled by controlling the etching depth of each etching period and the number of used etching periods, and the requirement on etching equipment is low. Compared with a fluorine ion implantation method, the uniformity is better; compared with a concave grid etching method, the etching damage is reduced by effectively controlling the etching depth, the process repeatability is good, and the roughness of the surface of the structure after the first grid is opened is reduced, so that the saturation current of the device is improved, and the grid leakage of the device is reduced.
Fig. 5 is a schematic diagram of a heterojunction structure with a first gate opening formed therein according to an embodiment of the present invention, and as shown in fig. 5, the first gate opening 50 is formed on the heterojunction structure 201 for manufacturing an enhancement device by using a dry oxidation-wet etching repeated cycle, and in addition, in fig. 5, the barrier layer 23 and the space isolation layer 22 at the first gate opening pattern are etched by using a dry oxidation-wet etching repeated cycle, and then the first gate opening 50 is formed.
S13, forming a first gate at the first gate opening.
Specifically, the first gate electrode is used as a gate electrode of an enhancement mode device, the material of the first gate electrode can be Ti/Au, and the thickness of the Ti/Au can be 40nm/100 nm.
In this embodiment, the formation of the first gate at the first gate opening may be sequentially formed by: and sequentially carrying out glue homogenizing, prebaking, photoetching, developing and postbaking on the heterojunction structure so as to define a first grid electrode figure at the first grid electrode opening. And placing the heterojunction structure defined with the first grid electrode pattern into an electron beam evaporation device to deposit a first grid electrode layer. And immersing the heterojunction structure deposited with the first gate layer into a dimethyl sulfoxide solution, and sequentially carrying out metal stripping, isopropanol rinsing for 10 minutes, deionized water rinsing for 10 minutes and nitrogen blow-drying in a water bath heating mode at 60-80 ℃ to form the first gate.
Exemplarily, fig. 6 is a schematic diagram of a heterojunction structure with a first gate formed according to an embodiment of the present invention, and in conjunction with fig. 5 and 6, a first gate 51 is formed at a first gate opening 50.
And S14, forming a second gate opening and a second gate.
Specifically, a second gate opening may be formed on the heterojunction structure for fabricating the depletion mode device, and the second gate opening may be located between the source and drain ohmic contact electrodes to form the second gate between the source and drain ohmic contact electrodes. The second gate serves as a gate of the depletion mode device, the material of the second gate may be Ti/Au, and the thickness of the Ti/Au may be 40nm/100 nm.
In this embodiment, the forming of the second gate opening and the second gate may be sequentially formed by: and sequentially carrying out glue homogenizing, prebaking, photoetching, developing and postbaking on the heterojunction structure to define a second grid opening pattern. And forming a second gate opening at the second gate opening pattern, wherein the second gate opening can be formed by a gas etching method. And (3) sequentially carrying out glue homogenizing, pre-baking, photoetching, developing and post-baking on the heterojunction structure with the second grid opening to define a second grid pattern. And putting the heterojunction structure defined with the second grid electrode pattern into an electron beam evaporation device to deposit a second grid electrode layer. And immersing the heterojunction structure evaporated with the second gate layer into a dimethyl sulfoxide solution to realize metal stripping, isopropanol rinsing for 10 minutes, deionized water rinsing for 10 minutes and nitrogen blow-drying in a water bath heating mode at 60-80 ℃ so as to form the second gate.
Exemplarily, fig. 7 is a schematic diagram of a heterojunction structure with a second gate opening formed therein according to an embodiment of the present invention, and as shown in fig. 7, a second gate opening 61 is formed on the heterojunction structure 202. Fig. 8 is a schematic view of a heterojunction structure with a second gate formed thereon according to an embodiment of the invention, and in conjunction with fig. 7 and 8, a second gate 60 is formed at a second gate opening 61 of the heterojunction structure 202.
And S15, forming a source electrode and a drain electrode.
Specifically, each heterojunction structure comprises a source electrode and a drain electrode, wherein the source electrode corresponds to the source ohmic contact electrode, and the drain electrode corresponds to the drain ohmic contact electrode. On the same substrate, a source electrode, a corresponding source electrode ohmic contact electrode, a first grid electrode, a drain electrode and a corresponding drain electrode ohmic contact electrode form an enhancement type device; one source electrode, one corresponding source electrode ohmic contact electrode, one second grid electrode, one drain electrode and one corresponding drain electrode ohmic contact electrode form a depletion mode device. The source electrode and the drain electrode can be made of Ti/Al/Ti/Au, and the thickness of the Ti/Al/Ti/Au can be 20nm/110nm/40nm/50 nm.
In this embodiment, the source and the drain may be formed by sequentially performing the following steps: and (3) sequentially carrying out glue homogenizing, prebaking, photoetching, developing and postbaking on the heterojunction structure to define a source electrode opening graph and a drain electrode opening graph, wherein the source electrode opening graph corresponds to the source electrode ohmic contact electrode, and the drain electrode opening graph corresponds to the drain electrode ohmic contact electrode. And forming a source opening at the source opening pattern, forming a drain opening at the drain opening pattern, and forming the source opening and the drain opening by a gas etching method. And (3) sequentially carrying out glue homogenizing, prebaking, photoetching, developing and postbaking on the heterojunction structure with the source electrode opening and the drain electrode opening to define a source electrode graph and a drain electrode graph, wherein the source electrode graph corresponds to the source electrode opening, and the drain electrode graph corresponds to the drain electrode opening. And placing the heterojunction structure with the source electrode pattern and the drain electrode pattern into an electron beam evaporation device to deposit a source electrode layer and a drain electrode layer. And immersing the heterojunction structure deposited with the active electrode layer and the drain electrode layer in a dimethyl sulfoxide solution to realize metal stripping, isopropanol washing for 10 minutes, deionized water washing for 10 minutes and nitrogen blow-drying in a water bath heating mode at 60-80 ℃ so as to form a source electrode and a drain electrode.
Exemplarily, fig. 9 is a schematic diagram of a heterojunction structure with a source electrode and a drain electrode according to an embodiment of the present invention, as shown in fig. 9, a source electrode 70 and a drain electrode 80 are formed on each heterojunction structure, the source electrode 70 corresponds to the source ohmic contact electrode 30 one by one, and the drain electrode 80 corresponds to the drain ohmic contact electrode 40 one by one.
In summary, in the present embodiment, the same process and material can be used to form the source ohmic contact electrode and the drain ohmic contact electrode of the enhancement type device and the depletion type device, the first gate opening is precisely formed as the gate opening of the enhancement type device by the dry oxidation-wet etching repeated cycle method without etching damage, the first gate is formed, the second gate opening is formed as the gate opening of the depletion type device by the dry etching method, the second gate is formed, the same process and material can be used to form the source and the drain of the enhancement type device and the depletion type device, the preparation of the enhancement type device is realized, the compatibility of the enhancement type device and the depletion type device in the process and material is also realized, and the integration of the enhancement type device and the depletion type device is realized on the same substrate.
Optionally, the forming the first gate opening on the side of the heterojunction structure away from the substrate by using a dry oxidation-wet etching repeated cycle method includes: dry oxidation in oxygen plasma; and carrying out wet etching in hydrochloric acid solution.
In the embodiment of the present invention, oxygen (O) may be used as the oxygen plasma2) By applying, for example, oxygen (O) in an etching apparatus2) Ionization is performed to form oxygen plasma. Here, the GaN layer, the space isolation layer, and the barrier layer are dry-oxidized in oxygen plasma. And performing wet etching on the oxidized GaN layer, the space isolation layer and the barrier layer by using dilute hydrochloric acid (HCl), namely dissolving and removing oxides corresponding to the GaN layer, the space isolation layer and the barrier layer by using the wet etching. Oxygen (O) gas in which oxygen plasma is formed2) The flow rate can be 40sccm, and the ratio of the hydrochloric acid solution to water in the dilute hydrochloric acid can be 1: 3 to 1: 5. experiments prove that the dry oxidation with oxygen and the wet etching with dilute hydrochloric acid have the best effect. For example, a barrier layer (AlGaN) may be oxidized with oxygen to form gallium oxide (Ga)2O3) And alumina (Al)2O3) And the gallium oxide and the aluminum oxide can be completely removed by using dilute hydrochloric acid.
Example two
The embodiment provides a preparation method of an E/D-mode GaN HEMT integrated device based on the embodiment. The present embodiment is different from the above embodiments in that: a first passivation layer is also formed on the heterojunction structure after the source and drain ohmic contact electrodes are formed. Thus, the forming of the first gate opening on the side of the heterojunction structure away from the substrate by means of repeated cycles of dry oxidation-wet etching comprises: and etching the first passivation layer on one side of the heterojunction structure far away from the substrate, and etching the barrier layer and the space isolation layer in a dry oxidation-wet etching repeated circulation mode to form a first gate opening. The first passivation layer, the barrier layer and the space isolation layer at the first gate opening pattern are etched to form a first gate opening.
Forming the second gate opening includes: the first passivation layer is etched to form a second gate opening.
Fig. 10 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a second embodiment of the present invention, and as shown in fig. 10, the method includes:
s20, forming at least two GaN HEMT heterojunction structures on the substrate; the heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked.
And S21, forming a source ohmic contact electrode and a drain ohmic contact electrode on the side of the heterojunction structure far away from the substrate.
And S22, forming a first passivation layer on the side of the heterojunction structure far away from the substrate.
Specifically, the first passivation layer covers all the heterojunction structures, is formed to reduce channel leakage of the device, and improves the voltage endurance of the device. The material of the first passivation layer may be silicon nitride (Si)3N4) And the thickness of the first passivation layer may be 150 nm. The first passivation layer can be formed by evaporation through a chemical vapor deposition method.
Exemplarily, as shown in fig. 5, the first passivation layer 90 may cover the heterojunction structure, the isolation region 200, and other regions on the substrate 10 except for the heterojunction structure and the isolation region 200.
And S23, etching the first passivation layer on the side of the heterojunction structure far away from the substrate, and etching the barrier layer and the space isolation layer in a dry oxidation-wet etching repeated circulation mode to form a first gate opening.
Specifically, the principle of etching the barrier layer and the space isolation layer in a dry oxidation-wet etching repeated cycle manner is the same as that of step S12 in the first embodiment, but since the first passivation layer is formed on the heterojunction structure, forming the first gate opening further includes etching the first passivation layer at the first gate opening pattern.
In this embodiment, the first passivation layer etched at the first gate opening pattern may be formed by sequentially performing the following steps: and sequentially carrying out glue homogenizing, pre-baking, photoetching, developing and post-baking on the heterojunction structure which is formed with the first passivation layer and used for preparing the enhancement device to define a first grid opening pattern. Sulfur hexafluoride (SF) is adopted as the heterojunction structure with the first grid opening pattern6) And argon (Ar) gas mixture is used for etching the first passivation layer at the first gate opening pattern, and besides sulfur hexafluoride (SF) is used6) Trifluoromethane (CHF) may also be used3) Or carbon tetrafluoride (CF)4) And other fluorine-containing gases. And sequentially carrying out acetone cleaning for 5 minutes, isopropanol cleaning for 10 minutes, deionized water washing for 10 minutes and nitrogen blow-drying on the heterojunction structure of the first passivation layer at the position of the etched first grid opening pattern.
Illustratively, as shown in fig. 5, the first passivation layer 90, the barrier layer 23, and the space isolation layer 22 at the first gate opening pattern are sequentially etched away to form the first gate opening 50.
S24, forming a first gate at the first gate opening.
Specifically, the principle of forming the first gate at the first gate opening is the same as in step S13 of the first embodiment described above.
S25, etching the first passivation layer to form a second gate opening; and forming a second grid.
Specifically, the principle of forming the second gate opening is the same as that of step S14 of the first embodiment. Wherein forming a second gate opening at the second gate opening pattern comprises: using sulfur hexafluoride (SF)6) And etching the first passivation layer at the second grid opening pattern by using the mixed gas of argon (Ar) to form a second grid opening, and sequentially cleaning the heterojunction structure with the second grid opening for 5 minutes by using acetone, 10 minutes by using isopropanol and deionized waterRinsed for 10 minutes and blown dry with nitrogen. In addition, in addition to using sulfur hexafluoride (SF)6) Trifluoromethane (CHF) may also be used3) Or carbon tetrafluoride (CF)4) And other fluorine-containing gases.
The principle of forming the second gate at the second gate opening is the same as that of forming the second gate at step S14 of the first embodiment described above.
Illustratively, as shown in fig. 7, the first passivation layer 90 at the second gate opening pattern is etched to form the second gate opening 61. With reference to fig. 7 and 8, a second gate 60 is formed at the second gate opening 61.
And S26, forming a source electrode and a drain electrode.
Specifically, the principle of forming the source and the drain is the same as in step S15 of the first embodiment described above.
EXAMPLE III
The present embodiment provides a method for manufacturing an E/D-mode GaN HEMT integrated device based on the above embodiments, and the difference between the present embodiment and the first embodiment is as follows: forming a first gate opening on a side of the heterojunction structure away from the substrate in a dry oxidation-wet etching repeated cycle manner, comprising: etching the barrier layer and the space isolation layer on one side of the heterojunction structure far away from the substrate in a dry oxidation-wet etching repeated circulation mode to form a first opening; forming a first dielectric layer, wherein the first dielectric layer is positioned between the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode; forming a second passivation layer; the second passivation layer at the first opening is etched to form a first gate opening. Forming the second gate opening includes: the second passivation layer is etched to form a second gate opening.
Fig. 11 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a third embodiment of the present invention, and as shown in fig. 11, the method includes:
s30, forming at least two GaN HEMT heterojunction structures on the substrate; the heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked.
And S31, forming a source ohmic contact electrode and a drain ohmic contact electrode on the side of the heterojunction structure far away from the substrate.
S32, etching the barrier layer and the space isolation layer by adopting a dry oxidation-wet etching repeated circulation mode on one side of the heterojunction structure far away from the substrate to form a first opening; forming a first dielectric layer, wherein the first dielectric layer is positioned between the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode; forming a second passivation layer; the second passivation layer at the first opening is etched to form a first gate opening.
Specifically, the principle of forming the first opening by repeating the dry oxidation-wet etching cycle is the same as that of step S12 in the first embodiment.
Exemplarily, fig. 12 is a schematic structural diagram of forming a first opening on the heterojunction structure according to the third embodiment of the present invention, and as shown in fig. 12, the barrier layer 23 and the space isolation layer 22 are etched on the heterojunction structure to form a first opening 54.
And forming a first dielectric layer between the source ohmic contact electrode and the drain ohmic contact electrode, wherein the enhancement type device and the depletion type device with the first dielectric layer are Mis-GaN HEMT devices. Mis-GaN HEMT devices have a higher threshold voltage than GaN HEMT devices due to the presence of the first dielectric layer. The material of the first dielectric layer may be aluminum oxide (Al)2O3) Or hafnium oxide (HfO)2) In view of better compactness of alumina, it is preferable that the material of the first dielectric layer is alumina (Al)2O3) The thickness of the first dielectric layer may be 10nm to 25 nm.
The first dielectric layer may be formed by sequentially: and sequentially carrying out glue homogenizing, prebaking, photoetching, developing and postbaking on the heterojunction structure to define a first dielectric layer pattern. And placing the heterojunction structure with the first dielectric layer pattern into atomic layer deposition equipment, and depositing the first dielectric layer. And immersing the heterojunction structure deposited with the first dielectric layer in a dimethyl sulfoxide solution to realize metal stripping, isopropanol washing for 10 minutes, deionized water washing for 10 minutes and nitrogen blow-drying in a water bath heating mode at 60-80 ℃, so as to form the first dielectric layer between the source ohmic contact electrode and the drain ohmic contact electrode.
Exemplarily, fig. 13 is a schematic structural view of forming a first dielectric layer on the heterojunction structure according to the third embodiment of the present invention, and as shown in fig. 13, the first dielectric layer 24 is formed between the source ohmic contact electrode 30 and the drain ohmic contact electrode 40.
The principle of forming the second passivation layer is the same as that of forming the first passivation layer in step S22 of the second embodiment, and the second passivation layer is formed to reduce the channel leakage of the device and to improve the withstand voltage performance of the device. The material of the second passivation layer may be silicon nitride (Si)3N4) And the thickness of the second passivation layer may be 150 nm.
Exemplarily, fig. 14 is a schematic structural diagram of forming a second passivation layer on the heterojunction structure according to the third embodiment of the present invention, and as shown in fig. 14, a second passivation layer 91 is formed on the heterojunction structure.
Using sulfur hexafluoride (SF)6) And etching the second passivation layer at the first opening by using the mixed gas of argon (Ar) to form a first grid opening, and sequentially carrying out acetone cleaning for 5 minutes, isopropanol cleaning for 10 minutes, deionized water cleaning for 10 minutes and nitrogen blow-drying on the heterojunction structure with the first grid opening. Furthermore, trifluoromethane (CHF) may be used in addition to sulfur hexafluoride3) Or carbon tetrafluoride (CF)4) And other fluorine-containing gases.
Exemplarily, fig. 15 is a schematic structural diagram of a first gate opening formed after etching the second passivation layer at the first opening according to a third embodiment of the present invention, and in conjunction with fig. 14 and fig. 15, the second passivation layer 91 is etched at the first opening 54 to form the first gate opening 55.
S33, forming a first gate at the first gate opening.
Specifically, the principle of forming the first gate at the first gate opening is the same as in step S13 of the first embodiment described above.
Exemplarily, fig. 16 is a schematic diagram of a heterojunction structure with a first gate formed according to a third embodiment of the present invention, and in conjunction with fig. 15 and 16, a first gate 56 is formed at the first gate opening 55.
S34, etching the second passivation layer to form a second gate opening; and forming a second grid.
Specifically, the principle of etching the second passivation layer to form the second gate opening is the same as the principle of etching the first passivation layer to form the second gate opening in step S25 of the second embodiment described above.
Illustratively, fig. 17 is a schematic structural diagram of a second gate opening formed by etching a second passivation layer according to the third embodiment of the present invention, and as shown in fig. 17, the second passivation layer 91 at the second gate opening pattern is etched to form the second gate opening 63.
The principle of forming the second gate at the second gate opening is the same as that of forming the second gate at step S14 of the first embodiment described above.
Exemplarily, fig. 18 is a schematic diagram of a heterojunction structure for forming the second gate according to the third embodiment of the present invention, and in conjunction with fig. 17 and 18, a second gate 64 is formed at the second gate opening 63.
And S35, forming a source electrode and a drain electrode.
Specifically, the principle of forming the source and the drain is the same as in step S15 of the first embodiment described above.
Exemplarily, fig. 19 is a schematic diagram of a heterojunction structure with a source and a drain formed according to a third embodiment of the present invention, as shown in fig. 19, that is, integration of Mis enhancement mode devices N and Mis depletion mode devices M is realized on the same substrate. In summary, the difference between the present embodiment and the above-mentioned embodiment is that before forming the first gate opening and the second gate opening, a first dielectric layer is further formed between the source ohmic contact electrode and the drain ohmic contact electrode, so that the formed device is an Mis-GaN HEMT device.
Example four
The present embodiment provides a method for manufacturing an E/D-mode GaN HEMT integrated device based on the above embodiments, and the difference between the present embodiment and the first embodiment is as follows: forming a first gate opening on a side of the heterojunction structure away from the substrate in a dry oxidation-wet etching repeated cycle manner, comprising: etching the first passivation layer on one side of the heterojunction structure far away from the substrate, and etching the barrier layer by adopting a dry oxidation-wet etching repeated circulation mode to form a second opening; and oxidizing the space isolation layer at the second opening into a second dielectric layer to form a first gate opening. Forming the second gate opening includes: etching the first passivation layer to form a third opening; and oxidizing part of the barrier layer at the third opening into a third dielectric layer to form a second grid opening.
Fig. 20 is a flowchart of a method for manufacturing an E/D-mode GaN HEMT integrated device according to a fourth embodiment of the present invention, as shown in fig. 20, the method includes:
s40, forming at least two GaN HEMT heterojunction structures on the substrate; the heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked.
And S41, forming a source ohmic contact electrode and a drain ohmic contact electrode on the side of the heterojunction structure far away from the substrate.
And S42, forming a first passivation layer on the side of the heterojunction structure far away from the substrate.
The principle of forming the first passivation layer on the side of the heterojunction structure remote from the substrate is the same as in step S22 of the second embodiment described above.
S43, etching the first passivation layer on the side of the heterojunction structure far away from the substrate, and etching the barrier layer by adopting a dry oxidation-wet etching repeated circulation mode to form a second opening; and oxidizing the space isolation layer at the second opening into a second dielectric layer to form a first gate opening.
Specifically, the principle of etching the barrier layer to form the second openings by using the dry oxidation-wet etching repeated cycle is the same as the principle of etching the barrier layer and the space isolation layer to form the first openings by using the dry oxidation-wet etching repeated cycle in step S32 in the third embodiment. The difference is only that: step S32 of the third embodiment is to etch the barrier layer and the space isolation layer by using a dry oxidation-wet etching repeated cycle, and the step of this embodiment is to etch the barrier layer by using a dry oxidation-wet etching repeated cycle.
Exemplarily, fig. 21 is a schematic structural view of forming a second opening on the heterojunction structure according to the fourth embodiment of the present invention, and as shown in fig. 21, the first passivation layer 90 and the barrier layer 23 are etched on the heterojunction structure to form the second opening 57.
Passing the space isolation layer at the second opening through oxygen (O)240sccm) into a second dielectric layer. The enhancement mode device with the second dielectric layer is an Mis-GaN HEMT device. Mis-GaN HEMT devices have a higher threshold voltage than GaN HEMT devices due to the presence of the second dielectric layer. The material of the second dielectric layer may be aluminum oxide (Al)2O3)。
Exemplarily, fig. 22 is a schematic structural diagram of forming a second dielectric layer on the heterojunction structure according to the fourth embodiment of the present invention, and in combination with fig. 21 and fig. 22, the space isolation layer 22 at the second opening 57 is oxidized into the second dielectric layer 25 to form the first gate opening 58.
S44, forming a first gate at the first gate opening.
Specifically, the principle of forming the first gate at the first gate opening is the same as in step S13 of the first embodiment described above.
Exemplarily, fig. 23 is a schematic diagram of a heterojunction structure with a first gate formed according to the fourth embodiment of the present invention, and in combination with fig. 22 and fig. 23, a first gate 59 is formed at the first gate opening 58.
S45, etching the first passivation layer to form a third opening; oxidizing part of the barrier layer at the third opening into a third dielectric layer to form a second grid opening; and forming a second grid.
Specifically, the principle of etching the first passivation layer to form the third opening is the same as that of etching the first passivation layer to form the second gate opening in step S25 of the second embodiment.
And oxidizing part of the barrier layer at the third opening into a third dielectric layer, wherein the depletion mode device with the third dielectric layer is an Mis-GaN HEMT device. Mis-GaN HEMT devices have a higher threshold voltage than GaN HEMT devices due to the presence of the third dielectric layer. The material of the third dielectric layer may be aluminum oxide (Al)2O3) In addition, the thickness of the third dielectric layer may also be the same as the thickness of the second dielectric layer in the third embodiment.
Exemplarily, fig. 24 is a schematic structural diagram of forming a third dielectric layer on the heterojunction structure according to the fourth embodiment of the present invention, and as shown in fig. 24, a third dielectric layer 65 is formed.
The principle of forming the second gate at the second gate opening is the same as in step S25 of the second embodiment described above.
Exemplarily, fig. 25 is a schematic structural diagram of forming a second gate on the heterojunction structure according to the fourth embodiment of the present invention, and in conjunction with fig. 24 and fig. 25, a second gate 66 is formed at the third dielectric layer 65.
And S46, forming a source electrode and a drain electrode.
Specifically, the principle of forming the source and the drain is the same as in step S15 of the first embodiment described above.
Exemplarily, fig. 26 is a schematic diagram of a heterojunction structure with a source and a drain formed according to the fourth embodiment of the present invention, as shown in fig. 26, that is, integration of Mis enhancement mode devices N and Mis depletion mode devices M is realized on the same substrate.
In summary, the difference between the present embodiment and the above embodiments is: forming a first passivation layer on the heterojunction structure after forming the source electrode ohmic contact electrode and the drain electrode ohmic contact electrode; etching the first passivation layer and the barrier layer to form a second opening on the heterojunction structure for preparing the enhancement device, and oxidizing a space isolation layer at the second opening into a second dielectric layer to form a first gate opening; and etching the first passivation layer to form a third opening on the heterojunction structure for preparing the depletion mode device, and oxidizing the barrier layer at the third opening into a third dielectric layer to form a second gate opening. In addition, the method of the third embodiment is simpler to integrate Mis enhancement mode devices and Mis depletion mode devices than the method of the third embodiment is to integrate Mis enhancement mode devices and Mis depletion mode devices.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A preparation method of an E/D-mode GaN HEMT integrated device is characterized by comprising the following steps:
forming at least two GaN HEMT heterojunction structures on a substrate; the heterojunction structure comprises a GaN layer, a space isolation layer and a barrier layer which are sequentially stacked;
forming a source electrode ohmic contact electrode and a drain electrode ohmic contact electrode on one side of the heterojunction structure far away from the substrate;
forming a first grid opening on one side of the heterojunction structure far away from the substrate in a dry oxidation-wet etching repeated circulation mode;
forming a first gate at the first gate opening;
forming a second gate opening and a second gate;
and forming a source electrode and a drain electrode.
2. The method of claim 1, wherein forming a first gate opening on a side of the heterojunction structure remote from the substrate in a dry oxidation-wet etching repeating cycle comprises:
dry oxidation in oxygen plasma;
and carrying out wet etching in hydrochloric acid solution.
3. The method for manufacturing an E/D-mode GaN HEMT integrated device according to claim 1, further comprising, after forming a source ohmic contact electrode and a drain ohmic contact electrode on a side of said heterojunction structure remote from the substrate:
and forming a first passivation layer on one side of the heterojunction structure far away from the substrate.
4. The method of claim 3, wherein the forming a first gate opening on the side of the heterojunction structure away from the substrate in a dry oxidation-wet etching repeated cycle manner comprises:
and etching the first passivation layer on one side of the heterojunction structure far away from the substrate, and etching the barrier layer and the space isolation layer in a dry oxidation-wet etching repeated circulation mode to form the first grid opening.
5. The method of fabricating an E/D-mode GaN HEMT integrated device according to claim 4, wherein forming a second gate opening comprises:
and etching the first passivation layer to form the second grid opening.
6. The method of claim 1, wherein forming a first gate opening on a side of the heterojunction structure remote from the substrate in a dry oxidation-wet etching repeating cycle comprises:
etching the barrier layer and the space isolation layer by adopting a dry oxidation-wet etching repeated circulation mode on one side of the heterojunction structure far away from the substrate to form a first opening;
forming a first dielectric layer, wherein the first dielectric layer is positioned between the source ohmic contact electrode and the drain ohmic contact electrode;
forming a second passivation layer;
and etching the second passivation layer at the first opening to form the first gate opening.
7. The method of fabricating an E/D-mode GaN HEMT integrated device according to claim 6, wherein forming a second gate opening comprises:
and etching the second passivation layer to form the second gate opening.
8. The method of claim 3, wherein the forming a first gate opening on the side of the heterojunction structure away from the substrate in a dry oxidation-wet etching repeated cycle manner comprises:
etching a first passivation layer on one side of the heterojunction structure far away from the substrate, and etching the barrier layer by adopting a dry oxidation-wet etching repeated circulation mode to form a second opening;
and oxidizing the space isolation layer at the second opening into a second dielectric layer to form the first gate opening.
9. The method of fabricating an E/D-mode GaN HEMT integrated device according to claim 8, wherein forming a second gate opening comprises:
etching the first passivation layer to form a third opening;
and oxidizing part of the barrier layer at the third opening into a third dielectric layer to form the second grid opening.
10. The method of fabricating an E/D-mode GaN HEMT integrated device according to claim 9, wherein the material of said second and third dielectric layers comprises aluminum oxide.
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| US20190259865A1 (en) * | 2018-12-29 | 2019-08-22 | Suzhou Han Hua Semiconductor Co.,Ltd | Integrated enhancement/depletion mode hemt and method for manufacturing the same |
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| CN107887383A (en) * | 2017-11-06 | 2018-04-06 | 中国科学院微电子研究所 | GaN base monolithic power inverter and preparation method thereof |
| US20190259865A1 (en) * | 2018-12-29 | 2019-08-22 | Suzhou Han Hua Semiconductor Co.,Ltd | Integrated enhancement/depletion mode hemt and method for manufacturing the same |
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