CN112820774A - GaN device and preparation method thereof - Google Patents

GaN device and preparation method thereof Download PDF

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CN112820774A
CN112820774A CN202011613280.5A CN202011613280A CN112820774A CN 112820774 A CN112820774 A CN 112820774A CN 202011613280 A CN202011613280 A CN 202011613280A CN 112820774 A CN112820774 A CN 112820774A
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layer
electrode
substrate
inaln
gan
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蒋洋
于洪宇
汪青
郑韦志
乔泽鹏
范梦雅
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Southwest University of Science and Technology
Southern University of Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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  • Microelectronics & Electronic Packaging (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The embodiment of the invention discloses a GaN device and a preparation method thereof. The device comprises a substrate, a buffer layer, a GaN layer, an AlN layer, an InAlN layer, a source electrode, a drain electrode and a grid electrode, wherein the substrate, the buffer layer, the GaN layer, the AlN layer and the InAlN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are formed on one side, far away from the substrate, of the InAlN layer, and the source electrode and the drain electrode are made5Al1And a laminated structure of TiN or Ti5Al1And W is a laminated structure using Ti5Al1And TiN, Ti5Al1And the material characteristics of W, the source electrode and the drain electrode are contacted with the GaN layer, the AlN layer and the InAlN layer to form an ohmic contact electrode mechanism, so that ohmic contact resistance is effectively reduced, the on-resistance of a GaN device is reduced, in addition, a normally-off GaN device is formed by utilizing an ALE etching process, the low-speed and low-loss etching is realized while the on-resistance is reduced, and the etching depth is accurately controlledTherefore, the grid leakage is effectively reduced, and the high withstand voltage value and the threshold voltage of the device are improved.

Description

GaN device and preparation method thereof
Technical Field
The embodiment of the invention relates to the technical field of GaN radio frequency devices, in particular to a GaN device and a preparation method thereof.
Background
Gallium nitride (GaN) materials have wide forbidden bandwidth, high breakdown electric field, high thermal conductivity, high electron saturation rate and higher radiation resistance, and have wide application prospects in high-temperature, high-frequency, radiation-resistant and high-power semiconductor devices. GaN-based High Electron Mobility Transistors (HEMTs) have been widely used in the fields of microwave communications and power electronic conversion.
The on-resistance of the GaN HEMT device is a key index affecting the performance of the device, for example, the GaN HEMT device has a large on-resistance, and is characterized by a reduction in output power density in a radio frequency device and an increase in conduction loss in a power electronic device, thereby affecting the power conversion efficiency, and meanwhile, the large on-resistance causes a large heat productivity of the device, and increases the heat dissipation cost or even affects the reliability of the device. At present, the channel resistance of an epitaxial material is reduced mainly by increasing the two-dimensional electron gas concentration of the channel of the epitaxial material, the gate length of a unit area is increased in the aspect of device design, the contact resistance of an ohmic contact electrode is reduced in the aspect of device technology, and the like, so that the on-resistance of a radio frequency device is reduced.
Disclosure of Invention
The embodiment of the invention provides a GaN device and a preparation method thereof, which can effectively reduce the on-resistance of the device, simplify the preparation process and reduce the manufacturing cost of the device.
In a first aspect, embodiments of the present invention provide a GaN device, including:
the substrate, the buffer layer, the GaN layer, the AlN layer and the InAlN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are formed on one side, far away from the substrate, of the InAlN layer;
wherein the source electrode and the drain electrode are made of Ti5Al1 and TiN or Ti5Al1And a laminated structure of W.
Optionally, the gate is located on the InAlN layer.
Optionally, a gate groove is formed in the InAlN layer corresponding to the gate;
the GaN device further comprises a grid electrode dielectric layer, and the grid electrode dielectric layer and the grid electrode are sequentially stacked in the grid electrode groove.
Optionally, the Ti5Al1And a laminated structure of TiN or the Ti5Al1And the thickness of the laminated structure of W ranges from 60 to 80 nm.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a GaN device, where the method includes:
providing a substrate;
sequentially forming a buffer layer, a GaN layer, an AlN layer and an InAlN layer on the substrate;
a source electrode, a drain electrode and a grid electrode are arranged on one side of the InAlN layer far away from the substrate;
wherein the source electrode and the drain electrode are made of Ti5Al1And a laminated structure of TiN or Ti5Al1And a laminated structure of W.
Optionally, the source, the drain and the gate at a side of the InAlN layer away from the substrate include:
forming the source electrode and the drain electrode on the surface of the InAlN layer far away from the substrate;
and forming the gate on the surface of the InAlN layer far away from the substrate.
Optionally, the source, the drain and the gate at a side of the InAlN layer away from the substrate include:
forming the source electrode and the drain electrode on the surface of the InAlN layer far away from the substrate;
forming a gate groove on the surface of the InAlN layer far away from the substrate by adopting an ALE etching process;
forming a grid electrode dielectric layer in the grid electrode groove;
and forming the grid electrode on the grid electrode dielectric layer in the grid electrode groove.
And forming other metal layers in the metal electrode layer.
The GaN device comprises a substrate, a buffer layer, a GaN layer, an AlN layer, an InAlN layer, a source electrode, a drain electrode and a grid electrode, wherein the substrate, the buffer layer, the GaN layer, the AlN layer and the InAlN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are formed on one side, far away from the substrate, of the InAlN layer, wherein the source electrode and the drain electrode are made of Ti5Al1And a laminated structure of TiN or Ti5Al1And W is a laminated structure using Ti5Al1And TiN, Ti5Al1And the source electrode and the drain electrode are in contact with the GaN layer, the AlN layer and the InAlN layer to form an ohmic contact electrode mechanism according to the polarization characteristic of the W material, so that ohmic contact resistance is effectively reduced, the on-resistance of the GaN device is reduced, in addition, the normally-off GaN device is formed by utilizing the ALE etching process, low-speed and low-loss etching is realized while the on-resistance is reduced, meanwhile, the etching depth is accurately controlled, the grid leakage is effectively reduced, and the high withstand voltage value and the threshold voltage of the device are improved.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic structural diagram of a GaN device according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another GaN device provided by an embodiment of the invention;
FIG. 3 is a schematic flow chart of a method for fabricating a GaN device according to an embodiment of the invention;
fig. 4a to fig. 4h are schematic process diagrams of a preparation method for forming a buffer layer, an epitaxial layer and a metal electrode layer according to an embodiment of the present invention;
fig. 5 is a schematic flow chart illustrating a process of forming a source, a drain and a gate according to an embodiment of the invention;
FIG. 6 is a schematic diagram of another process for forming a source, a drain and a gate according to an embodiment of the present invention;
fig. 7a to fig. 7e are schematic process diagrams of another preparation method for forming a buffer layer, an epitaxial layer and a metal electrode layer according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be noted that, in order to further explain the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the GaN device and the method for manufacturing the same according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
Fig. 1 is a schematic structural diagram of a GaN device according to an embodiment of the present invention. As shown in FIG. 1, the device comprises a substrate 10, a buffer layer 11, a GaN layer 12, an AlN layer 13, InAlN layers 14 and a source electrode 15, a drain electrode 16 and a grid electrode 17 which are sequentially stacked, wherein the InAlN layer 14 is formed on the side far away from the substrate, the source electrode 15 and the drain electrode 16 are made of Ti5Al1And a laminated structure of TiN or Ti5Al1And a laminated structure of W.
GaN, i.e., a gallium nitride material, is a semiconductor material having a wide forbidden band width, a high breakdown electric field, a high thermal conductivity, a high electron saturation rate, and a high radiation resistance. The GaN-based High Electron Mobility Transistor (HEMT) can be widely applied to the fields of microwave communication, electronic conversion and the like, and the on-resistance of the GaN HEMT device is a key index influencing the performance of the device. In an electronic power device, the large on-resistance leads to large heat productivity of the device, increases the heat dissipation cost and even affects the reliability of the device. In general, the on-resistance Ron of a GaN HEMT device can be roughly calculated by the following formula: ron is 2Rc + Rsh Lsd, where Ron is on-resistance, Rc is ohmic contact resistance, Rsh is channel resistance, and Lsd is channel length, and in a GaN power device, the channel resistance Rsh is the main factor affecting on-resistance Ron, while in a radio frequency device, the ohmic contact resistance Rc is the main factor affecting on-resistance Ron.
The InAlN layer 14 far away from the substrate 10 is made of a heterojunction material, has the characteristics of large interface gap difference and strong spontaneous polarization, can effectively inhibit short channel effect caused by the proportional reduction of the size of a device, and can greatly reduce the resistance of a parasitic channel. In this embodiment, the thickness of the InAlN layer 14 ranges from 5 nm to 20nm, where the In component is 0.17 and the Al component is 0.83, and the InAlN layer 14, the AlN layer 13, and the GaN layer 12 form an epitaxial structure of the device, which can realize a lower channel resistance of the epitaxial material, and the channel resistance is about 200-. In addition, the AlN layer 13 has a thickness in the range of 1 to 3nm, and the substrate 10 may be made of silicon, silicon carbide, GaN, or sapphire.
Wherein, a metal electrode layer is arranged on the InAlN layer 14 far from the substrate 10 side, the metal electrode layer comprises a source electrode 15, a drain electrode 16 and a grid electrode 17, Ti is arranged on the region of the source electrode 15 and the drain electrode 16 in a laminating way5Al1And a TiN structure or Ti5Al1And W structure of Ti as a forming material5Al1And a laminated structure of TiN or Ti5Al1And a source electrode 15 and a drain electrode 16 of a laminated structure of W. The ohmic contact resistance is reduced by the mechanism of forming the ohmic contact electrode by contacting the source electrode 15, the drain electrode 16 and the gate electrode 17 with the GaN layer 12, the AlN layer 13 and the InAlN layer 14, and by utilizing the unique properties of the materials of the stacked structure of the source electrode and the drain electrode.
In particular, with Ti5Al1The main characteristics of the source electrode and the drain electrode which are made of the materials are that Ti can react with N element in the InAlN layer 14 to form a TiN layer, the TiN layer is arranged between the source electrode 15 and the drain electrode 16 and the InAlN layer 14, ohmic contact can be well formed, and the formed ohmic contact is small in resistance. In addition, Ti5Al1Al element in the material can inhibit Al element in the InAlN layer 14 from diffusing outwards, and two-dimensional electron gas concentration in the InAlN can be well reservedAnd thus a better ohmic contact effect is achieved, therefore Ti is used5Al1And TiN material or Ti5Al1And the source electrode and the drain electrode formed by the W material can effectively reduce the ohmic contact resistance, thereby reducing the on-resistance of the device.
The GaN device provided by the embodiment comprises a substrate, a buffer layer, a GaN layer, an AlN layer, an InAlN layer, a source electrode, a drain electrode and a grid electrode, wherein the substrate, the buffer layer, the GaN layer, the AlN layer and the InAlN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are formed on one side, far away from the substrate, of the InAlN layer, and the source electrode and the drain electrode are5Al1And a laminated structure of TiN or Ti5Al1And W is a laminated structure using Ti5Al1And TiN, Ti5Al1And the source electrode and the drain electrode are in contact with the GaN layer, the AlN layer and the InAlN layer to form an ohmic contact electrode mechanism according to the characteristics of the W material, so that ohmic contact resistance is effectively reduced, the on-resistance of the GaN device is reduced, in addition, the normally-off GaN device is formed by utilizing the ALE etching process, the low-speed and low-loss etching is realized while the on-resistance is reduced, meanwhile, the etching depth is accurately controlled, the grid leakage is effectively reduced, and the high withstand voltage value and the threshold voltage of the device are improved.
Optionally, referring to fig. 1, a gate 17 is located on the InAlN layer 14.
Wherein, on the basis of the above embodiment, the source electrode 15 and the drain electrode 16 are made of Ti5Al1And a laminated structure of TiN or Ti5Al1And W, and ohmic contact is generated between the W and the InAlN layer 14, so that the device is normally opened, and the ohmic contact resistance is reduced.
Optionally, fig. 2 is a schematic structural diagram of another GaN device provided in an embodiment of the present invention. As shown in fig. 2, the InAlN layer 14 is provided with a gate groove 18 corresponding to the gate.
The gate groove 18 is disposed in a gate region on a side of the InAlN layer 14 away from the substrate, and a depth of the gate region groove 18 is the same as a thickness of the InAlN layer 14.
Since the gate recess 18 is formed in the gate region, the two-dimensional electron gas of the gate region portion is depleted, so that a current cannot flow from the source to the drain under normal conditions, and thus, it is in an off state. A groove is formed in the InAlN layer 14 corresponding to the grid, and other dielectric layers can be added into the grid groove 18 to reduce the electric leakage of the grid and improve the threshold voltage of the device, so that the normal close of the GaN device is realized.
In addition, compared with the conventional ICP gate concave gate etching, the normally-off GaN device with the gate groove 18 etched in the gate region can effectively reduce the electric leakage phenomenon of the GaN device, and the gate, the source and the drain jointly form a metal electrode layer, and Ti is used5Al1And TiN or Ti5Al1And the source and drain of the W material are in ohmic contact with the GaN layer 12, the AlN layer 13, or the InAlN layer 14, the gate electrode is provided with the gate recess 18 to also achieve the effect of reducing the ohmic contact resistance.
Optionally, Ti5Al1And a laminated structure of TiN or Ti5Al1And the thickness of the laminated structure of W ranges from 60 to 80 nm.
Fig. 3 is a schematic flow chart of a method for manufacturing a GaN device according to an embodiment of the present invention. As shown in fig. 3, the method specifically includes the following steps:
s310, providing a substrate.
Wherein after the substrate is provided, the substrate is cleaned by an ultrasonic cleaning process to remove impurities on the surface of the substrate.
Specifically, the substrate is ultrasonically cleaned for 5 minutes by acetone, ultrasonically cleaned for 10 minutes by isopropanol and finally cleaned for 10 minutes by deionized water by adopting an ultrasonic cleaning process, and dried by using nitrogen after the cleaning is finished, so that the aim of removing impurities on the surface of the substrate is fulfilled.
Acetone and isopropyl alcohol are representative compounds of aliphatic ketones, and are useful as a solution for ultrasonic cleaning because they can dissolve substances, can be used as a safe dissolving agent, do not cause harm to human health, and do not adversely affect the environmental level of a workplace.
And S320, sequentially forming a buffer layer, a GaN layer, an AlN layer and an InAlN layer on the substrate.
S330, a source electrode, a drain electrode and a grid electrode are arranged on the InAlN layer on the side far away from the substrate.
Specifically, before a source electrode, a drain electrode and a grid electrode on one side of the InAlN layer far away from the substrate, an integral structure formed by the substrate, the buffer layer, the GaN layer, the AlN layer and the InAlN layer is processed by adopting a glue homogenizing process, a pre-baking process, a photoetching process, a developing process and a post-baking process in sequence, and an isolation graph of the whole structure is defined. And after defining the isolation pattern, etching the defined isolation pattern by adopting a plasma coupling etching process, wherein when the isolation pattern is etched, the GaN layer, the AlN layer and the InAlN layer which are partially positioned above the buffer layer are etched.
It should be noted that, when the plasma coupled etching process is used to perform the etching process, chlorine gas etching may be used, or other chlorine-based etching gases may be used.
Specifically, after the isolation pattern of the device is formed, an ultrasonic cleaning process in the first step is performed to remove impurities on the surface of the device after the isolation pattern is formed. And sequentially performing a glue homogenizing process, a pre-baking process, a photoetching process, a developing process and a post-baking process to define ohmic contact patterns of a source electrode and a drain electrode on the InAlN layer.
In addition, when the well-defined isolation pattern is etched by adopting the plasma coupling etching process, the etching depth is 300-500 nm.
Wherein, the source electrode and the drain electrode are made of a laminated structure of Ti5Al1 and TiN or a laminated structure of Ti5Al1 and W.
Specifically, after ohmic contact patterns of a source electrode and a drain electrode are formed on the InAlN layer, the device is immersed in diluted hydrochloric acid solution to remove a natural oxidation layer on the surface of the whole structure after the source electrode, the drain electrode and the grid electrode are formed, then the device is washed for 10 minutes by deionized water, and after the washing is finished, the device is dried by nitrogen to carry out the next process operation.
And putting the whole device for forming the source electrode, the drain electrode and the grid electrode into a transmission cavity of the magnetron sputtering equipment, and adopting an evaporation process to prevent the surface of the device from being oxidized so as to influence the ohmic contact effect. Then, Ti is deposited on a source electrode area and a drain electrode area on the InAlN layer by adopting a film coating process5Al1And TiN alloy or deposited Ti5Al1And W alloy to form source and drain electrodesTi of (A)5Al1And a metal cap layer of TiN or Ti5Al1And a metal cap layer of W, and then Ti formed on the source region and the drain region on the InAlN layer5Al1And a metal cap layer of TiN or Ti5Al1And performing a water bath heating process at 60-80 ℃ on the metal cap layer of the W to strip the metal cap layer, after the stripping is completed, performing an ultrasonic cleaning process to clean the stripped device, flushing the device with deionized water for 10 minutes, and after the flushing is completed, drying the device with nitrogen to form a source electrode and a drain electrode on one side of the InAlN layer, which is far away from the substrate.
And then, after the source electrode and the drain electrode are formed, an annealing process is carried out on the structure formed by the substrate, the buffer layer, the GaN layer, the AlN layer, the InAlN, the source electrode and the drain electrode as an integral structure so as to realize better ohmic contact effect between the source electrode and the drain electrode and the GaN layer, the AlN layer or the InAlN layer. Wherein, the annealing process can be performed at 1000sccm N2The reaction is carried out in an atmosphere, and the temperature can be set between 800 ℃ and 1000 ℃.
Next, on the basis of the above steps, a source electrode and a drain electrode are defined. The photoresist homogenizing process, the pre-baking process, the photoetching process, the developing process and the post-baking process in the embodiment are sequentially adopted, a first layer of metal pad graph is defined in the source electrode area and the drain electrode area, then, an electron beam evaporation process is adopted to evaporate a first layer of pad metal in the defined area, wherein the first layer of pad metal in the source electrode area and the drain electrode area can be Ti and Au, or Ni or Au, the thickness range of Ti is 10-30nm, the thickness range of Au is 50-100nm, and the thickness range of Ni is 10-30 nm.
And then, on the basis of the steps, immersing the evaporated device with the first layer of pad metal in a dimethyl sulfoxide solution, performing a water bath heating process at the temperature of 60-80 ℃ to strip the film layer formed by evaporation, performing an ultrasonic cleaning process in the steps for cleaning for 10 minutes after the stripping is finished, washing for 10 minutes by using deionized water, and drying by using nitrogen after the washing is finished to form the first layer of metal pad on the drain electrode and the source electrode.
And then, after a first layer of metal pad is formed, defining the position of a grid on the InAlN layer by adopting an electron beam lithography process. And then, carrying out an electron beam evaporation process on the whole structure with the well-defined grid electrode position, and depositing grid electrode metal Ti and Au, or Ni and Au in the grid electrode area.
And then, performing a water bath heating process and an ultrasonic cleaning process in the steps to strip the film layer plated in the electron beam evaporation to form the grid metal.
After forming the source, the drain, and the gate on the InAlN layer away from the substrate, further processing is required to prevent the occurrence of leakage during device operation and to achieve better contact between the metal electrode layer and the GaN layer, the AlN layer, or the InAlN layer.
Specifically, on the basis of the steps, the substrate, the buffer layer, the GaN layer, the AlN layer, the InAlN layer, the source electrode, the drain electrode, the grid electrode and the first metal pad layer are used as an integral structure, and the integral structure is placed in Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment for evaporating a layer of Si with the thickness of 50-150nm3N4And a passivation layer.
In the cvd apparatus, a gas is excited to generate a low-temperature plasma, thereby enhancing the chemical activity of a reaction material and performing epitaxy.
Then, a substrate, a buffer layer, a GaN layer, an AlN layer, an InAlN layer, a source electrode, a drain electrode, a grid electrode, a first metal pad layer and Si3N4And the passivation layer is used as an integral structure, and the integral structure is subjected to the post-baking processes of the glue homogenizing process, the pre-baking process, the photoetching process and the developing process which are summarized in the steps in sequence so as to define the opening patterns of the source electrode, the drain electrode and the grid electrode.
Then, adopting plasma coupling etching process to define the opening patterns of the source electrode, the drain electrode and the grid electrode at SF6Etching in/Ar etching gas to remove Si on the surface3N4The shield layer forms an opening. And (4) removing impurities on the surface of the device by adopting the ultrasonic cleaning process in the steps.
And then, sequentially performing a glue spreading process, a pre-baking process, a photoetching process, a developing process and a post-baking process on the device with the formed opening to define a second layer pad metal pattern of the source electrode, the drain electrode and the grid electrode. And depositing a layer of Ti and Au or Ni and Au on the defined second layer pad metal pattern position by adopting an evaporation process. Similarly, the thickness of Ti and Ni ranges from 10 nm to 30nm, and the thickness of Au ranges from 150nm to 250 nm.
And then, immersing a layer of Ti and Al or Ti and Au on the position of the plated second layer of pad metal pattern in a dimethyl sulfoxide solution, stripping the film layer by a water bath heating process at 60-80 ℃, executing an ultrasonic cleaning process after the stripping is finished, sequentially washing for 10 minutes by using isopropanol and washing for 10 minutes by using deionized water, and blow-drying by using nitrogen after the cleaning is finished, thereby finally forming the device taking the substrate, the buffer layer, the GaN layer, the AlN layer, the InAlN layer, the source electrode, the drain electrode, the grid electrode, the first layer of pad metal, the second layer of pad metal and the passivation layer as an integral structure.
The following is a specific description of the preparation method of the present invention for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate.
Referring to fig. 4a, a buffer layer 11, a GaN layer 12, an AlN layer 13, and an InAlN layer 14 are sequentially formed on a substrate.
Referring to fig. 4b, before the source, the drain and the gate on the side of the InAlN layer away from the substrate, an isolation pattern of the whole structure is defined.
Referring to fig. 4c, the well-defined isolation pattern is etched using a plasma coupled etch process to deposit Ti on the InAlN layer 14 in the source region 15 and the drain region 165Al1And TiN alloy or deposited Ti5Al1And a W alloy.
Referring to fig. 4d, a first layer of pad metal 18 is evaporated in the source and drain regions using an e-beam evaporation process.
Referring to fig. 4e, a gate metal 19 of Ti and Au, or Ni and Au, is deposited in the gate region.
Referring to FIG. 4f, a layer of Si is evaporated on top3N4A passivation layer 20.
Referring to fig. 4g, an opening pattern of the source, drain and gate electrodes is defined, and an opening 21 is formed at the opening pattern of the source, drain and gate electrodes.
Referring to fig. 4h, a second layer of pad metal 22 is evaporated at the source, drain and gate openings 21.
Fig. 5 is a schematic flow chart of forming a source, a drain, and a gate according to an embodiment of the invention. As shown in fig. 5, the method for forming the source, the drain and the gate on the InAlN layer away from the substrate specifically includes the following steps:
and S510, forming a source electrode and a drain electrode on the surface of the InAlN layer far away from the substrate.
And S520, forming a gate on the surface of the InAlN layer far away from the substrate.
It should be noted that, in this embodiment, the process method for forming the source, the drain, and the gate on the surface of the InAlN layer away from the substrate is the same as the process method in the above embodiment, and is not described herein again.
In addition, the device finally formed by taking the substrate, the buffer layer, the GaN layer, the AlN layer, the InAlN layer, the source electrode, the drain electrode, the gate electrode, the first pad metal layer, the second pad metal layer and the passivation layer as a whole structure can be a normally-on device.
Fig. 6 is a schematic flow chart of forming a source, a drain and a gate according to another embodiment of the present invention. As shown in fig. 6, the method for forming the source, the drain and the gate on the InAlN layer away from the substrate specifically includes the following steps:
and S610, forming a source electrode and a drain electrode on the surface of the InAlN layer far away from the substrate.
It should be noted that, the process method for forming the source and the drain on the surface of the InAlN layer away from the substrate in this embodiment is the same as the process method in the above embodiment, and is not described herein again.
And S620, forming a gate groove on the surface of the InAlN layer far away from the substrate by adopting an atomic layer etching process.
In addition, after the gate and the first metal pad are formed, recess gate etching is performed on the gate, so that a recess is formed in a region corresponding to the gate on the InAlN layer and extends in the directions of the buffer layer and the substrate.
The depth of the groove formed in the gate region is kept the same as the thickness of the InAlN layer.
Specifically, the substrate, the buffer layer, the GaN layer, the AlN layer, the InAlN layer, the source electrode, the drain electrode and the grid electrode which are prepared and used as an integral structure are subjected to an atomic layer etching process to realize the groove at the grid electrode, the integral structure after the groove is formed is subjected to oxidation treatment and chlorine gas to remove an oxide layer in sequence, and atomic layer stripping etching of the surface of the InAlN layer of the integral structure is realized.
And S630, forming a grid dielectric layer in the grid groove.
Specifically, on the basis of the steps, the whole structure with the formed gate groove is placed into atomic layer deposition equipment to deposit a dielectric layer in a gate region.
It should be noted that the material of the dielectric layer may be Al2O3Or HfO2And the thickness of the dielectric layer ranges from 10 nm to 20 nm.
And S640, forming a grid on the grid dielectric layer in the grid groove.
Specifically, the whole structure with the dielectric layer deposited at the grid groove is placed into an electron beam evaporation device by adopting an electron beam evaporation process, and a layer of grid metal is deposited on the surface of the dielectric layer so as to realize the conductive contact of the metal electrode layer and the GaN layer, the AlN layer or the InAlN layer.
Wherein the thickness of Ti ranges from 10 nm to 30nm, the thickness of Au ranges from 50nm to 100nm, and the thickness of Ni ranges from 10 nm to 30 nm.
Next, the same water bath heating process as in the above embodiment was performed, the entire structure deposited with the gate metal at the gate groove was immersed in a dimethyl sulfoxide solution, and the water bath heating process was performed at a water bath temperature of 60 to 80 ℃ to peel off the film layer formed when the evaporation process was performed. And after the stripping is finished, performing the ultrasonic cleaning process in the steps, sequentially washing for 10 minutes by using isopropanol and for 10 minutes by using deionized water, and drying by using nitrogen.
Then, adopting an evaporation process, putting the integral structure after the metal film layer is deposited into plasma enhanced chemical vapor deposition equipment, and executing the evaporation process to deposit a layer of Si with the thickness of 50-150nm on the surface of the integral structure3N4And a passivation layer.
Then, a substrate, a buffer layer, a GaN layer, an AlN layer, an InAlN layer, a source electrode, a drain electrode, a grid electrode, a first metal pad layer and Si3N4And the passivation layer is used as an integral structure, and the integral structure is subjected to the post-baking processes of the glue homogenizing process, the pre-baking process, the photoetching process and the developing process which are summarized in the steps in sequence so as to define the opening patterns of the source electrode, the drain electrode and the grid electrode.
Then, adopting plasma coupling etching process to define the opening patterns of the source electrode, the drain electrode and the grid electrode at SF6Etching in/Ar etching gas to remove Si on the surface3N4The shield layer forms an opening. And (4) removing impurities on the surface of the device by adopting the ultrasonic cleaning process in the steps.
And then, sequentially performing a glue spreading process, a pre-baking process, a photoetching process, a developing process and a post-baking process on the device with the formed opening to define a second layer pad metal pattern of the source electrode, the drain electrode and the grid electrode. And depositing a layer of Ti and Au or Ni and Au on the defined second layer pad metal pattern position by adopting an evaporation process. Similarly, the thickness of Ti and Ni ranges from 10 nm to 30nm, and the thickness of Au ranges from 150nm to 250 nm. And then, immersing a layer of Ti and Al or Ti and Au on the position of the plated second layer of pad metal pattern in a dimethyl sulfoxide solution, stripping the film layer by a water bath heating process at 60-80 ℃, executing an ultrasonic cleaning process after the stripping is finished, sequentially washing for 10 minutes by using isopropanol and for 10 minutes by using deionized water, and drying by using nitrogen after the cleaning is finished, thereby finally forming the normally closed device of the concave grid with the substrate, the buffer layer, the GaN layer, the AlN layer, the InAlN layer, the source electrode, the drain electrode, the grid electrode, the first layer of pad metal, the second layer of pad metal and the passivation layer as an integral structure.
The following is a specific description of the preparation method of the present invention for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate.
With continued reference to fig. 4a, a buffer layer 11, a GaN layer 12, an AlN layer 13, and an InAlN layer 14 are sequentially formed on the substrate.
With continued reference to fig. 4b, an isolation pattern is defined for the entire structure before the source, drain and gate on the side of the InAlN layer 14 away from the substrate 10.
With continued reference to fig. 4c, the well-defined isolation pattern is etched using a plasma-coupled etch process to deposit Ti on the InAlN layer 14 in the source region 15 and the drain region 165Al1And TiN alloy or deposited Ti5Al1And a W alloy.
With continued reference to fig. 4d, a first layer of pad metal 17 is evaporated in the source and drain regions using an electron beam evaporation process.
Referring to fig. 7a, in the gate region of the InAlN layer 14, a gate groove 23 is formed on the surface of the InAlN layer 14 away from the substrate by using an atomic layer etching process.
Referring to fig. 7b, the whole structure after the gate recess 23 is formed is placed in an atomic layer deposition device to deposit a dielectric layer 24 in the gate region.
With continued reference to fig. 7b, the entire structure with the dielectric layer deposited in the gate recess is placed in an electron beam evaporation apparatus, and a layer of gate metal 25 is deposited on the surface of the dielectric layer.
Referring to FIG. 7c, a layer of Si is evaporated on the surface of the integrated structure3N4 A passivation layer 20.
Referring to fig. 7d, opening patterns of the source, drain and gate electrodes are defined, and openings 21 are formed at the opening patterns of the source, drain and gate electrodes.
Referring to fig. 7e, a second layer of pad metal 22 is evaporated at the openings 25 of the source, drain and gate electrodes.
According to the technical scheme provided by the embodiment, the source electrode and the drain electrode are formed on the surface, far away from the substrate, of the InAlN layer, the gate groove is formed on the surface, far away from the substrate, of the InAlN layer by adopting the ALE etching process, the gate dielectric layer is formed in the gate groove, and the gate electrode is formed on the gate dielectric layer in the gate groove, so that low-speed and low-loss etching is realized while the on-resistance is reduced, meanwhile, the etching depth is accurately controlled, the gate leakage is effectively reduced, and the high withstand voltage value and the threshold voltage of the device are improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (7)

1. A GaN device, comprising:
the substrate, the buffer layer, the GaN layer, the AlN layer and the InAlN layer are sequentially stacked, and the source electrode, the drain electrode and the grid electrode are formed on one side, far away from the substrate, of the InAlN layer;
wherein the source electrode and the drain electrode are made of Ti5Al1And a laminated structure of TiN or Ti5Al1And a laminated structure of W.
2. The GaN device of claim 1 wherein the gate is on the InAlN layer.
3. The GaN device of claim 1 wherein the InAlN layer is provided with a gate recess corresponding to the gate;
the GaN device further comprises a grid electrode dielectric layer, and the grid electrode dielectric layer and the grid electrode are sequentially stacked in the grid electrode groove.
4. The GaN device of claim 1, wherein the Ti is5Al1And a laminated structure of TiN orThe above Ti5Al1And the thickness of the laminated structure of W ranges from 60 to 80 nm.
5. A method for fabricating a GaN device, comprising:
providing a substrate;
sequentially forming a buffer layer, a GaN layer, an AlN layer and an InAlN layer on the substrate;
forming a source electrode, a drain electrode and a grid electrode on one side of the InAlN layer far away from the substrate;
wherein the source electrode and the drain electrode are made of Ti5Al1And a laminated structure of TiN or Ti5Al1And a laminated structure of W.
6. The method of claim 5, wherein forming a source, a drain and a gate on the InAlN layer on the side away from the substrate comprises:
forming the source electrode and the drain electrode on the surface of the InAlN layer far away from the substrate;
and forming the gate on the surface of the InAlN layer far away from the substrate.
7. The method of claim 5, wherein the source, the drain and the gate on the InAlN layer side away from the substrate comprise:
forming the source electrode and the drain electrode on the surface of the InAlN layer far away from the substrate;
forming a gate groove on the surface of the InAlN layer far away from the substrate by adopting an ALE etching process;
forming a grid electrode dielectric layer in the grid electrode groove;
forming the grid electrode on the grid electrode dielectric layer in the grid electrode groove;
and forming other metal layers in the metal electrode layer.
CN202011613280.5A 2020-12-30 2020-12-30 GaN device and preparation method thereof Pending CN112820774A (en)

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Application publication date: 20210518