JP2008306026A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress current collapse and peeling and floating of an insulating film. <P>SOLUTION: The method of manufacturing a semiconductor device performs heat treatment for forming ohmic electrodes 17 and 18 on a GaN semiconductor layer 16. The heat treatment is performed while the side walls of the ohmic electrodes 17 and 18 are away from a side wall of an insulating film 24 provided on the GaN semiconductor layer 16. The invention suppresses current collapse and peeling and floating of the insulating film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming an ohmic electrode on a layer having a compound semiconductor layer containing Ga and N and a step of heat treatment.

  A semiconductor device using a compound semiconductor (GaN-based semiconductor) layer containing Ga (gallium) and N (nitrogen), for example, an FET (Field Effect Transistor) such as a HEMT (High Electron Mobility Transistor) is an amplifier for a mobile phone base station. As a high-frequency high-power amplifying element that operates at a high frequency and high power, such as Examples of the GaN-based semiconductor include gallium nitride (GaN) and a semiconductor such as AlGaN or InGaN which is a mixed crystal of GaN and aluminum nitride (AlN) or indium nitride (InN). In FETs using GaN-based semiconductors (hereinafter referred to as GaN-based FETs), technological development for realizing higher performance and higher reliability is being promoted.

A method for manufacturing a GaN-based FET according to a conventional example will be described with reference to FIGS. As shown in FIG. 1A, a GaN-based semiconductor layer 16 including a GaN electron transit layer 12 and an AlGaN electron supply layer 14 is formed on a sapphire substrate 10 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. As shown in FIG. 1B, ohmic electrodes to be the source electrode 17 and the drain electrode 1 are formed on the GaN-based semiconductor layer 16. Referring to FIG. 1C, a heat treatment for alloying the source electrode 17 and the drain electrode 18 with the GaN-based semiconductor layer 16 is performed. Referring to FIG. 1D, a gate electrode is formed on the GaN-based semiconductor layer 16.
Japanese Patent Laid-Open No. 10-335637

  After the manufacturing process shown in FIG. 1D, a surface protective film (not shown) (a protective film 26 shown in FIG. 5C described later, for example, a silicon nitride film) is formed. As described above, in the conventional ohmic electrode forming process of the GaN-based semiconductor device, the heat treatment for ohmicization (see FIG. 1C) is performed in a state where the surface protective film (silicon nitride film or the like) is not covered. Has been done. The reason for this is due to the relationship between the heat treatment temperature and the surface protection film formation temperature and the properties unique to the GaN-based semiconductor. The reason for this will be described below.

  In order to form an ohmic electrode on the GaN-based semiconductor layer, a relatively high temperature heat treatment is required (generally 550 ° C. or higher). On the other hand, the growth temperature of a silicon nitride film generally used as a surface protective film is 320 ° C. or lower. Thus, since the formation temperature of the surface protective film is lower than the heat treatment temperature of the ohmic electrode, conventionally, the surface protective film has been formed after the heat treatment of the ohmic electrode which is a high temperature process. The reason why the high temperature heat treatment process is performed first is that the heat treatment process does not apply thermal stress to the surface protective film.

  According to the GaN-based FET manufacturing method, as shown in FIG. 1C, the surface of the GaN-based semiconductor layer 16 is exposed in the heat treatment of the ohmic electrode. There is concern about the possibility of receiving damage. However, the GaN-based semiconductor layer 16 is a material formed at a high temperature of about 1000 ° C. As a result, the unique property of the GaN-based semiconductor layer 16 is heat resistance. For this reason, until now, the necessity of protecting the surface of the GaN-based semiconductor layer 16 has not been recognized in the heat treatment of the ohmic electrode on the GaN-based semiconductor layer 16.

  On the other hand, the conventional GaN-based FET has a problem called current collapse. The current collapse is a phenomenon in which drain current decreases when the voltage becomes higher than a predetermined voltage when the voltage is increased in the IV (drain current-drain voltage) characteristics of the FET.

  The present invention has been made in view of the above problems, and an object thereof is to suppress the current collapse of a GaN-based FET.

  In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a heat treatment for forming an ohmic electrode on a GaN-based semiconductor layer is performed. This is performed in a state of being separated from the side wall of the insulating film provided on the GaN-based semiconductor layer. According to the present invention, the heat treatment is performed in a state where the surface of the GaN-based semiconductor layer is covered with the insulating film. Therefore, current collapse can be suppressed. Further, this heat treatment is performed in a state where the side wall of the ohmic electrode and the side wall of the insulating film are separated from each other. Therefore, peeling and floating of the insulating film due to thermal stress can be suppressed.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming an insulating film having an opening on a GaN-based semiconductor layer, and a region that covers the opening on the GaN-based semiconductor layer and overlaps the insulating film. In this order, an ohmic electrode is formed, and the ohmic electrode is heat-treated in this order. According to the present invention, the heat treatment is performed in a state where the surface of the GaN-based semiconductor layer is covered with the insulating film. Therefore, current collapse can be suppressed. In addition, peeling and floating of the insulating film due to thermal stress can be suppressed.

  In the above structure, the insulating film may be any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, and an aluminum nitride film. Moreover, the said structure WHEREIN: The process of forming the said ohmic electrode can be made into the structure implemented after the process of forming the said insulating film.

  In the above structure, the semiconductor device may be an FET, and the ohmic electrode may be a source electrode and a drain electrode. According to this configuration, current collapse can be suppressed.

  The said structure WHEREIN: The said ohmic electrode can be set as the structure containing Al. In the above structure, the heat treatment temperature may be higher than the growth temperature of the insulating film. Furthermore, the said structure WHEREIN: The temperature of the said heat processing can be set as the structure which is 550 degreeC or more. Further, in the above structure, the growth temperature of the insulating film may be 320 ° C. or lower.

  According to the present invention, the heat treatment is performed in a state where the surface of the GaN-based semiconductor layer is covered with the insulating film. Therefore, current collapse can be suppressed. Further, the heat treatment is performed in a state where the side wall of the ohmic electrode and the side wall of the insulating film are separated from each other. Therefore, current collapse can be suppressed while suppressing peeling and floating of the insulating film due to thermal stress.

  First, the present inventors examined a method for suppressing current collapse. As a result, it has been found that it is effective to protect the surface of the GaN-based semiconductor layer during heat treatment. Hereinafter, a method for manufacturing a GaN-based FET according to a comparative example used for the study will be described with reference to FIGS.

  In this comparative example, after performing the steps up to FIG. 1B of the conventional example, the source electrode 17, the drain electrode 18 and the GaN-based semiconductor layer 16 are covered with silicon nitride as shown in FIG. 2A. The insulating film 22 is formed using a plasma CVD method. Next, as shown in FIG. 2B, after performing heat treatment, referring to FIG. 2C, the region of the insulating film 22 where the gate electrode is to be formed is removed, and the gate electrode 20 is formed.

  FIG. 3A and FIG. 3B are diagrams showing IV (drain current Ids−drain voltage Vds) characteristics for explaining the current collapse suppression effect in the conventional example and the comparative example. FIG. 3A shows a case where a heat treatment (heat treatment for forming an ohmic electrode) is performed with the GaN-based semiconductor layer 16 exposed as shown in FIG. It is a figure at the time of heat-processing in the state which formed the insulating film 22 in the surface of the GaN-type semiconductor layer 16 like 2 (b). 3A and 3B, the solid line indicates the IV characteristics when the source-drain voltage is 10V, the broken line is 20V, and the dotted line is 50V. The gate voltage is applied in a 1V step from 2 to -1V.

  As apparent from FIG. 3A, when the heat treatment is performed without forming an insulating film on the surface of the GaN-based semiconductor layer 16, the rise of the drain current Ids is steep when the source-drain voltage Vds is 10V. When the source drain voltage Vds is 20V and 50V, the rise of the drain current Ids is low. That is, when the source / drain voltage Vds is applied to a high voltage, a sufficient source / drain current Ids cannot be obtained on the low voltage side (that is, current collapse occurs).

  On the other hand, as apparent from FIG. 3B, when the heat treatment is performed with the insulating film 22 formed on the surface of the GaN-based semiconductor layer 16, the source / drain voltage Vds is applied up to 50V. Even in this case, the drain current Ids on the low voltage side is approximate to the drain current Ids when the source / drain voltage Vds is 10 V or 20 V (that is, current collapse is suppressed).

  As described above, in the GaN-based semiconductor layer 16 that is resistant to high temperatures, it is difficult to think of a large amount of element detachment due to heat treatment such as loss of As that occurs when GaAs is heat-treated. As shown in FIG. 3B, the reason why the current collapse is suppressed by performing the heat treatment while covering the insulating film 22 is not clear.

  However, in the comparative example, as shown in FIG. 2B, due to the difference in thermal expansion coefficients between the source electrode 17 and the drain electrode 18 and the insulating film 22 during the heat treatment, Thermal stress is generated at the discontinuous interface A with the insulating film 22. As a result, there is a problem that the insulating film 22 is peeled off or floated from the GaN-based semiconductor layer 16.

  Such peeling or floating of the insulating film 22 can be eliminated by simply removing the insulating film 22 and forming a protective film again. However, if the insulating film 22 is to be removed, the ohmic electrode or the like is damaged. In particular, in an ohmic electrode containing Al (aluminum) often used in a GaN-based semiconductor device, Al is easily damaged in the process of removing the insulating film 22. The present inventor has made the present invention from the above findings. Examples of the present invention will be described below.

A method for manufacturing a GaN-based FET according to Example 1 will be described with reference to FIGS. After performing the steps up to FIG. 1A of the conventional example, as shown in FIG. 4A, an insulating film 24 made of silicon nitride having a thickness of, for example, 20 nm to 80 nm is formed on the GaN-based semiconductor layer 16 by plasma CVD. Form using the method. The growth temperature of the insulating film 24 is preferably 290 ° C. to 320 ° C., for example, 310 ° C. Deposition gas, using a SiH ₄ or _Si 2 _{H 6} and _NH 3 + _{N 2.} As shown in FIG. 4B, two photoresist layers having different photosensitivity are formed on the insulating film 24 and exposed and developed. Thereby, an overhang-shaped opening 52 is formed in the photoresist layer 50. As shown in FIG. 4C, the insulating film 24 is dry etched using the photoresist layer 50 as a mask. At this time, the insulating film 24 is isotropically etched using a mixed gas of SF ₆ and CHF ₃ as an etching gas. As a result, an opening 54 defined by the lower portion of the opening 52 of the photoresist layer 50 is formed in the insulating film 24.

  Referring to FIG. 4D, the source electrode 17 and the drain electrode 18 are formed on the GaN-based semiconductor layer 16 by using the photoresist layer 50 as a mask, and lifted off. The widths of the source electrode 17 and the drain electrode 18 are defined by the opening width of the upper portion of the photoresist layer 50 in FIG. Therefore, the side wall of the source electrode 17 and the drain electrode 18 and the side wall of the insulating film 24 are separated by a distance d, and a space 56 is formed. The source electrode 17 and the drain electrode 18 are composed of a Ta (tantalum) film having a thickness of 10 nm and an Al film having a thickness of 300 nm from the bottom. The widths of the source electrode 17 and the drain electrode 18 can be appropriately set from several μm to several tens of μm depending on the application. As the source electrode 17 and the drain electrode 18, Ti (titanium) / Al or Ni (nickel) / Al can also be used.

  As shown in FIG. 5A, heat treatment is performed at a temperature of 570 ° C. in a state where the space 56 is formed between the source electrode 17 and the drain electrode 18 and the insulating film 24. The heat treatment temperature is preferably 550 ° C. to 650 ° C., and can be appropriately set depending on the material of the source electrode 17 and the drain electrode 18 and the structure of the GaN-based semiconductor layer 16 in which the source electrode 17 and the drain electrode 18 are in ohmic contact. As shown in FIG. 5B, after removing the region where the gate electrode of the insulating film 22 is to be formed, the gate electrode 20 is formed. The gate electrode 20 is composed of, for example, a Ti film having a thickness of 60 nm and an Au film having a thickness of 300 nm from the bottom. The gate length is 0.4 μm, for example, and can be set as appropriate according to the application. As the gate electrode 20, any one of Ni / Au (gold), Pt (platinum) / Au, and Pd (palladium) / Au can be used.

  With reference to FIG. 5C, a silicon nitride film is formed as a protective film 26 on the source electrode 17, the drain electrode 18, the gate electrode 20, and the insulating film 24. An opening is provided in the protective film 26 and a wiring 28 made of Au connected to the source electrode 17 and the drain electrode 18 is formed. As described above, the GaN-based FET according to Example 1 is completed.

  According to Example 1, since the heat treatment is performed with the insulating film 24 formed as shown in FIG. 4C, the current collapse that is a problem in the conventional example can be suppressed. 4A to FIG. 5A, the film formation temperature of the insulating film 24 in FIG. 4A is 310 ° C., and the ohmic electrode in FIG. The state of the insulating film 24 after the heat treatment of FIG. 5A was observed for 10 sample wafers formed using Al, the heat treatment temperature of FIG. 5A being 570 ° C., but the insulating film 24 was peeled off or floated. Was not observed. This is because heat treatment due to thermal expansion of the ohmic electrode is hardly applied to the insulating film 24 by performing heat treatment in a state where the side walls of the source electrode 17 and the drain electrode 18 and the side wall of the insulating film 24 are spaced apart from each other with the space 56 interposed therebetween. It is thought that it was because of. The distance d (see FIG. 4D) between the source electrode 17 and the drain electrode 18 and the insulating film 24 may be separated, for example, about 0.2 μm to 1.0 μm.

  In Example 1, the example which implements the process of forming the source electrode 17 and the drain electrode 18 after the process of forming the insulating film 24 was demonstrated. After the source electrode 17 and the drain electrode 18 are formed, the insulating film 24 may be formed, and then heat treatment may be performed.

  A method for manufacturing a GaN-based FET according to Example 2 will be described with reference to FIGS. Similar to FIG. 4A of the first embodiment, an insulating film 30 made of silicon nitride is formed on the GaN-based semiconductor layer 16. As shown in FIG. 6A, an opening 58 is formed in the insulating film 30. As shown in FIG. 6B, the source electrode 17 and the drain electrode 18 are formed by vapor deposition and lift-off so as to cover the opening 58 and have a region overlapping the insulating film 30. As shown in FIG. 6C, heat treatment at 570 ° C. is performed. As shown in FIG. 6D, after removing the region where the gate electrode of the insulating film 22 is to be formed, the gate electrode 20 is formed. Then, the same process as FIG. 5C of Example 1 is performed. Thereby, the GaN-based FET according to Example 2 is completed.

  Also in Example 2. Since the heat treatment is performed with the insulating film 30 formed, current collapse is suppressed. The state of the insulating film 30 after the heat treatment of FIG. 6C was observed on 10 sample wafers formed using the manufacturing method of Example 2 from FIG. 6A to FIG. 6C. No peeling or lifting of 30 was observed. In Example 2, the reason why the peeling and floating of the insulating film 30 can be suppressed is that the ohmic electrode sidewall extending on the insulating film 30 is not in contact with the insulating film 30 and the ohmic electrode sidewall It is considered that this is because the insulating film 30 does not receive stress due to thermal expansion of the ohmic electrode.

  In the first and second embodiments, silicon nitride has been described as an example of the insulating films 24 and 30, but any insulating film that suppresses current collapse during heat treatment may be used. For example, a silicon oxide film, an aluminum oxide film, or an aluminum nitride film having a dense film quality and excellent adhesion can be used. Further, as the substrate 10, a SiC substrate, a GaN substrate, or the like can be used.

  Further, when the temperature of the heat treatment of the ohmic electrode is higher than the growth temperature of the insulating film, the insulating film peels off or floats due to the thermal stress of the ohmic electrode. Therefore, when the temperature of the heat treatment of the ohmic electrode is higher than the growth temperature of the insulating film, it is effective to use the present invention. The treatment temperature of the ohmic electrode is preferably 550 ° C. or higher, and the growth temperature of the insulating film is preferably 320 ° C. or lower.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

1 (a) to 1 (d) are cross-sectional views showing a method of manufacturing a GaN-based FET according to a conventional example. FIG. 2A to FIG. 2C are cross-sectional views showing a method for manufacturing a GaN-based FET according to a comparative example. FIGS. 3A and 3C are diagrams showing IV characteristics of a GaN-based FET according to a comparative example. 4A to 4D are cross-sectional views (part 1) illustrating the method for manufacturing the GaN-based FET according to the first embodiment. FIGS. 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the GaN-based FET according to the first embodiment. 6A to 6D are cross-sectional views illustrating a method for manufacturing a GaN-based FET according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 12 GaN electron transit layer 14 AlGaN electron supply layer 16 GaN-based semiconductor layer 17 Source electrode 18 Drain electrode 20 Gate electrode 22, 24, 30 Insulating film 26 Protective film 50 Photoresist 52, 54, 58 Opening

Claims (9)

In a method for manufacturing a semiconductor device that performs a heat treatment for forming an ohmic electrode on a GaN-based semiconductor layer,
The method of manufacturing a semiconductor device, wherein the heat treatment is performed in a state where a side wall of the ohmic electrode is separated from a side wall of an insulating film provided on the GaN-based semiconductor layer. Forming an insulating film having an opening on the GaN-based semiconductor layer;
Forming an ohmic electrode so as to cover the opening on the GaN-based semiconductor layer and have a region overlapping the insulating film;
The step of heat-treating the ohmic electrode, in this order,
A method for manufacturing a semiconductor device, comprising:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is any one of a silicon nitride film, a silicon oxide film, an aluminum oxide film, and an aluminum nitride film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the ohmic electrode is performed after the step of forming the insulating film.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an FET, and the ohmic electrode is a source electrode and a drain electrode. 6.   The method for manufacturing a semiconductor device according to claim 1, wherein the ohmic electrode contains Al.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a temperature of the heat treatment is higher than a growth temperature of the insulating film.   The method of manufacturing a semiconductor device according to claim 7, wherein the temperature of the heat treatment is 550 ° C. or higher.   The method for manufacturing a semiconductor device according to claim 7, wherein a growth temperature of the insulating film is 320 ° C. or less.

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