JP2008306027A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2008306027A
JP2008306027A JP2007152496A JP2007152496A JP2008306027A JP 2008306027 A JP2008306027 A JP 2008306027A JP 2007152496 A JP2007152496 A JP 2007152496A JP 2007152496 A JP2007152496 A JP 2007152496A JP 2008306027 A JP2008306027 A JP 2008306027A
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insulating film
semiconductor layer
manufacturing
electrode
compound semiconductor
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JP2008306027A5 (en
JP5202877B2 (en
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Shinko Nishi
眞弘 西
Hitoshi Ikumatsu
均 生松
Tsutomu Komatani
務 駒谷
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Sumitomo Electric Device Innovations Inc
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Abstract

<P>PROBLEM TO BE SOLVED: To improve coating characteristics of an electrode formed in the opening of an insulating film. <P>SOLUTION: The manufacturing method of a semiconductor device includes a process for forming a first insulating film 20 on a compound semiconductor layer 16, a process for thermally treating the first insulating film 20, a process for forming a second insulating film 22 on the first insulating film 20, a process for forming openings 44 and 46 through which the compound semiconductor layer 16 is exposed by selectively etching the second insulating film 22 and the first insulating film 20 using the same mask 40, and a process for forming an electrode that contacts to the inner wall of the openings 44 and 46. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体装置の製造方法に関し、特に、化合物半導体層上に電極を形成する工程を有する半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a step of forming an electrode on a compound semiconductor layer.

化合物半導体層を用いた半導体装置、例えばＨＥＭＴ（Ｈｉｇｈ Ｅｌｅｃｔｒｏｎ Ｍｏｂｉｌｉｔｙ Ｔｒａｎｓｉｓｔｏｒ）等のＦＥＴ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）は、携帯電話基地局用増幅器などの高周波数かつ高出力で動作する高周波高出力増幅用素子として注目されている。   A semiconductor device using a compound semiconductor layer, for example, an FET (Field Effect Transistor) such as a HEMT (High Electron Mobility Transistor) is used as a high frequency and high output amplifying element that operates at a high frequency and high output, such as an amplifier for a mobile phone base station. Attention has been paid.

特許文献１には、化合物半導体層としてＧａＮ系半導体層上に窒化シリコン膜を形成し、該窒化シリコン膜の所定領域を除去し、ＧａＮ系半導体層上にゲート電極を形成するＦＥＴの製造方法が開示されている。
特開２００５−２８６１３５号公報 Patent Document 1 discloses an FET manufacturing method in which a silicon nitride film is formed as a compound semiconductor layer on a GaN-based semiconductor layer, a predetermined region of the silicon nitride film is removed, and a gate electrode is formed on the GaN-based semiconductor layer. It is disclosed.
JP-A-2005-286135

ここで、図１を参照して、特許文献１に示されるようなＦＥＴの製造方法について検討してみる。図１は、化合物半導体層を用いたＦＥＴの断面図である。サファイア基板１０上に、ＧａＮ電子走行層１２及びＡｌＧａＮ電子供給層１４からなる化合物半導体層１６が形成されている。化合物半導体層１６上に絶縁膜２１が形成されている。絶縁膜２１には開口が形成され。それぞれの開口を覆うように、ゲート電極２８、ソース電極３０及びドレイン電極３２が化合物半導体層１６上に形成されている。ゲート電極２８はＮｉ（ニッケル）等のショットキ層２４とＡｕ（金）等の導電層２６とから構成される。   Here, with reference to FIG. 1, a method for manufacturing an FET as disclosed in Patent Document 1 will be examined. FIG. 1 is a cross-sectional view of an FET using a compound semiconductor layer. A compound semiconductor layer 16 including a GaN electron transit layer 12 and an AlGaN electron supply layer 14 is formed on the sapphire substrate 10. An insulating film 21 is formed on the compound semiconductor layer 16. An opening is formed in the insulating film 21. A gate electrode 28, a source electrode 30 and a drain electrode 32 are formed on the compound semiconductor layer 16 so as to cover the respective openings. The gate electrode 28 includes a Schottky layer 24 such as Ni (nickel) and a conductive layer 26 such as Au (gold).

図１に記載のＦＥＴにおいては、開口端Ａの形状が急峻であるため、開口端Ａにショットキ層２４が成膜されにくく、ショットキ層２４の被覆性が悪くなってしまう。このため、導電層２６がショットキ層２４の被覆性の悪い部分から化合物半導体層１６に拡散する可能性がある。なお、絶縁膜２１の開口をウエットエッチング等の等方性エッチングを用いて行うことにより、開口端でのショットキ層２４の被覆性を向上させることが考えられる。しかし、ゲート電極２８は短ゲート長とすること、ゲート長の制御性を向上させることが求められる。絶縁膜２１を等方性エッチングしたのでは、短いゲート長あるいは制御性のよいゲート電極の形成が困難となる。   In the FET shown in FIG. 1, since the shape of the opening end A is steep, the Schottky layer 24 is hardly formed on the opening end A, and the coverage of the Schottky layer 24 is deteriorated. For this reason, the conductive layer 26 may diffuse into the compound semiconductor layer 16 from a portion of the Schottky layer 24 with poor coverage. Note that it is conceivable to improve the coverage of the Schottky layer 24 at the opening end by performing isotropic etching such as wet etching to open the insulating film 21. However, the gate electrode 28 is required to have a short gate length and to improve the controllability of the gate length. If the insulating film 21 is isotropically etched, it becomes difficult to form a gate electrode having a short gate length or good controllability.

本発明は、上記課題に鑑みなされたものであり、簡単な製造方法により、絶縁膜の開口に形成する電極の被覆性を向上させることを目的とする。   The present invention has been made in view of the above problems, and an object thereof is to improve the coverage of an electrode formed in an opening of an insulating film by a simple manufacturing method.

本発明は、化合物半導体層の上に第１絶縁膜を形成する工程と、前記第１絶縁膜を熱処理する工程と、前記第１絶縁膜上に第２絶縁膜を形成する工程と、前記第２絶縁膜及び前記第１絶縁膜を同一マスクを用い選択的にエッチングし前記化合物半導体層が露出する開口部を形成する工程と、前記開口部の内壁に接する電極を形成する工程と、を有することを特徴とする半導体装置の製造方法である。本発明によれば、第１絶縁膜及び第２絶縁膜の開口端に段差が形成される。これにより、絶縁膜の開口端における電極の被覆性を向上させることができる。   The present invention includes a step of forming a first insulating film on a compound semiconductor layer, a step of heat-treating the first insulating film, a step of forming a second insulating film on the first insulating film, And selectively etching the insulating film and the first insulating film using the same mask to form an opening through which the compound semiconductor layer is exposed, and forming an electrode in contact with the inner wall of the opening. This is a method for manufacturing a semiconductor device. According to the present invention, a step is formed at the opening ends of the first insulating film and the second insulating film. Thereby, the coverage of the electrode at the opening end of the insulating film can be improved.

上記構成において、前記電極はゲート電極である構成とすることができる。この構成によれば、短ゲート長の実現及びゲート長制御性を向上させることができる。   In the above structure, the electrode may be a gate electrode. According to this configuration, realization of a short gate length and gate length controllability can be improved.

上記構成において、前記熱処理は、ソース電極及びドレイン電極をオーミック化するための熱処理である構成とすることができる。この構成によれば、製造工程を簡略化することができる。   In the above configuration, the heat treatment may be a heat treatment for ohmicizing the source electrode and the drain electrode. According to this configuration, the manufacturing process can be simplified.

上記構成において、前記化合物半導体層はＧａＮ系半導体層である構成とすることができる。また、上記構成において、前記第１絶縁膜及び前記第２絶縁膜は窒化シリコン膜である構成とすることができる。   In the above configuration, the compound semiconductor layer may be a GaN-based semiconductor layer. In the above structure, the first insulating film and the second insulating film may be silicon nitride films.

上記構成において、前記エッチングは、ドライエッチングである構成とすることができる。また、上記構成において、前記熱処理の温度は、５５０℃以上である構成とすることができる。   In the above structure, the etching may be dry etching. Moreover, the said structure WHEREIN: The temperature of the said heat processing can be set as the structure which is 550 degreeC or more.

本発明によれば、第１絶縁膜及び第２絶縁膜の開口端に段差が形成される。これにより、絶縁膜の開口端における電極の被覆性を向上させることができる。   According to the present invention, a step is formed at the opening ends of the first insulating film and the second insulating film. Thereby, the coverage of the electrode at the opening end of the insulating film can be improved.

本発明は、絶縁膜を熱処理するとドラエッチングのレートが低下することを利用している。以下、図面を参照に、本発明の実施例について説明する。   The present invention utilizes the fact that the rate of Dora etching decreases when the insulating film is heat-treated. Embodiments of the present invention will be described below with reference to the drawings.

図２（ａ）から図４を用い、実施例１に係るＦＥＴの製造方法を説明する。図２（ａ）のように、サファイア基板１０上にＧａＮ電子走行層１２及びＡｌＧａＮ電子供給層１４をＭＯＣＶＤ（Ｍｅｔａｌ Ｏｒｇａｎｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ）法を用い成長する。これにより、ＧａＮ電子走行層１２及びＡｌＧａＮ電子供給層１４からなる化合物半導体層１６が形成される。   A method for manufacturing the FET according to the first embodiment will be described with reference to FIGS. As shown in FIG. 2A, a GaN electron transit layer 12 and an AlGaN electron supply layer 14 are grown on the sapphire substrate 10 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. Thereby, the compound semiconductor layer 16 composed of the GaN electron transit layer 12 and the AlGaN electron supply layer 14 is formed.

図２（ｂ）のように、化合物半導体層１６上にプラズマＣＶＤ法を用い、窒化シリコン膜からなる第１絶縁膜２０を形成する。ここで、プラズマＣＶＤ法による成膜条件は、温度が３００℃、圧力が０．９ｔｏｒｒ、モノシランガス流量が４ｓｃｃｍ、窒素ガス流量が２００ｓｃｃｍ、アンモニアガス流量が０．５ｓｃｃｍ、ヘリウムガス流量が９００ｓｃｃｍ、ＲＦ（高周波）パワーが５０Ｗとすることができる。第１絶縁膜２０の膜厚は約３０ｎｍである。図２（ｃ）のように、第１絶縁膜２０のオーミック電極を形成すべき領域を除去し、化合物半導体層１６上に形成された第１絶縁膜２０の開口にオーミック電極としてソース電極３０及びドレイン電極３２を蒸着法及びリフトオフ法を用い形成する。ソース電極３０及びドレイン電極３２は下から膜厚が５ｎｍから１５ｎｍのＴａ（タンタル）、膜厚が２００から４００ｎｍのＡｌ（アルミニウム）からなる。図２（ｄ）のように、５５０℃で熱処理を行う。これにより、ソース電極３０及びドレイン電極３２が化合物半導体層１６と合金化され、ソース電極３０及びドレイン電極３２と化合物半導体層１６との間がオーミック接触される。   As shown in FIG. 2B, a first insulating film 20 made of a silicon nitride film is formed on the compound semiconductor layer 16 by using a plasma CVD method. Here, the film formation conditions by the plasma CVD method are as follows: temperature is 300 ° C., pressure is 0.9 torr, monosilane gas flow rate is 4 sccm, nitrogen gas flow rate is 200 sccm, ammonia gas flow rate is 0.5 sccm, helium gas flow rate is 900 sccm, RF ( High frequency) power can be 50W. The film thickness of the first insulating film 20 is about 30 nm. As shown in FIG. 2C, the region of the first insulating film 20 where the ohmic electrode is to be formed is removed, and the source electrode 30 and the ohmic electrode are formed in the opening of the first insulating film 20 formed on the compound semiconductor layer 16. The drain electrode 32 is formed using a vapor deposition method and a lift-off method. The source electrode 30 and the drain electrode 32 are made of Ta (tantalum) having a thickness of 5 nm to 15 nm and Al (aluminum) having a thickness of 200 to 400 nm from the bottom. Heat treatment is performed at 550 ° C. as shown in FIG. Thereby, the source electrode 30 and the drain electrode 32 are alloyed with the compound semiconductor layer 16, and the source electrode 30 and the drain electrode 32 and the compound semiconductor layer 16 are in ohmic contact.

図３（ａ）のように、第１絶縁膜２０、ソース電極３０及びドレイン電極３２上にプラズマＣＶＤ法を用い、窒化シリコン膜からなる第２絶縁膜２２を形成する。第２絶縁膜２２の膜厚は約３０ｎｍである。これにより、第１絶縁膜２０と第２絶縁膜２２とから絶縁膜２３が形成される。図３（ｂ）のように、第２絶縁膜２２上にフォトレジスト４０を塗布し、露光現像を行うことにより、フォトレジスト４０のゲート電極を形成すべき領域に開口部４２を形成する。   As shown in FIG. 3A, a second insulating film 22 made of a silicon nitride film is formed on the first insulating film 20, the source electrode 30, and the drain electrode 32 by using a plasma CVD method. The film thickness of the second insulating film 22 is about 30 nm. Thereby, the insulating film 23 is formed from the first insulating film 20 and the second insulating film 22. As shown in FIG. 3B, a photoresist 40 is applied on the second insulating film 22, and exposure and development are performed to form an opening 42 in a region where the gate electrode of the photoresist 40 is to be formed.

図３（ｃ）のように、第２絶縁膜２２及び第１絶縁膜２０を同一マスク（フォトレジスト4０）を用い選択的にエッチングし化合物半導体層１６が露出する開口部４４を形成する。エッチングは、例えばＳＦ６及びＣＨＦ３を用いたドライエッチングで行う。このとき、第１絶縁膜２０は熱処理によりエッチングレートが低下する。一方、第２絶縁膜２２は熱処理を経ていないため、エッチングレートは低下していない。そこで、第１絶縁膜２０を異方性エッチングし開口部４４を形成した際、第２絶縁膜２２はオーバエッチング状態となり、第２絶縁膜２２にサイドエッチング領域４６が形成される。 As shown in FIG. 3C, the second insulating film 22 and the first insulating film 20 are selectively etched using the same mask (photoresist 40) to form an opening 44 through which the compound semiconductor layer 16 is exposed. Etching is performed by dry etching using, for example, SF 6 and CHF 3 . At this time, the etching rate of the first insulating film 20 is lowered by the heat treatment. On the other hand, since the second insulating film 22 has not undergone heat treatment, the etching rate does not decrease. Therefore, when the first insulating film 20 is anisotropically etched to form the opening 44, the second insulating film 22 is over-etched, and a side etching region 46 is formed in the second insulating film 22.

図３（ｄ）のように、フォトレジスト４０を除去する。第２絶縁膜２２上に感光性の異なる２層のフォトレジスト層を塗布し、露光現像する。これにより、フォトレジスト４８にオーバーハング形状の開口部５０を形成する。   As shown in FIG. 3D, the photoresist 40 is removed. Two photoresist layers having different photosensitivity are applied on the second insulating film 22 and exposed and developed. As a result, an overhang-shaped opening 50 is formed in the photoresist 48.

図４（ａ）のように、絶縁膜２３の開口部４４、４６の内壁及び化合物半導体層１６に接するようにゲート電極２８を蒸着法及びリフトオフ法を用い形成する。ゲート電極２８は下から、膜厚が６０ｎｍのＮｉ（ニッケル）からなるショットキ層２４と、膜厚が３００ｎｍのＡｕ（金）からなる導電層２６と、から構成される。図４（ｂ）のように、ソース電極３０、ドレイン電極３２、ゲート電極２８及び第２絶縁膜２２上に保護膜３４として窒化シリコン膜を形成する。ソース電極３０及びドレイン電極３２にそれぞれ接続されるＡｕからなる配線３６を形成する。以上により、実施例１に係るＦＥＴが完成する。   As shown in FIG. 4A, the gate electrode 28 is formed by vapor deposition and lift-off so as to be in contact with the inner walls of the openings 44 and 46 of the insulating film 23 and the compound semiconductor layer 16. From the bottom, the gate electrode 28 is composed of a Schottky layer 24 made of Ni (nickel) with a thickness of 60 nm and a conductive layer 26 made of Au (gold) with a thickness of 300 nm. As shown in FIG. 4B, a silicon nitride film is formed as a protective film 34 on the source electrode 30, the drain electrode 32, the gate electrode 28 and the second insulating film 22. A wiring 36 made of Au connected to the source electrode 30 and the drain electrode 32 is formed. Thus, the FET according to Example 1 is completed.

実施例１によれば、熱処理工程を経た第１絶縁膜２０と熱処理工程を経ていない第２絶縁膜２２をエッチングすることにより、図３（ｃ）のように、開口部に段差を設けることができる。図５は、実施例１の図２（ａ）から図３（ｃ）と同じ工程を行い、フォトレジスト４０を除去後、ゲート電極２８と同じ金属を形成した後の断面ＳＥＭ画像を模式化した図である。図５のＢように、絶縁膜２３の開口端Ｂは、上部の開口が下部の開口より大きくなるような段差を有している。これにより、絶縁膜２３の開口端Ｂにおけるゲート電極２８中のショットキ層２４の被覆性が向上する。よって、導電層２４が化合物半導体層１６に拡散することを抑制することができる。   According to the first embodiment, by etching the first insulating film 20 that has undergone the heat treatment process and the second insulating film 22 that has not undergone the heat treatment process, a step is provided in the opening as shown in FIG. it can. FIG. 5 schematically illustrates a cross-sectional SEM image after the same process as in FIG. 2A to FIG. 3C of Example 1 was performed, and after the photoresist 40 was removed, the same metal as the gate electrode 28 was formed. FIG. As shown in FIG. 5B, the opening end B of the insulating film 23 has a step such that the upper opening is larger than the lower opening. Thereby, the coverage of the Schottky layer 24 in the gate electrode 28 at the opening end B of the insulating film 23 is improved. Therefore, diffusion of the conductive layer 24 into the compound semiconductor layer 16 can be suppressed.

実施例１においては、電極としてゲート電極２８を例に説明したが、その他の電極でもよい。半導体装置としてＦＥＴを例に説明したが他の半導体装置でもよい。しかしながら、化合物半導体層１６に接する電極はゲート電極２８であることが好ましい。ゲート電極２８は短ゲート長化及びゲート長制御性の向上が求められている。よって、本発明を適用することが有効である。特に、図３（ｃ）のエッチングとしてドライエッチングを用いることにより、第１絶縁膜２０が異方性エッチングされるため、ゲート電極の短ゲート長化及びゲート長制御性の向上を図ることができる。   In the first embodiment, the gate electrode 28 is described as an example of the electrode, but other electrodes may be used. Although the FET has been described as an example of the semiconductor device, other semiconductor devices may be used. However, the electrode in contact with the compound semiconductor layer 16 is preferably the gate electrode 28. The gate electrode 28 is required to have a shorter gate length and improved gate length controllability. Therefore, it is effective to apply the present invention. In particular, by using dry etching as the etching of FIG. 3C, the first insulating film 20 is anisotropically etched, so that the gate length of the gate electrode can be shortened and the gate length controllability can be improved. .

図２（ｄ）のように、熱処理工程は、ソース電極３０及びドレイン電極３２をオーミック化するための熱処理であることが好ましい。これにより、製造工程を簡略化することができる。なお、実施例１のようにＧａＮ系半導体層１６とオーミック電極とのオーミック化のための熱処理は、比較的高温（例えば５５０℃以上）で実施されている。これは、第１絶縁膜２０と第２絶縁膜２２とのエッチングレート差を実用的に得ることのできる温度であり、絶縁膜２３に開口部の段差を設けることによりショットキ層２４の被覆性を向上させるという目的によく合致する。   As shown in FIG. 2D, the heat treatment step is preferably a heat treatment for making the source electrode 30 and the drain electrode 32 ohmic. Thereby, a manufacturing process can be simplified. Note that, as in Example 1, the heat treatment for ohmic formation of the GaN-based semiconductor layer 16 and the ohmic electrode is performed at a relatively high temperature (for example, 550 ° C. or more). This is a temperature at which an etching rate difference between the first insulating film 20 and the second insulating film 22 can be obtained practically. By providing a step in the insulating film 23, the coverage of the Schottky layer 24 can be improved. It fits well with the purpose of improving.

化合物半導体層１６としてＧａＮ系半導体層を例に説明したが、化合物半導体層はＧａＡｓ等の化合物半導体層であってもよい。しかしながら、ＧａＮ系半導体層の場合、図２（ｄ）のオーミック電極の合金化のための熱処理を比較的高温で行う。化合物半導体層１６はＧａＮ系半導体層であることが好ましい。なお、ＧａＮ系半導体としては、例えば、窒化ガリウム（ＧａＮ）並びにＧａＮと窒化アルミニウム（ＡｌＮ）または窒化インジウム（ＩｎＮ）との混晶であるＡｌＧａＮまたはＩｎＧａＮ等の半導体を用いることができる。   Although the GaN-based semiconductor layer has been described as an example of the compound semiconductor layer 16, the compound semiconductor layer may be a compound semiconductor layer such as GaAs. However, in the case of a GaN-based semiconductor layer, the heat treatment for alloying the ohmic electrode in FIG. 2D is performed at a relatively high temperature. The compound semiconductor layer 16 is preferably a GaN-based semiconductor layer. As the GaN-based semiconductor, for example, gallium nitride (GaN) and a semiconductor such as AlGaN or InGaN which is a mixed crystal of GaN and aluminum nitride (AlN) or indium nitride (InN) can be used.

熱処理温度として５５０℃、第１絶縁膜２０及び第２絶縁膜２２として窒化シリコン膜、エッチングのエッチャントとしてＳＦ６及びＣＨＦ３を例に説明した。熱処理によりエッチングレートが遅くなる熱処理温度、材料、エッチャントを適宜選択することができる。 The heat treatment temperature is 550 ° C., the first insulating film 20 and the second insulating film 22 are silicon nitride films, and the etchant is SF 6 and CHF 3 as an example. The heat treatment temperature, material, and etchant at which the etching rate is lowered by the heat treatment can be appropriately selected.

以上、発明の好ましい実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

図１は従来例に係るＦＥＴの製造方法を示す断面図である。FIG. 1 is a cross-sectional view illustrating a conventional method for manufacturing an FET. 図２（ａ）から図２（ｄ）は実施例１に係るＦＥＴの製造方法を示す断面図（その１）である。2A to 2D are cross-sectional views (part 1) illustrating the method of manufacturing the FET according to the first embodiment. 図３（ａ）から図３（ｄ）は実施例１に係るＦＥＴの製造方法を示す断面図（その２）である。FIGS. 3A to 3D are cross-sectional views (part 2) illustrating the method of manufacturing the FET according to the first embodiment. 図４（ａ）及び図４（ｂ）は実施例１に係るＦＥＴの製造方法を示す断面図（その３）である。4A and 4B are cross-sectional views (part 3) illustrating the method of manufacturing the FET according to the first embodiment. 図５は断面ＳＥＭ画像の模式図である。FIG. 5 is a schematic diagram of a cross-sectional SEM image.

符号の説明Explanation of symbols

１０ サファイア基板
１２ ＧａＮ電子走行層
１４ ＡｌＧａＮ電子供給層
１６ 化合物半導体層
２０ 第１絶縁膜
２２ 第２絶縁膜
２８ ゲート電極
３０ ソース電極
３２ ドレイン電極 DESCRIPTION OF SYMBOLS 10 Sapphire substrate 12 GaN electron transit layer 14 AlGaN electron supply layer 16 Compound semiconductor layer 20 1st insulating film 22 2nd insulating film 28 Gate electrode 30 Source electrode 32 Drain electrode

Claims (7)

化合物半導体層の上に第１絶縁膜を形成する工程と、
前記第１絶縁膜を熱処理する工程と、
前記第１絶縁膜上に第２絶縁膜を形成する工程と、
前記第２絶縁膜及び前記第１絶縁膜を同一マスクを用い選択的にエッチングし前記化合物半導体層が露出する開口部を形成する工程と、
前記開口部の内壁に接する電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 Forming a first insulating film on the compound semiconductor layer;
Heat-treating the first insulating film;
Forming a second insulating film on the first insulating film;
Selectively etching the second insulating film and the first insulating film using the same mask to form an opening exposing the compound semiconductor layer;
Forming an electrode in contact with the inner wall of the opening;
A method for manufacturing a semiconductor device, comprising: 前記電極はゲート電極であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the electrode is a gate electrode. 前記熱処理は、ソース電極及びドレイン電極をオーミック化するための熱処理であることを特徴とする請求項２記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 2, wherein the heat treatment is a heat treatment for making the source electrode and the drain electrode ohmic. 前記化合物半導体層はＧａＮ系半導体層であることを特徴とする請求項１記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor layer is a GaN-based semiconductor layer. 前記第１絶縁膜及び前記第２絶縁膜は窒化シリコン膜であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are silicon nitride films. 前記エッチングは、ドライエッチングであることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is dry etching. 前記熱処理の温度は、５５０℃以上であることを特徴とする請求項１記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the heat treatment is 550 ° C. or higher.
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