JP2019165056A - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device capable of forming a flange part of a gate electrode with good reproducibility.SOLUTION: A method for manufacturing a semiconductor device comprises the steps of: forming a first SiN film on a semiconductor laminate located on a substrate; forming a second SiN film on the first SiN film; forming a mast including an opening pattern on the second SiN film; forming a second opening on the second SiN film and forming a first opening having a narrower opening width than the second opening on the first SiN film; forming a first resist provided with a third opening having a wider opening width than the second opening, a second resist provided with a fourth opening having a wider opening width than the third opening, and a third resist provided with a fifth opening having an opening width wider than the third opening and narrower than the fourth opening on the second SiN film; and forming a gate in contact with the semiconductor laminate via the first opening with the first to third resists as a mask.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  An example of the semiconductor device is a high electron mobility transistor (HEMT) described in Patent Document 1 below. In the HEMT, in order to suppress current collapse, a flange portion that extends a part of the gate and does not contact the semiconductor layer may be provided. The following Patent Document 1 discloses an aspect of a HEMT including a two-stage flange portion. In the following Patent Document 1, a SiN layer and an HfO (hafnium oxide) layer are sequentially provided on a barrier layer, a first-stage flange portion is formed on the SiN layer, and a second-stage flange portion is formed on the HfO layer. Is formed. By forming the two-stage flange portion in this way, the number of edges in the gate electrode is increased, so that the effect of dispersing the electric field is increased.

JP 2013-222939 A

  In Patent Document 1, the width of the second flange portion is determined by the shape of the opening formed in the mask by wet etching. For this reason, since the reproducibility of the shape of the opening is low, the length of the second flange portion is also likely to vary. Therefore, in the said patent document 1, there exists a problem from which the characteristic for every HEMT mass-produced differs.

  An object of one aspect of the present invention is to provide a method for manufacturing a semiconductor device in which a flange portion can be formed with good reproducibility.

  A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first SiN film on a semiconductor stacked body located on a substrate by a low pressure CVD method, and a second SiN film on the first SiN film. A second opening is formed in the second SiN film by a step of forming the film by plasma CVD, a step of forming a mask having an opening pattern on the second SiN film, and dry etching through the opening pattern. Forming a first opening having an opening width narrower than the second opening in the first SiN film, and having an opening width wider than the second opening and overlapping the second opening on the second SiN film. A third opening is provided, a first resist located on the second SiN film, and a fourth opening having an opening width wider than the third opening and overlapping the third opening are provided, and are located on the first resist. Wider than the second resist and the third opening A fifth opening having an opening width narrower than the four openings and overlapping the fourth opening, and forming a third resist located on the second resist; and using the first to third resists as a mask, Forming a gate in contact with the semiconductor stacked body through one opening.

  According to one aspect of the present invention, it is possible to provide a method for manufacturing a semiconductor device in which the flange portion can be formed with good reproducibility.

FIG. 1 is a cross-sectional view illustrating an example of a transistor 1 manufactured by the manufacturing method according to the embodiment. 2A and 2B are diagrams illustrating a method for manufacturing the transistor 1 according to the embodiment. 3A and 3B are diagrams illustrating a method for manufacturing the transistor 1 according to the embodiment. 4A and 4B are diagrams illustrating a method for manufacturing the transistor 1 according to the embodiment, and an enlarged method for manufacturing the transistor 1 near the gate electrode 23 is shown. FIGS. 5A and 5B are diagrams illustrating a method for manufacturing the transistor 1 according to the embodiment, and show an enlarged manufacturing method in the vicinity of the gate electrode 23 in the transistor 1. 6A and 6B are diagrams for explaining a method for manufacturing the transistor 1 according to the embodiment, and show an enlarged manufacturing method in the vicinity of the gate electrode 23 in the transistor 1. FIG. 7 is a diagram conceptually showing how the wall surface of the gate opening 11a of the first SiN film 11 and the wall surface of the opening 12a of the second SiN film 12 are retreated by etching. FIG. 8 is a diagram showing a conventional gate electrode forming process.

  A specific example of a method for manufacturing a field effect transistor, which is a kind of semiconductor device according to an embodiment of the present invention, will be described below with reference to the drawings. In addition, this invention is not limited to these illustrations, is shown by the claim, and intends that all the changes within the meaning and range equivalent to the claim are included. In the following description, the same reference numerals are given to the same elements in the description of the drawings, and redundant descriptions are omitted.

  FIG. 1 is a cross-sectional view showing an example of a field effect transistor (hereinafter simply referred to as a transistor) manufactured by the method for manufacturing a semiconductor device according to the present embodiment. As shown in FIG. 1, the transistor 1 includes a substrate 2, a semiconductor stacked body 7, a first SiN film 11 (first SiN film), a second SiN film 12 (second SiN film), and a source electrode. 21, a drain electrode 22, and a gate electrode 23. The semiconductor stacked body 7 includes a buffer layer 3, a channel layer 4, a barrier layer 5, and a cap layer 6 in order from the substrate 2. The transistor 1 is a high electron mobility transistor (HEMT), and a two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) is generated on the channel layer side of the interface between the channel layer 4 and the barrier layer 5. A channel region is formed.

The substrate 2 is a substrate for crystal growth. Examples of the substrate 2 include a SiC substrate, a GaN substrate, and a sapphire (Al ₂ O ₃ ) substrate. In the present embodiment, the substrate 2 is a SiC substrate. The buffer layer 3 is a buffer layer for epitaxially growing the channel layer 4 and the barrier layer 5 on the substrate 2 formed of different materials. The buffer layer 3 is made of a nitride semiconductor, for example, an AlN layer. The thickness of the buffer layer 3 is, for example, not less than 10 nm and not more than 100 nm. The channel layer 4 is a layer epitaxially grown on the substrate 2 (on the buffer layer 3 in this embodiment), and the above-described two-dimensional electron gas is generated to form a channel region through which current flows. The channel layer 4 is made of a nitride semiconductor, for example, a GaN layer. The thickness of the channel layer 4 is, for example, not less than 400 nm and not more than 2000 nm.

  The barrier layer 5 is a layer epitaxially grown on the channel layer 4. The barrier layer 5 is made of a nitride semiconductor having a higher electron affinity than the channel layer 4 and includes, for example, an AlGaN layer, an InAlN layer, or an InAlGaN layer. The barrier layer 5 may exhibit n-type conductivity. In the present embodiment, the barrier layer 5 is an n-type AlGaN layer. The thickness of the barrier layer 5 is, for example, not less than 5 nm and not more than 30 nm. The cap layer 6 is a layer epitaxially grown on the barrier layer 5. The cap layer 6 is made of a nitride semiconductor and is, for example, a GaN layer. The cap layer 6 may also contain impurities. In the present embodiment, the cap layer 6 is composed of an n-type GaN layer. The lower limit value of the thickness of the cap layer 6 is, for example, 1 nm. The upper limit value of the thickness of the cap layer 6 is, for example, 5 nm.

  The first SiN film 11 is an insulating protective film provided on the cap layer 6. The first SiN film 11 is provided to protect the surface of the semiconductor stacked body 7. As will be described later, the first SiN film 11 is formed by a low pressure chemical vapor deposition (LPCVD) method in order to increase the etching resistance as compared with the second SiN film 12. The LPCVD method is a method for forming a dense film by lowering the deposition pressure and increasing the deposition temperature. Further, the first SiN film 11 is a so-called Si-rich film in which the proportion of Si is larger than the stoichiometric composition. The refractive index of the first SiN film 11 is, for example, 2.05 or more.

  The lower limit value of the thickness of the first SiN film 11 is, for example, 10 nm, and the upper limit value is, for example, 50 nm. In the present embodiment, the thickness of the first SiN film 11 is preferably 15 nm or more and 25 nm or less. In the first SiN film 11, a gate opening (first opening) 11a, a source opening 11b, and a drain opening 11c are formed. The gate opening 11a is located between the source opening 11b and the drain opening 11c. The cap layer 6 is exposed in the gate opening 11a. The side wall of the gate opening 11 a is inclined with respect to the stacking direction of the semiconductor stacked body 7 so that the width of the gate opening 11 a gradually increases as the distance from the semiconductor stacked body 7 increases. In the source opening 11b and the drain opening 11c, the cap layer 6 is removed and the barrier layer 5 is exposed.

  The source electrode 21 closes the source opening 11b, is provided on the semiconductor stacked body 7, and is in contact with the barrier layer 5 through the source opening 11b. The drain electrode 22 closes the drain opening 11c, is provided on the semiconductor stacked body 7, and is in contact with the barrier layer 5 through the drain opening 11c. The source electrode 21 and the drain electrode 22 are ohmic electrodes, and are formed, for example, by alloying a laminated structure of a titanium (Ti) layer and an aluminum (Al) layer. The source electrode 21 and the drain electrode 22 may be alloyed after further stacking another Ti layer on the Al layer. Moreover, a tantalum (Ta) layer can be used instead of the Ti layer.

  The second SiN film 12 is provided on the first SiN film 11. As will be described later, in order to make the etching resistance lower than that of the first SiN film 11, the second SiN film 12 is formed by a plasma CVD method. Since the film formation temperature is low in the plasma CVD method, the film quality of the second SiN film 12 is sparser than that of the first SiN film 11. The Si composition of the second SiN film 12 is smaller than that of the first SiN film 11, and the refractive index thereof is smaller than that of the first SiN film 11. The refractive index of the second SiN film 12 is, for example, about 2.0 or less. The lower limit value of the thickness of the second SiN film 12 is, for example, 30 nm, and the upper limit value is, for example, 500 nm. In the present embodiment, the thickness of the second SiN film 12 may be not less than 35 nm and not more than 45 nm.

  Openings 12 a, 12 b and 12 c are formed in the second SiN film 12. The opening (second opening) 12 a is located on the gate opening 11 a of the first SiN film 11 and exposes the gate opening 11 a and the peripheral portion of the first SiN film 11. For this reason, the opening width of the opening 12a is wider than that of the gate opening 11a. The side wall of the opening 12a is inclined with respect to the stacking direction of the semiconductor stacked body 7, similarly to the gate opening 11a. The inclination angle of the side wall of the opening 12a is larger than the inclination angle of the side wall of the gate opening 11a (θ11 <θ12, see FIG. 4B). The opening 12 b is formed in a portion of the second SiN film 12 that covers the source electrode 21 and exposes the upper surface of the source electrode 21. The source electrode 21 is in contact with a source electrode pad (not shown) through the opening 12b. The opening 12 c is formed in a portion of the second SiN film 12 that covers the drain electrode 22 and exposes the upper surface of the drain electrode 22. The drain electrode 22 is in contact with a drain electrode pad (not shown) through the opening 12c.

  The gate electrode 23 is provided in a region on the semiconductor stacked body 7 between the source electrode 21 and the drain electrode 22, and is in contact with the cap layer 6 through the gate opening 11a. Specifically, the gate electrode 23 fills the gate opening 11a and the opening 12a, the cap layer 6 in the gate opening 11a, the surface of the first SiN film 11 exposed in the opening 12a, and the second The surface of the SiN film 12 is in contact with the peripheral portion of the opening 12a. The gate electrode 23 includes a material that is in Schottky contact with the cap layer 6 and has, for example, a stacked structure of a nickel (Ni) layer and a gold (Au) layer. In this case, the Ni layer is in Schottky contact with the cap layer 6. In addition to Ni, Pt (platinum) etc. are mentioned as a material which can perform Schottky contact with the cap layer 6. The thickness of the Ni layer is 200 nm, for example, and the thickness of the Au layer is 700 nm, for example.

  A portion of the gate electrode 23 that is in contact with the first SiN films 11 and 12 has a function of relaxing the electric field in the channel. Hereinafter, in the gate electrode 23, a portion in contact with the first SiN film 11 is referred to as a first portion 23 a, and a portion in contact with the second SiN film 12 is referred to as a second portion 23 b. The width of the first portion 23a is determined by the opening width of the gate opening 11a and the opening width of the opening 12a. As will be described later, the width of the second portion 23b is determined by the opening width of the opening 12a and the opening width of the opening provided in the resist. The gate electrode 23 has a third portion 23c located outside the second portion 23b in the width direction. Since the third portion 23c is separated from the second SiN film 12, the effect of relaxing the electric field in the channel is weak.

  Here, a manufacturing method of the transistor 1 according to the present embodiment will be described with reference to FIGS. 2 (a), (b), FIG. 3 (a), (b), FIG. 4 (a), (b), FIG. 5 (a), (b) and FIG. 6 (a), (b) FIG. 6 is a diagram for explaining a method of manufacturing the transistor 1 according to the present embodiment. 4 (a), 4 (b), 5 (a), 5 (b), and 6 (a), 6 (b) are enlarged views of the manufacturing method in the vicinity of the gate electrode 23 in the transistor 1. FIG. .

  First, as illustrated in FIG. 2A, a semiconductor stacked body 7 including a buffer layer 3, a channel layer 4, a barrier layer 5, and a cap layer 6 is formed on the substrate 2. For example, by using metal organic chemical vapor deposition (MOCVD), an AlN layer that functions as the buffer layer 3, a GaN layer that functions as the channel layer 4, an AlGaN layer that functions as the barrier layer 5, and a cap A GaN layer functioning as the layer 6 is epitaxially grown in order on the SiC substrate.

Subsequently, as shown in FIG. 2B, a first SiN film 11 covering the surface of the semiconductor stacked body 7 (in this embodiment, the surface of the cap layer 6) is formed. In this step, the first SiN film 11 is formed on the cap layer 6 by a low pressure CVD method using dichlorosilane gas and ammonia gas as raw materials. In the present embodiment, the thickness of the first SiN film 11 is 20 nm. In this step, the lower limit value of the deposition temperature of the first SiN film 11 is, for example, 800 ° C., and the upper limit value is, for example, 900 ° C. This is a temperature extremely higher than the film formation temperature in the plasma CVD method. However, this temperature is lower than the growth temperature of the semiconductor stacked body 7. The lower limit value of the deposition pressure of the first SiN film 11 is, for example, 10 Pa, and the upper limit value is, for example, 100 Pa. In the present embodiment, the film forming pressure is 50 Pa to 100 Pa. Further, the ratio (F1 / F2) between the flow rate F1 of dichlorosilane and the flow rate F2 of ammonia gas is set to 0.3 or more, for example. Since the flow rate ratio of this dichlorosilane is larger than the flow rate ratio of dichlorosilane used as stoichiometry, a Si-rich film is formed. The flow rate F1 of dichlorosilane is in the range of 10 sccm to 100 sccm, for example, and the flow rate F2 of ammonia gas is in the range of 200 sccm to 2000 sccm, for example. The unit sccm means cubic centimeter per minute in the standard state, and is converted by ¹ sccm = 1.69 × 10 ⁻⁴ Pa · m ³ · sec ⁻¹ .

  In one embodiment, the flow rate F1 of dichlorosilane is 40 sccm, the flow rate F2 of ammonia gas is 90 sccm, the film formation pressure is 50 Pa, and the film formation temperature is 850 ° C. Under such film formation conditions, the Si-rich first SiN film 11 having a refractive index of approximately 2.1 can be obtained. Note that the Si-rich first SiN film 11 may be formed by further increasing the flow rate F1 of dichlorosilane.

  Subsequently, as shown in FIG. 3A, a part of the first SiN film 11 is selectively etched to form a source opening 11b and a drain opening 11c. For example, the source opening 11b and the drain opening 11c are formed in the first SiN film 11 by selective dry etching through a resist mask. Further, the cap layer 6 in the source opening 11b and the drain opening 11c is removed by dry etching using a chlorine-based gas as a reaction gas. Thereby, the barrier layer 5 is exposed in the source opening 11b and the drain opening 11c. Thereafter, the source electrode 21 is formed in the source opening 11b, and the drain electrode 22 is formed in the drain opening 11c. In this step, the metal for the source electrode 21 and the drain electrode 22 is formed by, for example, physical vapor deposition (PVD method) such as vacuum vapor deposition and lift-off. Thereafter, alloying is performed by heat treatment to make them ohmic electrodes.

  Subsequently, as shown in FIG. 3B, a second SiN film 12 is formed on the first SiN film 11. The second SiN film 12 covers the entire surface of the semiconductor stacked body 7 including the first SiN film 11, the source electrode 21 and the drain electrode 22. In this step, the second SiN film 12 is formed by plasma CVD using silane gas and ammonia gas as raw materials. In the present embodiment, the thickness of the second SiN film 12 is 40 nm. In this step, the lower limit value of the deposition temperature of the second SiN film 12 is, for example, 300 ° C., and the upper limit value is, for example, 350 ° C. The reason why the film formation temperature can be lowered in this way is that plasma assists the decomposition process of silane and ammonia. The lower limit value of the deposition pressure of the second SiN film 12 is, for example, 50 Pa, and the upper limit value is, for example, 200 Pa. The flow rate F3 of silane is in the range of 10 sccm to 50 sccm, and the flow rate F4 of ammonia gas is in the range of 100 sccm to 500 sccm.

  In one embodiment, the flow rate F3 of silane is 20 sccm, the flow rate F4 of ammonia gas is 200 sccm, the deposition pressure is 133 Pa, the deposition temperature is 350 ° C., and the RF power is 200 W. Under such film formation conditions, the second SiN film 12 having a refractive index of approximately 1.8 can be obtained.

Subsequently, as shown in FIG. 4A, a mask 31 having an opening pattern 31 a is formed on the second SiN film 12. The formation position and planar shape of the opening pattern 31a correspond to the formation position and planar shape of the gate opening 11a. The mask 31 is made of, for example, an ultraviolet exposure resist or an electron beam exposure resist. The opening pattern 31a is formed by, for example, ultraviolet exposure or electron beam exposure. Aperture width _{L 0} of the opening pattern 31a in the case of electron beam exposure of 50nm for example, in the case of UV exposure is 400nm for example. The opening width L ₀ may be determined by calculating backward from the desired opening width L ₁ of the gate opening 11a in the first SiN film 11 (see FIG. 4B).

Subsequently, as shown in FIG. 4 (b), by dry etching through the opening pattern 31a, an opening 12a is formed in the second SiN film 12, a gate opening having a narrow opening width _{L 1} than the opening 12a 11a is formed on the first SiN film 11 (etching step). Thereby, the cap layer 6 of the semiconductor stacked body 7 is exposed through the opening 12a and the gate opening 11a. In this step, if the etching conditions for the first SiN film 11 are applied to the second SiN film 12 as they are, significant side etching occurs in the second SiN film 12. The dry etching is, for example, reactive ion etching (RIE). As an etching gas, for example, a fluorine-based gas is used. As the fluorine-based gas, for example, one or more are selected from the group consisting of SF ₆ , CF ₄ , CHF ₃ , C ₃ F ₆ , and C ₂ F ₆ . Since the reactivity with the nitride film changes depending on the type of gas, the shape of the opening 12a is affected. The RIE apparatus may be an inductive coupled type (ICP). As the etching conditions when using a fluorine-based gas, for example, the etching gas is set to SF ₆ , the reaction pressure is set to 1 Pa, and the RF power is set to 100 W. In this step, the reaction pressure affects the mean free path of ions as well as the RF power, and therefore affects the degree of etching anisotropy.

  FIG. 7 is a diagram conceptually showing how the wall surface of the gate opening 11a of the first SiN film 11 and the wall surface of the opening 12a of the second SiN film 12 are retreated by etching. FIG. 7A shows a state where the etching depth and the thickness of the second SiN film 12 are equal to each other (that is, the state where the etching reaches the upper surface of the first SiN film 11). FIGS. 7B and 7C show a state in which the etching for the first SiN films 11 and 12 proceeds gradually. FIG. 7D shows a state where the etching depth and the sum of the thicknesses of the first SiN films 11 and 12 are equal to each other (that is, a state where the etching reaches the upper surface of the cap layer 6 and is completed). A broken-line rectangle D2 shown in the figure represents an aspect ratio A2 (A2 = a2 / b2) between the etching rate a2 in the depth direction and the etching rate b2 in the lateral direction with respect to the second SiN film 12. Yes. The broken-line rectangle D1 indicates the etching rate a1 in the depth direction and the etching in the lateral direction with respect to the first SiN film 11 when it is assumed that the first SiN film 11 in the region overlapping the mask 31 is not etched from above. The aspect ratio A1 (A1 = a1 / b1) with the rate b1 is shown.

  In the present embodiment, the second SiN film 12 is formed by a plasma CVD method, and the first SiN film 11 is formed by a low pressure CVD method. As described above, SiN formed by the plasma CVD method is sparse, and its resistance to dry etching such as RIE is relatively small. Therefore, since the second SiN film 12 is isotropically etched mainly by chemical reaction, the lateral etching rate becomes relatively large and approaches the etching rate in the depth direction. On the other hand, SiN formed by the low pressure CVD method is dense and has relatively high resistance to dry etching such as RIE. Therefore, in the first SiN film 11, the chemical reaction is retreated, the ion sputtering action is relatively large, and the lateral etching rate is sufficiently smaller than the depth etching rate.

  The difference in the etching characteristics of the first SiN films 11 and 12 as described above appears in these etching rates. That is, the etching rate a1 in the depth direction of the first SiN film 11 is slower than the etching rate a2 in the depth direction of the second SiN film 12, and the etching rate in the lateral direction of the first SiN film 11 b1 becomes slower than the lateral etching rate b2 of the second SiN film 12. Furthermore, the aspect ratio A1 of the first SiN film 11 tends to be larger than the aspect ratio A2 of the second SiN film 12. In one example, the etching rate a1 is 4 nm / min, the etching rate a2 is 20 nm / min, and the ratio (a2 / a1) is about 5. The etching rate b1 is 0.5 nm / min, the etching rate b2 is 8 nm / min, and the ratio (b2 / b1) is about 16. In this case, the ratio (A1 / A2) of these aspect ratios A1 and A2 is 16/5. Note that the ratio (A1 / A2) can be made larger than 16/5 by changing the film formation condition and the etching condition.

As shown in FIGS. 7A to 7D, when the etching in the depth direction of the first SiN film 11 proceeds, the etching in the lateral direction of the second SiN film 12 proceeds simultaneously, and the opening 12a The side wall is gradually retracted. Therefore, the upper surface of the first SiN film 11 located around the gate opening 11a is gradually exposed. At this time, if it is assumed that the etching gas is blown only from the opening pattern 31a of the mask 31 along the direction perpendicular to the surface of the semiconductor stacked body 7, the upper surface of the first SiN film 11 is not etched. Therefore, in this case, the side wall of the gate opening 11a becomes Wa in the figure, and the inclination angle of the side wall Wa with respect to the surface of the semiconductor stacked body 7 follows only the aspect ratio A1. However, in many cases, the traveling direction of the etching gas includes a component that is inclined with respect to the direction perpendicular to the surface of the semiconductor stacked body 7. In this step, the sputtering action of the corner portion (edge) of the first SiN film 11 is performed. Etching is simultaneously performed. Wb in the figure is the side wall of the gate opening 11a when it is assumed that the exposed portion of the first SiN film 11 is not covered with the mask 31 and the corner portion of the first SiN film 11 is sufficiently etched. Represents the shape. In this case, the side wall of the gate opening 11a extends linearly from the lower edge of the gate opening 11a to the lower edge of the opening 12a. Actually, the shape of the side wall of the gate opening 11a is an intermediate between Wa and Wb, for example, around Wc. Therefore, the inclination angle θ of the side wall of the gate opening 11a of the first SiN film 11 with respect to the surface of the semiconductor stacked body 7 is less than θ = tan ⁻¹ (4 / 0.5) = tan ⁻¹ (8), θ = tan ⁻¹ (t11 / ((t11 / 4) × 8)) = tan ⁻¹ (0.5) or more. The upper limit is when the side etching of the second SiN film 12 does not occur at all during the etching of the first SiN film 11 (corresponding to Wa), and the lower limit is the side etching of the second SiN film isotropic. Shows the case (equivalent to Wb). Here, t11 indicates the thickness of the first SiN film 11.

  The retraction amount B of the second SiN film 12 with respect to the lower edge of the gate opening 11a of the first SiN film 11 increases as the second SiN film 12 becomes thicker. As an example, when the thickness of the first SiN film 11 is 20 nm and the thickness of the second SiN film 12 is 40 nm, the receding amount B is 70 nm. At this time, the inclination angle θ is 75 °. As another example, when the thickness of the first SiN film 11 is 20 nm and the thickness of the second SiN film 12 is 120 nm, the receding amount B is 100 nm. At this time, the inclination angle θ is 70 °. The retraction amount B corresponds to the distance S1 between the side wall of the opening 12a and the side wall of the gate opening 11a (see FIG. 5B).

  As the second SiN film 12 becomes thicker, the inclination angle θ becomes smaller. However, when the thickness of the second SiN film 12 becomes 300 nm or more, the inclination angle θ becomes saturated at about 60 °. The reason why the inclination angle θ is saturated is that etching proceeds not only at the corner portion of the first SiN film 11 but also at the side wall portion of the gate opening 11a.

  Further, an increase in pressure during etching (for example, an increase from 1 Pa to 5 Pa) acts in the direction of decreasing the inclination angle θ. This is because the mean free path of ions is reduced and the traveling direction of ions is isotropic. However, even when the pressure increases, the inclination angle θ is saturated as the thickness of the second SiN film 12 increases. However, the saturation angle of the tilt angle θ is about 45 °, and the higher the pressure, the smaller the saturation angle.

Next, the manufacturing method will be described. As shown in FIG. 5A, the mask 31 is removed (peeled) from the second SiN film 12. Then, as shown in FIG. 5B, a resist (first resist) 41 located on the second SiN film 12 and a resist (first resist) located on the resist 41 are formed on the second SiN film 12. 2 resist) 42 and a resist (third resist) 43 located on the resist 42 are formed. The resist 41, an opening (third opening) 41a is provided to overlap the opening 12a has a wide opening width _{L 3} than the opening 12a. The resist 42 has a wider opening width _{L 4} than the opening 41a, the opening (fourth opening) 42a is provided to overlap the opening 41a. The resist 43 has an opening width narrower _{L 5} than wider opening 42a than the opening 41a, the opening (5 opening) 43a is provided to overlap the opening 42a. A detailed example of a method for forming such resists 41 to 43 will be described below.

  First, resists 41 to 43 are sequentially formed on the second SiN film 12. The resist 41 is, for example, a copolymer of α-chloroacrylate and α-methylstyrene. In the present embodiment, as the resist 41, a copolymer of α-chloroacrylate and α-methylstyrene (for example, ZEP520A or ZEP520A-7 manufactured by Nippon Zeon Co., Ltd.) is used. Further, in order to adjust the thickness of the resist 41 after coating, the copolymer may be diluted with anisole or the like. The thickness of the resist 41 is, for example, not less than 50 nm and not more than 400 nm. The lower limit of the thickness of the resist 41 is a thickness at which the resist 41 can be applied stably. Next, a resist 42 is formed on the resist 41. In the present embodiment, polymethylglutarimide (PMGI) is used as the resist 42. The thickness of the resist 42 is, for example, not less than 300 nm and not more than 800 nm. The lower limit of the thickness of the resist 42 is the metal thickness of the gate electrode 23. Then, a resist 43 is formed on the resist 42. In this embodiment, a copolymer of α-chloroacrylate and α-methylstyrene (for example, ZEP520A or ZEP520A-7 manufactured by Nippon Zeon Co., Ltd.) is used as the resist 43. In order to adjust the thickness of the resist 43 after coating, the copolymer may be diluted with anisole or the like. The thickness of the resist 43 is, for example, not less than 100 nm and not more than 400 nm. The lower limit of the thickness of the resist 43 is a thickness at which the resist 43 is deformed during vapor deposition and the electrode width of the third portion 23c of the gate electrode 23 does not change.

Next, openings 41a to 43a are formed in the resists 41 to 43, respectively. First, an electron beam is irradiated to portions of the resist 43 that overlap the gate opening 11a and the opening 12a to expose the portions. Next, the exposed portion of the resist 43 is developed and removed. Thus, overlapping the gate opening 11a and the opening 12a, to form an opening 43a having an opening width _{L 5.} Then, the resist 42 is wet-etched through the opening 43 a of the resist 43 to form the opening 42 a in the resist 42. Since the opening width L ₄ of the opening 42 a is wider than the opening width L ₅ of the opening 43 a, a part of the resist 43 functions as a ridge with respect to the resist 42.

Next, an electron beam is irradiated to the part which overlaps with the gate opening 11a and the opening 12a in the resist 41 through opening 43a, 42a, and the said part is exposed. Then, the exposed portion of the resist 44 is developed and removed to form an opening 41a. The opening width _{L 3} of the opening 41a is wider than the opening width _{L 2} of the opening 12a, narrower than the opening width _{L 4} of the opening 42a.

As described above, the openings 41a and 43a of the resists 41 and 43 are formed by electron beam drawing, while the openings 42a of the resist 42 are formed by wet etching. For this reason, the opening widths L ₃ and L ₅ of the openings 41a and 43a can be formed more accurately than the opening width L ₄ of the opening 42a. That is, when the transistor 1 is mass-produced, the opening widths L ₃ and L ₅ have higher reproducibility than the opening width L ₄ .

  Subsequently, as shown in FIG. 6A, the gate electrode 23 in contact with the semiconductor stacked body 7 through the gate opening 11a is formed using the resists 41 to 43 as a mask. Specifically, the resist exposed on the semiconductor stacked body 7 exposed from the gate opening 11a, on the first SiN film 11 exposed from the opening 12a, on the second SiN film 12 exposed from the opening 41a, and from the opening 42a. A metal film is deposited on 41 by PVD. The metal film is, for example, a laminated film of a nickel (Ni) film having a thickness of 200 nm and a gold (Au) film having a thickness of 700 nm. As a result, a first portion 23 a in contact with the first SiN film 11 and a second portion 23 b in contact with the second SiN film 12 in the gate electrode 23 are formed. Of the gate electrode 23, the width of the first portion 23a corresponds to the interval S1, and the width of the second portion 23b corresponds to the interval S2.

  Subsequently, as shown in FIG. 6B, the resists 41 to 43 are removed. At this time, the metal 51 deposited on the resist 43 shown in FIG. 6A is removed simultaneously with the resists 41 to 43. Through the above steps, the transistor 1 shown in FIG. 1 is formed.

  The operations and effects obtained by the semiconductor device manufacturing method according to the present embodiment described above will be described with reference to FIG. FIG. 8 is a diagram showing a conventional gate electrode forming process. As shown in FIG. 8, conventionally, when forming the gate electrode 123, only two layers of resists 42 and 43 are used. That is, in the prior art, the gate electrode 123 is formed without using the resist 41, and the resist 42 is formed immediately above the second SiN film 12. As described above, since the opening 42a of the resist 42 is formed by wet etching, the opening width of the opening 42a is less reproducible than the resist 43 and is likely to vary. For this reason, the width of the second portion 123b of the gate electrode 123 formed on the second SiN film 12 exposed through the opening 42a is also likely to vary. Thereby, the electric field relaxation effect in the channel caused by the second portion 123b varies from transistor to transistor. In addition, since the gate electrode 123 is formed by the PVD method, the metal constituting the gate electrode 123 tends to spread. As a result, the width of the second portion 123 b cannot be controlled by the resist 43, and the protruding portion 123 d that overlaps the portion that becomes the ridge of the resist 43 is formed on the second SiN film 12. In this case, the protrusion 123d also produces an electric field relaxation effect in the channel, and a desired electric field relaxation effect cannot be obtained.

On the other hand, in the manufacturing method of the present embodiment, the opening 41a of the resist 41 formed immediately above the second SiN film 12 is formed by electron beam depiction. For this reason, the shape of the second portion 23b of the gate electrode 23 formed in accordance with the shape of the opening 41a can be accurately determined. In addition, the opening 12a of the gate opening 11a and the second SiN film 12 of the first SiN film 11 because it is formed by dry etching, the opening width of the opening 12a _{L 2} may also be determined accurately. Thus, the shape of the first portion 23a of the gate electrode 23 formed in accordance with the opening width L ₂ may also be determined accurately. Therefore, according to the present embodiment, since the shapes of both the first portion 23a and the second portion 23b can be accurately determined, the electric field relaxation effect in the channel can be expressed with good reproducibility.

  In addition, in the present embodiment, the first SiN film 11 is formed by the low pressure CVD method, and the second SiN film 12 is formed by the plasma CVD method. In this case, since the etching rate of the second SiN film 12 is faster than the etching rate of the first SiN film 11, the gate opening 11a is formed by etching the first SiN film 11, as shown in FIG. While being performed, the side wall of the opening 12a of the second SiN film 12 recedes. Then, the upper surface of the first SiN film 11 around the gate opening 11a is exposed. Since this upper surface is etched from above, the inclination angle θ of the side wall of the gate opening 11a with respect to the surface of the semiconductor stacked body 7 is larger than the angle based on the aspect ratio A1 of the etching rate of the first SiN film 11. Get smaller. Therefore, according to the method of this embodiment, the side wall of the gate opening 11a can be sufficiently inclined. Therefore, it is possible to effectively suppress a decrease in breakdown voltage and deterioration of coplus due to the concentration of the electric field at the gate end.

  Further, in the present embodiment, after the first SiN film 11 and the second SiN film 12 are continuously formed, these are continuously formed (the first SiN film 11 and the second SiN film 12 are brought into the atmosphere. Etching (without exposure) prevents impurities such as ions and carbon atoms from remaining inside the insulating film to which the electric field of the gate voltage is applied. Therefore, it is possible to avoid fluctuations in characteristics of the transistor 1 and deterioration in reliability due to impurities. Further, in the method of the present embodiment, the sidewalls of the opening 12a and the gate opening 11a are formed by dry etching. Therefore, compared to the case where the sidewalls of the opening are formed by wet etching, the sidewall inclination angle is changed for each wafer and within the wafer surface. Therefore, it is possible to reduce variations in operating characteristics of each element.

  As in the present embodiment, the thickness of the first SiN film 11 is in the range of 15 nm to 25 nm, the thickness of the second SiN film 12 is in the range of 35 nm to 45 nm, and the first The refractive index of the SiN film 11 may be larger than the refractive index of the second SiN film 12. By setting the thickness of the first SiN film 11 to 15 nm or more, the function of the first SiN film 11 as an insulating film and a protective film can be sufficiently exhibited. In addition, by setting the thickness of the second SiN film 12 to 35 nm or more, a sufficient amount of retreat of the side wall of the opening 12a can be secured, and the side wall of the gate opening 11a can be effectively inclined. Further, by reducing the thickness of the first SiN film 11 (for example, 25 nm or less) and reducing the thickness of the second SiN film 12 (for example, 45 nm or less), the resist mask can be thinned. Dimension controllability can be improved.

  As in this embodiment, in the LPCVD process for forming the first SiN film 11, the film formation temperature can be in the range of 800 ° C. to 900 ° C., and the film formation pressure can be in the range of 50 Pa to 100 Pa. By forming the first SiN film 11 at such a high temperature and low pressure, the above-described difference in etching rate between the first SiN film 11 and the second SiN film 12 can be effectively generated. .

  As in the present embodiment, in the step of forming the second SiN film 12, a plasma CVD method can be employed within a film forming temperature range of 300 ° C. to 350 ° C. By forming the second SiN film 12 at such a low temperature, the above-described difference in etching rate between the first SiN film 11 and the second SiN film 12 can be effectively generated.

  The manufacturing method of the semiconductor device according to the present invention is not limited to the above-described embodiment, and various other modifications are possible. For example, in the above-described embodiment, an example in which the present invention is applied to a HEMT is described. However, the manufacturing method of the present invention can be applied to various field effect transistors other than the HEMT. In the above embodiment, the second SiN film is formed after the ohmic electrodes (source electrode and drain electrode) are formed. However, the second SiN film is formed first, and then the ohmic electrode is formed. Also good. In that case, it is preferable that the electrode metal does not touch the second SiN film during the heat treatment (alloying) of the ohmic electrode. In that case, the diffusion of the electrode metal into the second SiN film can be avoided. However, since the first SiN film has a dense film quality, the electrode metal may touch the first SiN film.

  DESCRIPTION OF SYMBOLS 1 ... Transistor, 2 ... Board | substrate, 3 ... Buffer layer, 4 ... Channel layer, 5 ... Barrier layer, 6 ... Cap layer, 7 ... Semiconductor laminated body, 11 ... 1st SiN film, 11a ... Gate opening (1st opening) ), 11b ... Source opening, 11c ... Drain opening, 12 ... Second SiN film, 12a, 12b ... Opening, 12c ... Opening (second opening), 21 ... Source electrode, 22 ... Drain electrode, 23, 123 ... Gate Electrode, 23a ... first part, 23b ... second part, 23c ... third part, 31 ... mask, 31a ... opening pattern, 41 ... resist (first resist), 41a ... opening (third opening), 41 ... resist (Second resist), 42a ... opening (fourth opening), 43 ... resist (third resist), 43a ... opening (fifth opening), a1, a2 ... etching rate, B ... retraction amount, b1, b2 ... etching Over door, θ ... angle of inclination.

Claims (7)

Forming a first SiN film on the semiconductor stack located on the substrate by a low pressure CVD method;
Forming a second SiN film on the first SiN film by a plasma CVD method;
Forming a mask having an opening pattern on the second SiN film;
Forming a second opening in the second SiN film by dry etching through the opening pattern, and forming a first opening in the first SiN film having an opening width narrower than the second opening; ,
On the second SiN film,
A first resist having a wider opening width than the second opening and having a third opening overlapping the second opening, the first resist being located on the second SiN film;
A fourth opening having an opening width wider than the third opening and overlapping the third opening is provided, a second resist located on the first resist, and wider than the third opening than the fourth opening Forming a third resist that has a narrow opening width and is provided with a fifth opening that overlaps the fourth opening and is located on the second resist;
Forming a gate in contact with the semiconductor stacked body through the first opening using the first to third resists as a mask;
A method for manufacturing a semiconductor device comprising:   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of simultaneously removing the first to third resists and a metal deposited on the third resist after the step of forming the gate.   3. The method of manufacturing a semiconductor device according to claim 1, wherein an inclination angle of the side wall in the first opening is larger than an inclination angle of the side wall in the second opening. The thickness of the first SiN film is in the range of 15 nm to 25 nm;
The thickness of the second SiN film is in the range of 35 nm to 45 nm,
The method for manufacturing a semiconductor device according to claim 1, wherein a refractive index of the first SiN film is larger than a refractive index of the second SiN film.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a composition of Si in the first SiN film is larger than a composition of Si in the second SiN film.   In the step of forming the first SiN film, the film formation temperature is in the range of 800 ° C to 900 ° C, and the film formation pressure is in the range of 50 Pa to 100 Pa. A method for manufacturing the semiconductor device according to the item.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the second SiN film, a film forming temperature is in a range of 300 ° C. to 350 ° C. 7.

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