JP5163095B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device suitable for use in, for example, a HEMT (High Electron Mobility Transistor) made of a compound semiconductor and a method for manufacturing the same.

In recent years, HEMTs have excellent high-speed characteristics, and thus have been applied to signal processing circuits of optical communication systems and other high-speed digital circuits. In particular, since it has excellent low noise characteristics, application to amplifiers in the microwave and millimeter wave bands is also expected.
On the other hand, in order to operate a digital circuit at high speed, it is required to increase the value of mutual conductance gm, which is an element parameter related to the amplification factor of the element.

One method for improving the mutual conductance gm of the HEMT is to reduce the resistance (source resistance) between the source electrode and the gate electrode.
For example, in Patent Document 1 (see, for example, FIG. 1), in order to reduce the source resistance of the HEMT, a metal film (Al film) is provided on an ohmic contact layer made of InGaAs, and a source electrode and a drain electrode are provided on the metal film. Proposed to provide.

For example, in Patent Document 2 (see, for example, FIGS. 1 and 4), in order to reduce the source resistance of a field effect transistor, a metal film (W film) is formed on the surface of a semiconductor crystal. It describes that a source electrode and a drain electrode having a thick film part and a thin film part are formed by etching the part.
JP-A-9-64340 JP 2006-324514 A

By the way, in the above-mentioned patent document 1 (for example, refer FIG. 2), the following manufacturing methods of HEMT are described.
First, a plurality of semiconductor layers are stacked, a recess portion is formed, and a gate electrode having a T-shaped cross section is formed. Next, Al is vapor-deposited to form a metal film (Al film) on the InGaAs ohmic contact layer. Thereafter, a source electrode and a drain electrode are provided on the metal film.

  However, in such a manufacturing method, the metal film is not formed under the umbrella portion of the gate electrode having a T-shaped cross section. That is, in order to further reduce the source resistance and improve the mutual conductance gm, it is necessary to increase the length of the metal film. However, in the manufacturing method described in Patent Document 1 described above, the T-shaped cross-sectional shape is required. Since the metal film cannot be formed so as to enter under the umbrella portion of the gate electrode, the length of the metal film cannot be made sufficiently long.

On the other hand, in Patent Document 2 described above, since the thin film portion of the metal film (W film) constituting the source electrode and the drain electrode is formed so as to enter below the umbrella portion of the gate electrode, the source resistance and the drain resistance are reduced. Can be reduced.
However, in Patent Document 2 described above, the insulating film is in contact with the gate electrode, leaving a gap in the recess region below the insulating film, and exposing the surface of the semiconductor layer (for example, FIG. 1, see FIG. That is, in the manufacturing method described in Patent Document 2, an opening (gate opening) is formed in the insulating film in order to form the gate electrode, and recess etching is performed through the opening. After the recess is formed, A gate electrode is immediately formed and the gate opening is closed. For this reason, the insulating film (protective film) cannot be formed so as to be in contact with the entire surface of the semiconductor layer exposed in the recess region, and voids remain in the recess region on the lower side of the insulating film. And reliability will be lowered.

  The present invention was devised in view of such problems, and a semiconductor device in which an insulating film can be formed to improve breakdown voltage and reliability while lowering source resistance and improving mutual conductance. And it aims at providing the manufacturing method.

For this reason, this semiconductor device is formed by laminating a plurality of semiconductor layers, a semiconductor multilayer structure having a recess, a metal layer formed on the semiconductor multilayer structure and having an opening at a position corresponding to the recess, and the recess. A gate electrode having an umbrella part and a shaft part that supports the umbrella part; and a drain electrode and a source electrode provided on both sides of the gate electrode, and formed on the metal layer. The opening of the metal layer is equal to or larger than the size of the opening of the recess, and the opening of the insulating film is the opening of the metal layer. The metal layer is formed so as to enter under the umbrella part of the gate electrode, and the insulating film is not in contact with the umbrella part of the gate electrode. Is a requirement.

  In this method of manufacturing a semiconductor device, a semiconductor stacked structure is formed by stacking a plurality of semiconductor layers on a semiconductor substrate, a metal layer is formed on the semiconductor stacked structure, and a recess forming opening is formed in the metal layer. In addition, it is necessary to form a recess through the recess formation opening, widen the recess formation opening, and form a gate electrode having an umbrella portion and a shaft portion supporting the umbrella portion in the recess.

  Therefore, according to the semiconductor device and the manufacturing method thereof, there is an advantage that the breakdown voltage and the reliability can be improved by forming the insulating film while reducing the source resistance and improving the mutual conductance.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to FIGS.

The semiconductor device according to the present embodiment is provided, for example, in an integrated circuit (for example, MMIC), and is an application of the present invention to a HEMT made of a compound semiconductor [here, HEMT (InP-HEMT) formed on an InP substrate]. is there. Hereinafter, InP-HEMT will be specifically described as an example.
As shown in FIG. 1, the present InP-HEMT includes a semiconductor multilayer structure 15 formed by laminating a plurality of semiconductor layers (compound semiconductor layers), a metal layer 9 formed on the semiconductor multilayer structure 15, and a recess 7. The gate electrode 8 is provided, and the drain electrode 10 and the source electrode 11 are formed on the metal layer 9 and provided on both sides of the gate electrode 8.

In this embodiment, the semiconductor multilayer structure 15 is formed on a semi-insulating InP substrate (semiconductor substrate) 1 as shown in FIG. 1, for example, and includes a buffer layer 2 and a channel layer (electron traveling layer, carrier traveling layer). 3, an electron supply layer (carrier supply layer) 4, a stopper layer (etching stop layer) 5, and a cap layer (contact layer) 6 are sequentially laminated.
Here, the buffer layer 2 is formed of undoped InAlAs (i-InAlAs). The thickness is, for example, 300 nm.

  The channel layer 3 is made of undoped InGaAs (i-InGaAs). The channel layer 3 may be formed of, for example, InAlGaAs (i-InAlGaAs), InAs (i-InAs), InP (i-InP), or a multilayer structure of these materials. Here, the thickness of the channel layer 3 is, for example, 15 nm.

The electron supply layer 4 is formed of InAlAs (δ-doped InAlAs; n-InAlAs) that is doped with Si and imparts n-type conductivity. The electron supply layer 4 may be formed of, for example, InAlAsSb (δ-doped InAlAsSb). Here, the thickness of the electron supply layer 4 is, for example, 5 nm to 30 nm.
Instead of the electron supply layer 4, a spacer layer (for example, 3 nm in thickness) formed of undoped InAlAs (i-InAlAs) in order from the bottom, Si is δ-doped to impart n-type conductivity. Δ-doped layer (planar doped layer, electron supply layer; for example, impurity concentration 5 × 10 ¹² cm ⁻² ) formed of InAlAs (n-InAlAs), barrier layer formed of undoped InAlAs (i-InAlAs) ( A barrier layer (for example, a thickness of 6 nm) may be laminated.

The stopper layer 5 is made of undoped InP (i-InP). The thickness is, for example, 5 nm. The stopper layer 5 may be omitted. Further, a stopper layer having a two-layer structure made of different materials may be provided.
The cap layer 6 is made of InGaAs (n-InGaAs) doped with Si to give n-type conductivity. The thickness is, for example, 50 nm, and the carrier concentration is, for example, 1 × 10 ¹⁹ cm ⁻³ . Note that a two-layer structure may be formed by placing InAlAs (n-InAlAs) doped with Si to give n-type conductivity under the n-InGaAs layer.

  In the present embodiment, as shown in FIG. 1, a metal layer (here, WSi) 9 is formed on the entire or almost entire surface of the cap layer (semiconductor cap layer) 6 that is the uppermost semiconductor layer of the semiconductor multilayer structure 15. Is provided. The metal layer 9 is in ohmic contact with the cap layer 6 that is the uppermost semiconductor layer of the semiconductor multilayer structure 15. The metal layer 9 may be made of a material that can easily obtain ohmic characteristics with the lower semiconductor layer (here, the cap layer 6) with which the metal layer 9 is in contact. In the present embodiment, as will be described later, after the recess 7 is formed, the portion of the metal layer 9 protruding above the recess is removed by dry etching. In this case, it is made of a W-based material.

And in this embodiment, as shown in FIG. 1, the cap layer 6 is etched and the recess 7 is formed. That is, the semiconductor multilayer structure 15 has the recess 7.
The surface of the stopper layer 5 is exposed at the bottom surface (surface, recess surface) of the recess 7, and the end face of the gate electrode 8 is in Schottky contact. That is, the gate electrode 8 is provided on the recess 7 and is formed on the stopper layer 5 constituting the bottom surface of the recess 7.

  The gate electrode 8 is configured by sequentially stacking Ti (10 nm) / Pt (30 nm) / Au (500 nm). Here, the gate electrode 8 has an umbrella portion 8A and a shaft portion 8B that supports the umbrella portion 8A, and is configured as a T-type gate electrode having a T-shaped cross-sectional shape. The gate electrode 8 is not limited to this, and any gate electrode 8 may be used as long as it has an umbrella part and a shaft part that supports the umbrella part, and the shape thereof is, for example, a Y-type gate electrode having a Y-shaped cross-sectional shape. You may comprise as.

  Further, metal layers (metals) 9 are formed on the cap layers 6 that are located on both sides of the recesses 7 and constitute the side surfaces of the recesses 7. A drain electrode 10 and a source electrode 11 are formed respectively. That is, the drain electrode 10 and the source electrode 11 having a smaller area than the metal layer 9 are formed on the metal layer 9. These electrodes (ohmic electrodes) 10 and 11 are configured by sequentially stacking Ti (10 nm) / Pt (30 nm) / Au (300 nm). In the present embodiment, the metal layer 9 is the only layer or film formed above the layer constituting the side surface of the recess 7 (here, the cap layer 6).

  The metal layer 9 can be regarded as a part of the cap layer or a part of the ohmic electrode. For example, when the metal layer 9 is viewed as a part of the cap layer, the cap layer has a two-layer structure of a semiconductor cap layer and a metal cap layer. On the other hand, when viewed as a part of the ohmic electrode, the ohmic electrode has a two-layer structure with a different configuration, and has a thick part and a thin part.

By the way, in HEMT, it is required to increase the value of mutual conductance (transfer conductance) gm.
One method for improving the mutual conductance gm of the HEMT is to reduce the resistance (source resistance) between the source electrode and the gate electrode. In order to reduce the source resistance, for example, a method of shortening the recess length or reducing the resistance of the cap layer can be considered.

For example, as a method of shortening the recess length, as shown in FIG. 2A, for example, an opening (gate opening) for forming a gate electrode is formed in the insulating film 20, and the wet is formed through this opening. There is a method of forming a recess having a short recess length by undercut by etching.
However, in this method, although the recess length can be shortened, the gate electrode is formed immediately after the formation of the recess and the gate opening is closed, so that the insulating film (protective film) is in contact with the surface of the recess. ) Cannot be formed, and a void is formed in the recess region below the insulating film 20. The HEMT manufactured by such a method has low withstand voltage and reliability.

In this method, the recess length is determined by the size of the gate electrode (the size of the gate shaft portion; the gate length), and thus the recess length cannot be designed freely.
Furthermore, in this method, since the recess has a symmetric structure with respect to the gate electrode, and the gate electrode is formed at the center of the recess, the gate electrode can be provided at any position in the recess. Can not. For example, since the gate electrode cannot be brought closer to the side surface of the cap layer on which the source electrode is formed, the gate electrode is brought closer to the source electrode and away from the drain electrode to reduce the source resistance and improve the drain withstand voltage. The drain offset structure cannot be realized.

In addition, for example, as shown in FIG. 2B, an opening having a size larger than the size of the gate electrode is formed in the insulating film 20, and wet etching is performed through the opening to form a recess. It can be considered that a gate electrode is formed by defining a gate electrode formation region with a resist film.
However, in this method, an insulating film (protective film) in contact with the surface of the recess can be formed. However, since the recess is formed by an undercut, the recess length is increased according to the size of the opening formed in the insulating film 20. turn into. For this reason, there is a limit to shortening the recess length.

Further, in this method, since the insulating film 20 protrudes above the recess, a region where the date electrode can be disposed within the recess is limited.
On the other hand, as a method of reducing the resistance of the cap layer, the carrier concentration of the cap layer is increased or the length of the region where the ohmic electrode of the cap layer is not formed (that is, the distance between the ohmic electrode and the recess). ) Can be shortened.

However, increasing the carrier concentration of the cap layer is close to the limit. For example, when the ohmic electrode is formed by lift-off, it is difficult to shorten the length of the region of the cap layer where the ohmic electrode is not formed, and this method can be expected only to a certain extent.
Therefore, in the present embodiment, as shown in FIG. 1, the metal layer 9 is provided on the entire surface or almost the entire surface of the cap layer 6 to greatly reduce the resistance (source resistance and drain resistance) of the cap layer.

In particular, in the present embodiment, as shown in FIG. 1, the metal layer 9 is formed to have a sufficiently long length so as to enter under the umbrella portion 8 </ b> A of the gate electrode 8.
Here, the metal layer 9 is formed so as to extend to the vicinity of the recess 7 whose size is sufficiently smaller than the size of the umbrella portion 8A of the gate electrode 8. That is, the metal layer 9 is configured to have an opening 9A that is sufficiently smaller than the size of the umbrella 8A (thickest part) of the gate electrode 8. Thereby, the source resistance is sufficiently lowered so that the value of the mutual conductance gm can be increased.

  Here, Table 1 below shows (A) a structure having only an InGaAs cap layer [see FIG. 3A], (B) an InGaAs cap layer and a metal layer (metal; here, a TiW layer), and a metal layer Has a structure that does not penetrate below the umbrella portion of the gate electrode [see FIG. 3B], (C) an InGaAs cap layer and a metal layer (metal; here, TiW layer), and the metal layer is an umbrella of the gate electrode The results of calculating the sheet resistance, the source resistance, and the mutual conductance gm of each structure (cap layer structure) of the structure [see FIG. Although the metal layer is a TiW layer here, the same result can be obtained when the metal layer is a WSi layer as in this embodiment.

  As shown in Table 1, in the structure including only the InGaAs cap layer [see column (A) in Table 1], the sheet resistance is 70Ω / □. On the other hand, when a metal layer (here, TiW layer) is provided on the InGaAs cap layer [see column (B) in Table 1], the lower side of the umbrella portion of the gate electrode where the metal layer is not provided is a sheet resistance. Is 70Ω / □, but the sheet resistance is 9Ω / □ outside the umbrella portion of the gate electrode provided with the metal layer. Furthermore, when a metal layer (here, TiW layer) is provided on almost the entire surface of the InGaAs cap layer so that the metal layer (here, TiW layer) enters under the umbrella portion of the gate electrode, [in Table 1, (C ) Column]], the sheet resistance is greatly reduced to 9Ω / □.

  Thus, since the sheet resistance is reduced according to the cap layer structure shown in FIGS. 3A, 3B, and 3C, the source resistance is 0.209 Ωmm, 0.178 Ωmm, The mutual conductance gm increases to 1.60 S / mm, 1.68 S / mm, and 1.75 S / mm along with the reduction to 0.154 Ωmm. That is, the reduction of the sheet resistance directly leads to the reduction of the source resistance, and appears as an improvement of the mutual conductance gm.

In the present embodiment, as will be described later, the wet formation is performed via the metal layer 9 in which the recess forming opening 9X [see FIG. 4D] having a size capable of forming a recess having a desired length is formed. Etching is performed to form the recess 7 so that the size (recess length) of the recess 7 can be freely designed.
In particular, wet etching is performed through the metal layer 9 in which the recess forming opening 9X having a size corresponding to the size of the gate electrode 8 (see FIG. 4D) is formed, and the recess 7 is formed by undercut. Thus, the recess 7 having a sufficiently short desired length (desired recess length) can be formed. Thereby, source resistance can be reduced and the value of mutual conductance gm can be made larger. Further, miniaturization can be achieved.

  Furthermore, in this embodiment, as will be described later, after forming a recess 7 having a desired recess length, a portion (eave structure) 9Y protruding above the recess 7 of the metal layer 9 [see FIG. 4F] 1 (that is, by opening the recess forming opening 9X formed in the metal layer 9), the opening 6A (recess; recess) of the cap layer 6 is formed in the metal layer 9 as shown in FIG. An opening 9A larger than the size of the (opening) is formed. Here, since the layer or film formed above the layer constituting the side surface of the recess 7 (here, the cap layer 6) is only the metal layer 9, the opening 9 </ b> A of the metal layer 9 serves as the cap layer 6. This is larger than the size of the opening 6A (opening of the recess 7).

As described above, the distance from the gate electrode 8 to the end face of the metal layer 9 is larger than the distance from the gate electrode 8 to the end face of the cap layer 6, so that the eaves structure of the metal layer 9 does not exist above the recess 7. It has become. For this reason, the area | region which can arrange | position the gate electrode 8 in the recess 7 spreads, and a design freedom increases.
As will be described later, the process of forming the recess 7 and the process of forming the gate electrode 8 are separated, and the recess forming opening 9X is immediately closed by the gate electrode 8 after the formation of the recess 7. Therefore, in order to improve breakdown voltage and reliability, at least the entire portion exposed on the surface of the semiconductor multilayer structure 15 [here, the surface (upper surface) of the stopper layer 5 constituting the bottom surface of the recess 7 and the recess) The insulating film (protective film; for example, SiN film) can be formed so as to be in contact with the surface (side surface and upper surface) of the cap layer 6 constituting the side surface 7.

For example, an insulating film can be formed so as to be in contact with the entire surface of the mesa structure including a portion exposed on the surface of the semiconductor multilayer structure 15. By forming such an insulating film, the withstand voltage and the reliability can be improved. It can be improved. The insulating film may be an insulating film formed of, for example, SiO ₂ or SiON.
In the present embodiment, the opening 9A of the metal layer 9 is set to be larger than the size of the opening 6A of the cap layer 6 (opening of the recess 7), but is not limited thereto. The opening 9A of the metal layer 9 may have the same size as the opening 6A of the cap layer 6 (opening of the recess 7). For example, the distance L between the end surface (metal end) of the metal layer 9 and the end surface (recess end) of the cap layer 6 constituting the side surface of the recess 7 is in the range of 0 nm or more and 200 nm or less (preferably 100 nm or less). The metal layer 9 may be provided on the cap layer 6 so that

Next, a method for manufacturing the present InP-HEMT will be described with reference to FIG.
First, as shown in FIG. 4A, an i-InAlAs buffer layer (for example, a thickness of 300 nm) 2 and an i-InGaAs channel layer (for example, a thickness of 300 nm) are sequentially formed on a semi-insulating InP substrate (semiconductor substrate) 1 from the bottom. (Thickness 15 nm) 3, planar-doped n-InAlAs electron supply layer 4, i-InP stopper layer (for example, thickness 5 nm) 5, n-InGaAs cap layer (for example, impurity concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 50 nm) 6 are stacked by, for example, MOCVD (metal organic chemical vapor deposition) to form a semiconductor stacked structure 15.

  Next, as shown in FIG. 4B, a metal material (here, WSi) is sputtered onto the entire surface of the n-InGaAs cap layer 6 which is the uppermost semiconductor layer constituting the semiconductor multilayer structure 15 to form a metal, for example. A layer (here, WSi layer) 9 is formed. The WSi layer 9 formed on the n-InGaAs cap layer 6 can obtain an ohmic contact without heat treatment (non-alloy).

Next, an element isolation region is defined by, for example, a photolithography technique.
First, as shown in FIG. 4B, after providing the resist film 12, a part of the metal layer 9 is removed by dry etching using, for example, CF4. Next, the n-InGaAs cap layer 6 is removed by wet etching using, for example, a mixed solution of phosphoric acid, hydrogen peroxide solution, and water (phosphoric acid-based etchant). At this time, the etching stops at the upper surface (surface) of the i-InP stopper layer 5. Next, the i-InP stopper layer 5 is selectively removed with, for example, hydrochloric acid. Next, the n-InAlAs electron supply layer 4 to the i-InAlAs buffer layer 2 are etched with, for example, a phosphoric acid-based etchant in the same manner as the n-InGaAs cap layer 6, and then the resist film 12 is removed. In this way, element separation is performed by mesa etching. Thereby, a mesa structure of the element operation region is formed.

Here, the mesa etching up to the i-InAlAs buffer layer 2 is effected. However, if the mesa etching up to the i-InGaAs channel layer 3 is effected, the element isolation effect can be obtained without etching the i-InAlAs buffer layer 2. There is.
Next, a new electrode having openings corresponding to the sizes of the source electrode 11 and the drain electrode 10 is formed on the metal layer 9 in order to define the source electrode region and the drain electrode region (ohmic electrode region) by, for example, photolithography. A resist film (not shown) is provided.

  Then, Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 300 nm) are sequentially deposited on the entire surface (for example, after being deposited by vacuum evaporation), and then the resist film and the resist film are formed on the resist film. By removing the deposited Ti / Pt / Au (that is, by lift-off method), the source electrode 11 and the drain electrode 10 having a three-layer structure of Ti / Pt / Au are formed. Thereby, as shown in FIG. 4C, the source electrode 11 and the drain electrode 10 are formed on the metal layer 9.

Next, the recess region is defined by using, for example, photolithography technology or EB lithography (electron beam exposure method).
First, as shown in FIG. 4D, after providing a new resist film 13 having an opening corresponding to the recess forming opening 9X formed in the metal layer 9, a dry film using, for example, SF6 or CF4 is used. The metal layer 9 is removed by etching, and a recess forming opening 9 </ b> X having a size capable of forming a recess having a desired length is formed in the metal layer 9. Next, as shown in FIG. 4E, the n-InGaAs cap is formed by wet etching using, for example, a mixed solution (etching solution) of phosphoric acid, hydrogen peroxide solution, and water through the recess forming opening 9X. The layer 6 is removed, and a recess 7 having a desired recess length is formed. At this time, since the etching solution hardly etches the i-InP stopper layer 5, the etching stops on the surface of the i-InP stopper layer 5. That is, the n-InGaAs cap layer 6 is selectively etched with respect to the i-InP stopper layer 5. As a result, the surface of the i-InP stopper layer 5 is exposed, and the surface of the i-InP stopper layer 5 forms the bottom surface of the recess 7 (InP recess surface).

In the present embodiment, the size (recess length) of the recess 7 can be freely designed by arbitrarily setting the size of the recess forming opening 9 </ b> X formed in the metal layer 9.
In particular, in the present embodiment, the metal layer 9 in which the recess forming opening 9X having a size capable of forming a recess having a desired length (here, a size corresponding to the size of the gate electrode 8) is formed is used as a mask. By performing wet etching (isotropic etching) and forming the recess 7 by undercut, the recess 7 having a sufficiently short desired length (desired recess length) is formed. Thereby, source resistance can be reduced and the value of mutual conductance gm can be made larger. Further, miniaturization can be achieved.

In this case, as shown in FIG. 4E, the metal layer 9 protrudes above the recess 7 by the undercut by wet etching, so that the eaves structure 9Y is formed.
Next, after removing the resist film 13, patterning is performed again to form an opening larger than the recess 7 (recess opening) having a desired recess length formed as described above, as shown in FIG. A new resist film 14 is provided, and as shown in FIG. 4G, the portion (eave structure) 9Y protruding above the recess 7 of the metal layer 9 is removed by dry etching using, for example, SF6 or CF4. To do.

Thereby, an opening 9A larger than the size of the recess 7 (recess opening; opening 6A of the cap layer 6) is formed in the metal layer 9. That is, the metal layer 9 is formed to extend to the vicinity of the recess 7.
Here, since the size (recess length) of the recess 7 is sufficiently smaller than the size of the umbrella portion 8A of the gate electrode 8 formed as described later, the metal layer 9 is formed of the umbrella portion 8A of the gate electrode 8. It has a length sufficient to enter the lower side.

  Thus, in this embodiment, after forming the recess 7 having a desired recess length, as shown in FIG. 4G, a portion (eave structure) 9Y protruding above the recess 7 of the metal layer 9 is formed. By removing (that is, by opening the recess forming opening 9X formed in the metal layer 9), an opening 9A larger than the size of the recess 7 is formed in the metal layer 9, and a gate electrode 8 described later is formed. In the step of forming the gate electrode 8, the gate electrode 8 can be arranged in the recess 7 without limitation.

The opening formed in the new resist film 14 is required to be larger (wider) than the size of the recess 7 including the undercut portion [length in the left-right direction in FIG. 4F]. . Although the surface of the recess 7 is also exposed to dry etching, the etching may be performed with a sufficiently weak power that does not cause a change in the surface of the recess 8.
Next, as shown in FIG. 4H, after the resist film 14 is removed, for example, using an electron beam exposure method (that is, using, for example, an electron beam resist and an electron beam), a T-shaped cross-sectional shape is formed. In order to define the T-type gate electrode region, a new opening having an opening (gate opening; for example, about 0.1 μm) corresponding to the size of the shaft portion 8B of the T-type gate electrode 8 as shown in FIG. A resist film 16 is provided.

At this time, although not shown, the air gap is formed by selectively etching the i-InGaAs channel layer 3 using, for example, a mixed solution of citric acid, hydrogen peroxide solution, and water through the gate opening.
Then, as shown in FIG. 4 (J), Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 500 nm) are sequentially deposited on the entire surface (for example, vapor deposition is performed by a vacuum evaporation method). After), by removing Ti / Pt / Au deposited on the resist film 16 together with the resist film 16 (that is, by the lift-off method), as shown in FIG. A gate electrode 8 having a three-layer structure of / Au is formed. Thereby, the gate electrode 8 having a T-shaped cross section having the umbrella portion 8A and the shaft portion 8B supporting the umbrella portion 8A is formed on the i-InP stopper layer 5 constituting the bottom surface of the recess 7. Here, the end face of the gate electrode 8 and the i-InP stopper layer 5 are in Schottky contact.

  In order to improve the breakdown voltage and the reliability of the InP-HEMT manufactured as described above, at least the entire portion exposed on the surface of the semiconductor multilayer structure 15 [here, the bottom surface of the recess 7 is formed. When the insulating film (protective film) is formed so as to contact the surface (upper surface) of the stopper layer 5 and the surface (side surface and upper surface) of the cap layer 6 constituting the side surface of the recess 7, 7 may be formed before the gate electrode is formed, or may be formed after the gate electrode is formed.

Therefore, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, it is possible to improve the breakdown voltage and the reliability by forming the insulating film while reducing the source resistance and improving the mutual conductance gm. There are advantages.
[Second Embodiment]
Next, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to FIGS.

  The semiconductor device and the manufacturing method thereof according to this embodiment are different from those of the first embodiment described above on the surface of the metal layer 9 and on the surfaces of the source electrode 11 and the drain electrode 10 as shown in FIG. The difference is that an insulating film (protective film) 17 is formed. In other words, in the first embodiment described above, only the metal layer 9 is formed as a layer or film formed above the layer constituting the side surface of the recess 7 (here, the cap layer 6). The present embodiment is different in that a metal layer 9 and an insulating film 17 are formed as a layer or film formed above a layer (here, the cap layer 6) constituting the side surface of the recess 7. In FIG. 5, the same components as those in the first embodiment (see FIG. 1) are denoted by the same reference numerals.

Specifically, the InP-HEMT further includes an insulating film (here, SiN film) 17 formed on the metal layer 9 and having an opening 17A. The insulating film 17 may be an insulating film formed of, for example, SiO ₂ or SiON.
Here, as in the case of the first embodiment described above, the uppermost semiconductor layer of the semiconductor multilayer structure 15 is the cap layer (semiconductor cap layer) 6. The layer constituting the side surface of the recess 7 is a cap layer 6.

Therefore, the layers or films formed above the layers constituting the side surface of the recess 7 are the metal layer 9 and the insulating film 17.
The metal layer 9 and the insulating film 17 have openings 9A and 17A larger than the size of the opening 6A of the cap layer 6 (opening of the recess 7; recess opening). That is, the metal layer 9 and the insulating film 17 are formed so that the end portions thereof do not protrude above the recess 7, that is, the end surfaces thereof are located outside the side surfaces of the recess 7.

However, the present invention is not limited to this, and the openings 9A and 17A of the metal layer 9 and the insulating film 17 have the same size as the opening 6A of the cap layer 6 (opening of the recess 7; recess opening). Also good.
As will be described later, the step of forming the recess 7 and the step of forming the gate electrode 8 are separated, and the recess forming openings 9X and 17X are immediately closed by the gate electrode 8 after the recess 7 is formed. Therefore, in order to improve the breakdown voltage and reliability, at least the entire portion exposed on the surface of the semiconductor multilayer structure 15 [here, the surface (upper surface) of the stopper layer 5 constituting the bottom surface of the recess 7, and Then, another insulating film (protective film; for example, SiN film) can be formed so as to be in contact with the surface (side surface and upper surface) of the cap layer 6 constituting the side surface of the recess 7. For example, another insulating film can be formed so as to be in contact with the entire surface of the mesa structure including a portion exposed on the surface of the semiconductor multilayer structure 15. By forming such an insulating film, withstand voltage and Reliability can be improved. The insulating film may be an insulating film formed of, for example, SiO ₂ or SiON.

Further, the opening 17A of the insulating film 17 has the same size as the opening 9A of the metal layer 9. However, the present invention is not limited to this, and the opening 17A of the insulating film 17 may be larger than the size of the opening 9A of the metal layer 9.
In this way, when there are a plurality of layers or films (here, the metal layer 9 and the insulating film 17) formed above the layer constituting the side surface of the recess 7 (here, the cap layer 6), the layers adjacent in the vertical direction. Alternatively, between the films, the size of the upper layer or film opening (here, the opening 17A of the insulating film 17) is the lower layer or film opening (here, the opening 9A of the metal layer 9). It is preferable that it is the same as the magnitude | size of this, or larger than it. As a result, the eaves structure of the upper layer or film (here, the insulating film 17) cannot be formed. Therefore, in order to improve the breakdown voltage and the reliability, the portion exposed on the surface of the metal layer 9 (side surface of the metal layer) Another insulating film can be formed so as to be in contact with each other, and by forming such another insulating film [see FIG. 7C], the withstand voltage and the reliability can be improved.

Next, a manufacturing method of the present InP-HEMT will be described with reference to FIG.
First, as in the case of the first embodiment described above, the semiconductor multilayer structure 15, the metal layer 9, the source electrode 11, and the drain electrode 10 are formed [see FIGS. 4A to 4C]. In FIG. 6, the same components as those in the first embodiment (see FIG. 4) are denoted by the same reference numerals.
Next, as shown in FIG. 6A, an insulating film (here, SiN film) 17 is deposited on the entire surface, for example, by a thickness of 10 to 50 nm, for example, by plasma CVD.

Next, as shown in FIGS. 6B and 6C, the recess region is defined by using, for example, photolithography technique or EB lithography (electron beam exposure method).
First, as shown in FIG. 6B, a new resist film 13 having openings corresponding to the recess forming openings 17X and 9X formed in the insulating film 17 and the metal layer (here, WSi layer) 9 is formed. After the formation, the insulating film 17 and the metal layer 9 are removed by dry etching using, for example, SF6 or CF4, so that a recess having a desired length can be formed in the insulating film 17 and the metal layer 9. Opening portions 17X and 9X are formed. Next, as shown in FIG. 6C, n is formed by wet etching using, for example, a mixed solution (etching solution) of phosphoric acid, hydrogen peroxide solution, and water through the recess forming openings 17X and 9X. The InGaAs cap layer 6 is removed, and a recess 7 having a desired recess length is formed. At this time, since the etching solution hardly etches the i-InP stopper layer 5, the etching stops on the surface of the i-InP stopper layer 5. That is, the n-InGaAs cap layer 6 is selectively etched with respect to the i-InP stopper layer 5. The insulating film 17 and the metal layer 9 are not etched either. As a result, the surface of the i-InP stopper layer 5 is exposed, and the surface of the i-InP stopper layer 5 forms the bottom surface of the recess 7 (InP recess surface).

In the present embodiment, the size of the recess 7 (recess length) can be freely designed by arbitrarily setting the sizes of the recess forming openings 17X and 9X formed in the insulating film 17 and the metal layer 9. .
In particular, in this embodiment, the insulating film 17 in which the recess forming openings 17X and 9X having a size capable of forming a recess having a desired length (here, the size corresponding to the size of the gate electrode 8) and the metal are formed. By performing wet etching (isotropic etching) using the layer 9 as a mask and forming the recess 7 by undercutting, the recess 7 having a sufficiently short desired length (desired recess length) is formed. Try to form. Thereby, source resistance can be reduced and the value of mutual conductance gm can be made larger. Further, miniaturization can be achieved.

In this case, as shown in FIG. 6C, since the undercut by wet etching is cut down to the lower side of the insulating film 17 and the metal layer 9, the insulating film 17 and the metal layer 9 protrude above the recesses 7 Structures 17Y and 9Y are formed.
Next, after removing the resist film 13, patterning is performed again, and as shown in FIG. 6D, the opening is larger than the opening (recess opening) of the recess 7 having a desired recess length formed as described above. A new resist film 14 having an opening is provided, and, as shown in FIG. 6E, for example, a portion protruding above the recess 7 of the insulating film 17 and the metal layer 9 by dry etching using SF6 or CF4, for example. (Eave structure) 17Y and 9Y are removed.

Thereby, openings 17A and 9A larger than the size of the recess 7 (recess opening; opening 6A of the cap layer 6) are formed in the insulating film 17 and the metal layer 9. That is, the metal layer 9 is formed to extend to the vicinity of the recess 7.
Here, since the size (recess length) of the recess 7 is sufficiently smaller than the size of the umbrella portion 8A of the gate electrode 8 formed as described later, the metal layer 9 is formed of the umbrella portion 8A of the gate electrode 8. It has a length sufficient to enter the lower side.

  Thus, in this embodiment, after forming the recess 7 having a desired recess length, as shown in FIG. 6E, the insulating film 17 and the portion of the metal layer 9 protruding above the recess 7 (elongation) (Structure) By removing 17Y and 9Y (that is, by opening the recess forming openings 17X and 9X formed in the insulating film 17 and the metal layer 9), the insulating film 17 and the metal layer 9 have the size of the recess 7. The openings 17A and 9A larger than the above are formed so that the gate electrode 8 can be disposed in the recess 7 without limitation in the step of forming the gate electrode 8 described later.

  Next, as shown in FIG. 6F, after removing the resist film 14, for example, using an electron beam exposure method (that is, using, for example, an electron beam resist and an electron beam), a T-shaped cross-sectional shape is formed. In order to define the T-type gate electrode region, a new opening having an opening (gate opening; for example, about 0.1 μm) corresponding to the size of the shaft portion 8B of the T-type gate electrode 8 as shown in FIG. A resist film 16 is provided.

  Then, as shown in FIG. 6 (H), Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 500 nm) were sequentially deposited on the entire surface (for example, deposited by vacuum evaporation). After), by removing Ti / Pt / Au deposited on the resist film 16 together with the resist film 16 (that is, by lift-off method), as shown in FIG. A gate electrode 8 having a three-layer structure of / Au is formed. Thereby, the gate electrode 8 having a T-shaped cross section having the umbrella portion 8A and the shaft portion 8B supporting the umbrella portion 8A is formed on the i-InP stopper layer 5 constituting the bottom surface of the recess 7. Here, the end face of the gate electrode 8 and the i-InP stopper layer 5 are in Schottky contact.

Other configurations and manufacturing methods are the same as those of the above-described first embodiment, and thus description thereof is omitted here.
Therefore, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, as in the case of the first embodiment described above, the insulating film is formed and the withstand voltage or There is an advantage that the reliability can be improved.

By the way, in the above-described embodiment, it is configured not to include another insulating film that is in contact with the entire portion exposed at least on the surface of the semiconductor multilayer structure 15, but in order to improve breakdown voltage and reliability, [Here, the surface (upper surface) of the stopper layer 5 constituting the bottom surface of the recess 7 and the cap layer 6 constituting the side surface of the recess 7 so as to be in contact with the entire portion exposed on the surface of the semiconductor multilayer structure 15. Another insulating film (protective film; for example, SiN) 18 may be formed so as to be in contact with the surface (side surface and upper surface) [see FIG. 7C]. For example, another insulating film 18 may be formed so as to be in contact with the entire surface of the mesa structure including a portion exposed on the surface of the semiconductor stacked structure 15 [see FIG. 7C]. By forming the insulating film 18, the breakdown voltage and reliability can be improved. The other insulating film may be an insulating film formed of, for example, SiO ₂ or SiON.

In the case where such another insulating film 18 is formed, the manufacturing method of the above-described embodiment may be changed as follows.
That is, in the manufacturing method of the above-described embodiment, the portions 17Y and 9Y protruding above the recesses 7 of the insulating film 17 and the metal layer 9 are removed and the resist film is removed [see FIG. 6F]. As shown in FIG. 7A, another insulating film (here, SiN film) 18 is deposited to a thickness of, for example, 10 to 50 nm over the entire surface of the mesa structure, for example, by plasma CVD. As a result, another insulating film 18 is formed and protected so as to be in contact with the entire surface of the mesa structure including the portion exposed to the surface of the semiconductor multilayer structure 15 (particularly the recess surface).

Next, as shown in FIG. 7B, a T-type gate electrode region having a T-shaped cross-sectional shape is defined by using, for example, an electron beam exposure method (that is, using, for example, an electron beam resist and an electron beam). Accordingly, a new resist film 16 having an opening (gate opening; for example, about 0.1 μm) corresponding to the size of the shaft portion 8B of the T-type gate electrode 8 is provided.
Next, as shown in FIG. 7B, a part of the other insulating film 18 is removed by dry etching using, for example, SF 6 or CF 4 to form a gate opening 18 A in the other insulating film 18.

  Then, Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 500 nm) are sequentially deposited on the entire surface (for example, after vapor deposition by a vacuum vapor deposition method), and then the resist film 16 together with the resist film 16. By removing Ti / Pt / Au deposited thereon (that is, by lift-off method), as shown in FIG. 7C, a gate electrode 8 having a three-layer structure of Ti / Pt / Au is formed in the recess 7. Form. As a result, the T-shaped gate electrode 8 having a T-shaped cross section having the umbrella portion 8A and the shaft portion 8B that supports the umbrella portion 8A is formed on the i-InP stopper layer 5 constituting the bottom surface of the recess 7.

Note that the method of forming the other insulating film 18 is not limited to this. For example, the other insulating film 18 may be formed after the gate electrode 8 is formed. In this case, the other insulating film 18 is formed so as to cover the entire surface including the gate electrode 8.
In the semiconductor device manufacturing method according to the above-described embodiment, the insulating film 17 and the other insulating film 18 are formed so as to cover the source electrode 11 and the drain electrode 10 after forming the source electrode 11 and the drain electrode 10. However, the present invention is not limited to this. For example, the insulating film 17 and the other insulating film 18 may be formed before the source electrode 11 and the drain electrode 10 are formed as in the fourth embodiment described later. good. In this case, the insulating film 17 and the other insulating film 18 are not formed on the source electrode 11 and the drain electrode 10.
[Third Embodiment]
Next, a semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to FIGS.

The semiconductor device and the manufacturing method thereof according to the present embodiment are different from those of the first embodiment described above in that the thickness of the metal layer 9 is changed as shown in FIG.
In the present embodiment, as shown in FIG. 8, the metal layer 9 is thinner on the gate electrode 8 side than on the drain electrode 10 or source electrode 11 side. That is, the end of the metal layer 9 on the gate electrode 8 side gradually becomes thinner from the drain electrode 10 or the source electrode 11 side toward the gate electrode 8 side. In other words, the film thickness at the end of the metal layer 9 on the recess 7 side increases as the distance from the recess 7 increases. In FIG. 8, the same components as those in the first embodiment (see FIG. 1) are denoted by the same reference numerals.

Specifically, in the first embodiment described above, the end of the metal layer 9 on the gate electrode 8 side has a vertical shape, whereas in the present embodiment, as shown in FIG. The end portion of the metal layer 9 on the gate electrode 8 side is gradually thinned so that the distance between the umbrella portion 8A and the end portion of the metal layer 9 is kept constant.
Note that the present invention is not limited to such a configuration. For example, the metal layer 9 may be thinned stepwise from the drain electrode 10 side or the source electrode 11 side toward the gate electrode 8 side. That is, the metal layer 9 has a thickness on the gate electrode 8 side and a thickness on the drain electrode 10 or source electrode 11 side so that the thickness on the gate electrode 8 side is thinner than the thickness on the drain electrode 10 or source electrode 11 side. The thickness may change stepwise.

  Thus, in this embodiment, the umbrella portion 8A of the gate electrode 8 and the end portion of the metal layer 9 are separated from each other by a certain distance. This is because the parasitic capacitance between the metal layer 9 connected to the source electrode 11 or the drain electrode 10 and the gate electrode 8 affects the high-speed characteristics and the high-frequency characteristics, so that it is connected to the source electrode 11 or the drain electrode 10. This is because it is desirable that the distance between the metal layer 9 and the gate electrode 8 be a predetermined distance or more.

  In particular, as shown in FIG. 9, when the thickness of the metal layer 9 is increased in order to reduce the source resistance and the drain resistance, as described above, the end on the gate electrode 8 side is gradually reduced so that the gate electrode By separating the 8 umbrella portion 8A and the end portion of the metal layer 9 by a certain distance, the source resistance and drain resistance are reduced while ensuring high speed characteristics and high frequency characteristics without generating extra parasitic capacitance. be able to.

Next, a method for manufacturing the present InP-HEMT will be described with reference to FIG.
First, as in the case of the first embodiment described above, the semiconductor multilayer structure 15, the metal layer (here, WSi layer) 9, the source electrode 11 and the drain electrode 10 are formed, and a recess formation opening 9 </ b> X is formed in the metal layer 9. And the recess 7 are formed [see FIGS. 4A to 4E]. In FIG. 10, the same components as those in the first embodiment (see FIG. 4) are denoted by the same reference numerals.

Next, after removing the resist film 13, patterning is performed again, and as shown in FIG. 10A, the opening is larger than the opening (recess opening) of the recess 7 having a desired recess length formed as described above. A new resist film 14 having an opening is provided.
Next, as shown in FIG. 10A, the pattern edge of the resist film 14 is rounded by baking the resist film 14 at 180 ° C. to 200 ° C., for example. As a result, the thickness of the end portion of the resist film 14 on the recess 7 side is gradually reduced.

Thereafter, as in the case of the first embodiment described above, as shown in FIG. 10 (B), the portion (elongation) protruding above the recess 7 of the metal layer 9 by dry etching using, for example, SF6 or CF4. Structure) 9Y is removed. Thereby, an opening 9A larger than the size of the recess 7 (recess opening; opening 6A of the cap layer 6) is formed in the metal layer 9.
That is, the metal layer 9 is formed to extend to the vicinity of the recess 7. Here, since the size (recess length) of the recess 7 is sufficiently smaller than the size of the umbrella portion 8A of the gate electrode 8 formed as described later, the metal layer 9 is formed of the umbrella portion 8A of the gate electrode 8. It has a length sufficient to enter the lower side.

  Thus, in this embodiment, after forming the recess 7 having a desired recess length, as shown in FIG. 10B, a portion (eave structure) 9Y protruding above the recess 7 of the metal layer 9 is formed. By removing (that is, by opening the recess forming opening 9X formed in the metal layer 9), an opening 9A larger than the size of the recess 7 is formed in the metal layer 9, and a gate electrode 8 described later is formed. In the step of forming the gate electrode 8, the gate electrode 8 can be arranged in the recess 7 without limitation.

  In particular, in this embodiment, since the thickness of the end portion on the recess 7 side of the resist film 14 is gradually reduced, the metal layer 9 gradually increases from the pattern edge where the thickness of the resist film 14 is the smallest. Then, the rounded shape of the end portion of the resist film 14 is transferred to the metal layer 9. As a result, as shown in FIG. 10B, the thickness of the end portion of the metal layer 9 on the recess 7 side (gate electrode 8 side) is gradually reduced.

Thus, in this embodiment, in order to widen the recess forming opening 9X formed in the metal layer 9, the thickness on the gate electrode 8 side of the metal layer 9 is the thickness on the drain electrode 10 or source electrode 11 side. Etching to be thinner than this. That is, in this embodiment, the etching is performed so that the thickness of the end portion of the metal layer 9 on the recess 7 side (gate electrode 8 side) gradually decreases.
Next, as shown in FIG. 10C, after removing the resist film 14, for example, using an electron beam exposure method (that is, using, for example, an electron beam resist and an electron beam), a T-shaped cross-sectional shape is formed. In order to define the T-type gate electrode region, a new resist film having an opening (gate opening; for example, about 0.1 μm) corresponding to the size of the shaft portion 8B of the T-type gate electrode 8 is provided.

  Then, Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 500 nm) are sequentially deposited on the entire surface (for example, after vapor deposition by a vacuum deposition method), and then on the resist film together with the resist film. By removing the deposited Ti / Pt / Au (that is, by a lift-off method), a gate electrode 8 having a three-layer structure of Ti / Pt / Au is formed in the recess 7 as shown in FIG. To do. Thereby, the gate electrode 8 having a T-shaped cross section having the umbrella portion 8A and the shaft portion 8B supporting the umbrella portion 8A is formed on the i-InP stopper layer 5 constituting the bottom surface of the recess 7.

Other configurations and manufacturing methods are the same as those of the above-described first embodiment, and thus description thereof is omitted here.
Therefore, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, as in the first embodiment described above, the insulating film is formed and the breakdown voltage and the reliability are improved while reducing the source resistance and improving the mutual conductance gm. There is an advantage that it becomes possible to improve.

In particular, since the end of the metal layer 9 on the gate electrode 8 side is gradually thinned, it is possible to prevent extra parasitic capacitance from being generated between the gate and the source or between the gate and the drain. Characteristics can be improved.
In addition, although the above-mentioned embodiment demonstrated as a modification of the above-mentioned 1st Embodiment, it can also be comprised as a modification of the above-mentioned 2nd Embodiment (including the modification). That is, as described above, the insulating film 17 or another insulating film 18 may be formed on the metal layer 9 whose end on the gate electrode 8 side is gradually thinned.
[Fourth Embodiment]
Next, a semiconductor device and a manufacturing method thereof according to a fourth embodiment of the present invention will be described with reference to FIG.

The semiconductor device and the manufacturing method thereof according to this embodiment are configuration examples when the above-described embodiments are applied to the InP-HEMT, whereas the configuration example is applied to the GaN-HEMT. Is different.
That is, the semiconductor device according to the present embodiment is provided in, for example, an integrated circuit (for example, MMIC), and the present invention is applied to a HEMT made of a compound semiconductor [here, a HEMT using a GaN-based material (GaN-HEMT)]. It is. This will be specifically described below.

  As shown in FIG. 11B, the present GaN-HEMT is formed on a semiconductor stacked structure 30 formed by stacking a plurality of semiconductor layers (compound semiconductor layers; including GaN here), and the semiconductor stacked structure 30. A metal electrode 31 provided on the recess 32, and a drain electrode 34 and a source electrode 35 formed on the metal layer 31 and provided on both sides of the gate electrode 33.

In this embodiment, the semiconductor multilayer structure 30 is formed on a SiC substrate (semiconductor substrate) 36 as shown in FIG. 11, for example, and includes a channel layer (electron transit layer, carrier transit layer) 37, an electron supply layer (carrier supply). Layer) 38 is laminated in order.
Here, the channel layer 37 is made of undoped GaN (i-GaN). Here, the thickness of the channel layer 37 is, for example, 3 μm.

The electron supply layer 38 is formed of AlGaN [n-AlGaN; Si doping concentration (impurity concentration) 5 × 10 ¹⁸ cm ⁻³ ] doped with Si to give n-type conductivity. Here, the thickness of the electron supply layer 38 is, for example, 30 nm.
An i-AlGaN spacer layer (for example, 5 nm thick) may be provided between the i-GaN channel layer 37 and the n-AlGaN electron supply layer 38.

  In the present embodiment, as shown in FIG. 11B, a metal layer (metal; here, a TiAl layer) 31 is provided on the electron supply layer 38 which is the uppermost semiconductor layer of the semiconductor multilayer structure 30. ing. The metal layer 31 is in ohmic contact with the electron supply layer 38 that is the uppermost semiconductor layer of the semiconductor multilayer structure 30. The metal layer 31 may be made of a material that can easily obtain ohmic characteristics with the lower semiconductor layer (here, the electron supply layer 38) with which the metal layer 31 is in contact. In this embodiment, as will be described later, since the recess 32 is formed by dry etching, the metal layer 31 is made of a material that can be dry etched (here, a Ti-based material).

Furthermore, in this embodiment, as shown in FIG. 11B, an insulating film (protective film; here, SiN film) 39 formed on the metal layer 31 and having an opening 39A is further provided. The insulating film 39 may be an insulating film formed of, for example, SiO ₂ or SiON.
In this embodiment, the recess 32 is formed by etching the insulating film 38 and the metal layer 31 as shown in FIG. That is, the recess 32 is formed in the metal layer 31.

The surface of the electron supply layer 38 is exposed on the bottom surface (surface, recess surface) of the recess 32, and the end face of the gate electrode 33 is in Schottky contact. That is, the gate electrode 33 is provided on the recess 32 and is formed on the electron supply layer 38 constituting the bottom surface of the recess 32.
The gate electrode 33 is configured by sequentially stacking Ni / Au. Here, the gate electrode 33 has an umbrella portion 33A and a shaft portion 33B that supports the umbrella portion 33A, and is configured as a T-type gate electrode having a T-shaped cross-sectional shape. The gate electrode 33 is not limited to this, and any gate electrode 33 may be used as long as it has an umbrella part and a shaft part that supports the umbrella part. The shape of the gate electrode 33 is, for example, a Y-type gate electrode having a Y-shaped cross-sectional shape. You may comprise as.

  Further, a source electrode 35 and a drain electrode 34 are formed on a part of the metal layer 31 that is located on both sides of the recess 32 and that forms the side surface of the recess 32. That is, the source electrode 35 and the drain electrode 34 having a smaller area than the metal layer 31 are formed on the metal layer 31. These electrodes (ohmic electrodes) 34 and 35 are configured by sequentially stacking Ni / Au. In the present embodiment, the insulating film 39 is the only layer or film formed above the layer (here, the metal layer 31) constituting the side surface of the recess 32.

The metal layer 31 can be regarded as a cap layer or a part of the ohmic electrode. For example, when viewed as a part of the ohmic electrode, the ohmic electrode has a two-layer structure with a different configuration, and has a thick part and a thin part.
By the way, in the conventional GaN-HEMT, for example, as shown in FIG. 11A, an i-GaN channel layer 51 and an n-AlGaN electron supply layer 52 are formed in this order on a SiC substrate 50 to supply n-AlGaN electrons. A gate electrode 53, a source electrode 54 and a drain electrode 55 are provided on the layer 52, and the surface of the n-AlGaN electron supply layer 52 is covered with an insulating film 56.

In contrast, in the present embodiment, as shown in FIG. 11B, a metal layer (here, TiAl layer) 31 is provided on the n-AlGaN electron supply layer 38 so as to lower the source resistance and drain resistance. ing.
In particular, in the present embodiment, as shown in FIG. 11B, the length of the metal layer 31 is formed to be sufficiently long so as to enter under the umbrella portion 33A of the gate electrode 33. Thereby, the source resistance is sufficiently lowered so that the value of the mutual conductance gm can be increased.

  Moreover, in this embodiment, since the recess 32 is formed by dry-etching the metal layer 31 as described later, the size (recess length) of the recess 32 can be freely designed. In particular, the recess 32 having a sufficiently short desired length (desired recess length) can be formed, the source resistance can be lowered, and the value of the mutual conductance gm can be increased. Further, miniaturization can be achieved.

  Further, in the present embodiment, as shown in FIG. 11B, an opening 39A having the same size as the opening 31A (recess 32; recess opening) of the metal layer 31 is formed in the insulating film 39. Yes. Here, since the insulating film 39 is the only layer or film formed above the layer constituting the side surface of the recess 32 (here, the metal layer 31), the opening 39 A of the insulating film 39 serves as the metal layer 31. This is the same size as the opening 31A (opening of the recess 32).

As described above, the distance from the gate electrode 33 to the end face of the insulating film 39 is larger than the distance from the gate electrode 33 to the end face of the metal layer 31, so that the eaves structure of the insulating film 39 does not exist above the recess 32. It has become. For this reason, the area | region which can arrange | position the gate electrode 33 in the recess 32 is wide, and a design freedom is high.
Further, as shown in FIG. 11C, in order to improve breakdown voltage and reliability, at least the entire portion exposed on the surface of the semiconductor multilayer structure 30 [here, the electron supply layer constituting the bottom surface of the recess 32 The other insulating film (protective film; for example, SiN) 40 can be formed so as to be in contact with the surface (upper surface 38).

For example, as shown in FIG. 11C, another insulating film can be formed so as to be in contact with the entire surface of the mesa structure including the portion exposed on the surface of the semiconductor stacked structure 30. By forming the other insulating film 40, the breakdown voltage and the reliability can be improved. The other insulating film 40 may be an insulating film formed of, for example, SiO ₂ or SiON.

  In the present embodiment, the size of the opening 39A of the insulating film 39 is the same as the size of the opening 31A of the metal layer 31 (the opening of the recess 32), but the present invention is not limited to this. The opening 39A of the insulating film 39 is formed with the opening 31A of the metal layer 31 (the opening of the recess 32) so that at least another insulating film 40 in contact with the entire portion exposed on the surface of the semiconductor multilayer structure 30 can be formed. It is sufficient that it is larger than the size of the part).

Next, a method for manufacturing the GaN-HEMT will be described with reference to FIG. Here, a description will be given including a step of forming another insulating film 40 so as to be in contact with at least the entire portion exposed on the surface of the semiconductor multilayer structure 30.
First, an i-GaN channel layer (electron transit layer; for example, 3 μm in thickness) 37, n-AlGaN is formed on an SiC substrate (semiconductor substrate) 36 by, for example, MOVPE (organometallic vapor phase epitaxy). An electron supply layer (for example, a thickness of 30 nm; Si doping concentration of 5 × 10 ¹⁸ cm ⁻³ ) 38 is sequentially stacked to form a semiconductor stacked structure 30 [see FIG. 11C].

Next, a metal material (here, TiAl) is vapor-deposited, for example, on the entire surface of the n-AlGaN electron supply layer 38 which is the uppermost semiconductor layer constituting the semiconductor multilayer structure 30 to form a metal layer (here, TiAl layer) 31. [See FIG. 11C].
Next, an insulating material (here, SiN) is deposited on the entire surface of the metal layer 31 by, for example, CVD (chemical vapor deposition) to form an insulating film (here, SiN film) 39 [ See FIG. 11C]. That is, after forming the metal layer 31 and before forming the recess 32 as described later, the insulating film 39 is formed on the metal layer 31.

Next, after element separation is performed by, for example, a photolithography technique, the recess region is defined by using, for example, a photolithography technique or EB (electron beam) lithography (electron beam exposure method).
That is, after providing a resist film having an opening corresponding to the recess 32 having a desired size on the insulating film 39, for example, dry etching (anisotropic etching) using F-based and Cl-based gases is performed. Then, the insulating film 39 and the metal layer 31 are removed, and the recess 32 is formed. As a result, the surface of the n-AlGaN electron supply layer 38 is exposed, and the bottom surface (InP recess surface) of the recess 32 is formed by the surface of the n-AlGaN electron supply layer 38 (see FIG. 11C). ].

  Next, after removing the resist film, an insulating material (here, SiN) is deposited on the entire surface by, eg, plasma CVD to form another insulating film (here, SiN film) 40 [FIG. reference]. Thereby, the entire surface including the portion exposed on the surface of the semiconductor multilayer structure 30 (the surface of the n-AlGaN electron supply layer 38; the recess surface) [here, the surface of the electron supply layer 38 constituting the bottom surface of the recess 32 ( Another insulating film 40 is formed so as to be in contact with the upper surface), the surface (side surface) of the metal layer 31 constituting the side surface of the recess 32, and the surface (side surface and upper surface) of the insulating film 39].

Next, heat treatment is performed, for example, between 400 ° C. and 1000 ° C. (for example, 600 ° C.) in a nitrogen atmosphere, and the ohmic characteristics of the metal layer (here, TiAl layer) 31 are obtained.
Next, in order to define the source electrode region and the drain electrode region (ohmic electrode region) by, for example, photolithography technology, the source electrode formation planned region and the drain electrode formation planned region are respectively formed on the insulating film 39 and the other insulating film 40. A new resist film having an opening is provided.

  Then, after Ti, Pt, and Au are sequentially deposited on the entire surface (for example, after being deposited by vacuum deposition), Ti / Pt / Au deposited on the resist film together with the resist film is removed (that is, A source electrode 35 and a drain electrode 34 having a three-layer structure of Ti / Pt / Au are formed by a lift-off method. Thereby, the source electrode 35 and the drain electrode 34 are formed on the metal layer 31 [see FIG. 11C].

Next, after removing the resist film, for example, an electron beam exposure method or the like is used to define a T-type gate electrode region having a T-shaped cross-sectional shape. A resist film is provided.
Then, after the other insulating film 40 is removed by dry etching, Ni and Au are sequentially deposited on the entire surface (for example, after vapor deposition by a vacuum vapor deposition method), and then Ni / deposited on the resist film together with the resist film. By removing Au (that is, by lift-off method), a Ni / Au two-layer gate electrode 33 is formed in the recess 32 [see FIG. 11C]. Accordingly, the umbrella portion 33A having a size larger than the recess 32 (longer than the recess length) and the shaft portion 33B supporting the umbrella portion 33A are formed on the n-AlGaN electron supply layer 38 constituting the bottom surface of the recess 32. A T-shaped gate electrode 33 having a T-shaped cross section is formed. Here, the end face of the gate electrode 33 and the n-AlGaN electron supply layer 38 are in Schottky contact.

Therefore, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, it is possible to improve the breakdown voltage and the reliability by forming the insulating film while reducing the source resistance and improving the mutual conductance gm. There are advantages.
In particular, as shown in FIG. 11C, at least the entire portion exposed on the surface of the semiconductor multilayer structure 30 [here, the surface (upper surface) of the electron supply layer 38 constituting the bottom surface of the recess 32] is in contact. Further, by forming another insulating film (protective film) 40, the breakdown voltage and the reliability can be improved.

Note that the structure and manufacturing method of the present GaN-HEMT are not limited to those of the above-described embodiment. For example, it can also be configured as in the following modification.
In the manufacturing method of this modification, in the process of performing dry etching (anisotropic etching) for forming the recess 32 of the manufacturing method of the above-described embodiment, not only the insulating film 39 and the metal layer 31 but also n -A part of the AlGaN electron supply layer 38 is also removed by etching to form a recess 32X [see FIG. 11D]. That is, the recess is formed in the metal layer 31 and the semiconductor laminated structure 30 (here, a part of the n-AlGaN electron supply layer 38). As a result, the n-AlGaN electron supply layer 38 is exposed, and the n-AlGaN electron supply layer 38 forms the bottom surface (InP recess surface) of the recess 32X and the side surface of the recess 32X. In this case, since the thickness of the n-AlGaN electron supply layer 38 is reduced, the mutual conductance gm can be further improved.

  In the configuration of this modification, as shown in FIG. 11D, the layer constituting the side surface of the recess 32X is the uppermost semiconductor layer (here, the n-AlGaN electron supply layer 38) of the semiconductor multilayer structure 30. . The layers or films formed above the layer constituting the side surface of the recess 32 </ b> X are the metal layer 31 and the insulating film 39. Furthermore, the openings 31A and 39A of the metal layer 31 and the insulating film 39 have the same size as the opening 38A of the uppermost semiconductor layer (here, the n-AlGaN electron supply layer 38). The opening 39A of the insulating film 39 has the same size as the opening 31A of the metal layer 31.

  However, the present invention is not limited to this, and the metal layer 31 and the insulating layer 31 can be formed so that at least another insulating film (here, the insulating film 40) in contact with the entire portion exposed on the surface of the semiconductor multilayer structure 30 can be formed. It suffices that the openings 31A and 39A of the film 39 are larger than the size of the opening 38A of the uppermost semiconductor layer (here, the n-AlGaN electron supply layer 38). Further, it is only necessary that the opening 39A of the insulating film 39 is larger than the size of the opening 31A of the metal layer 31 (the opening of the recess 32X).

  Thus, when there are a plurality of layers or films (here, the metal layer 31 and the insulating film 39) formed above the layer (here, the n-AlGaN electron supply layer 38) constituting the side surface of the recess 32X, The size of the upper layer or film opening (here, the opening 39A of the insulating film 39) between adjacent layers or films is lower than the lower layer or film opening (here the metal layer 31). It is preferable that it is the same as the opening 31A) or larger. As a result, the eaves structure of the upper layer or film (here, the insulating film 39) cannot be formed, so that it is exposed to the surface of the metal layer 31 as shown in FIG. The other insulating film 40 can be formed so as to be in contact with the portion (side surface of the metal layer 31), and by forming such another insulating film 40, the breakdown voltage and the reliability can be improved. become.

  In the semiconductor device manufacturing method according to the above-described embodiment and its modification, the other insulating film 40 is formed before the gate electrode 33 is formed. However, the present invention is not limited to this. Another insulating film 40 may be formed after the electrode 33 is formed. In this case, the other insulating film 40 is formed so as to cover the entire surface including the gate electrode 33.

In the method for manufacturing a semiconductor device according to the modification of the above-described embodiment, the insulating film 39 and the other insulating film 40 are formed before the source electrode 35 and the drain electrode 34 are formed. For example, as in the second embodiment described above, after forming the source electrode and the drain electrode, the insulating film 39 and the other insulating film 40 may be formed so as to cover the source electrode and the drain electrode. . In this case, the insulating film 39 and the other insulating film 40 are also formed on the source electrode and the drain electrode.
[Others]
In each of the above embodiments, the metal layer provided on the n-InGaAs cap layer is WSi and the metal layer provided on the n-AlGaN electron supply layer is a TiAl layer. However, the material of the metal layer is limited to this. It is not a thing. For example, materials that are relatively easy to dry etch, such as silicides such as W, Mo, Ta, MoSi, and TaSi, compounds with Ti such as TiW, TiMo, and TiTa, nitrides such as WN, MoN, and TaN, WSiN, It is preferable to use silicide nitride such as MoSiN or TaSiN. Al, AlSi (silicide), or the like may be used.

In each of the above-described embodiments, the case where the present invention is applied to InP-HEMT or GaN-HEMT is described as an example. However, the present invention is not limited to this, and the present invention is also applied to other HEMTs. can do.
The present invention is not limited to the above-described embodiments and modifications, and various modifications can be made without departing from the spirit of the present invention.

Hereinafter, additional notes will be disclosed regarding each of the above-described embodiments.
(Appendix 1)
A plurality of semiconductor layers stacked, and a semiconductor stacked structure having a recess;
A metal layer formed on the semiconductor multilayer structure and having an opening at a position corresponding to the recess;
A gate electrode provided in the recess and having an umbrella part and a shaft part supporting the umbrella part;
A drain electrode and a source electrode formed on the metal layer and provided on both sides of the gate electrode;
The opening of the metal layer is equal to or larger than the size of the opening of the recess,
The semiconductor device is characterized in that the metal layer is formed so as to enter under the umbrella portion of the gate electrode.

(Appendix 2)
The uppermost semiconductor layer of the semiconductor multilayer structure is a semiconductor cap layer,
The semiconductor device according to appendix 1, wherein the recess is formed in the semiconductor cap layer.
(Appendix 3)
An insulating film formed on the metal layer and having an opening;
The semiconductor device according to appendix 1 or 2, wherein the opening of the insulating film is the same as or larger than the opening of the metal layer.

(Appendix 4)
The semiconductor device according to any one of appendices 1 to 3, wherein the metal layer has a thickness on the gate electrode side thinner than a thickness on the drain electrode or source electrode side. .
(Appendix 5)
The semiconductor device according to appendix 4, wherein the metal layer has an end portion on the gate electrode side gradually becoming thinner.

(Appendix 6)
The semiconductor device according to any one of appendices 1 to 5, further comprising an insulating film in contact with an entire portion exposed on a surface of the semiconductor multilayer structure.
(Appendix 7)
The semiconductor device according to any one of appendices 1 to 6, wherein the semiconductor stacked structure is formed on a semiconductor substrate and includes an electron supply layer and an electron transit layer.

(Appendix 8)
A semiconductor laminated structure in which a plurality of semiconductor layers containing GaN are laminated;
A metal layer formed on the semiconductor multilayer structure and formed with a recess;
A gate electrode provided in the recess and having an umbrella part and a shaft part supporting the umbrella part;
A drain electrode and a source electrode formed on the metal layer and provided on both sides of the gate electrode;
The semiconductor device, wherein the metal layer is formed so as to enter under the umbrella portion of the gate electrode.

(Appendix 9)
The semiconductor device according to appendix 8, wherein the recess is formed in the metal layer and the semiconductor stacked structure.
(Appendix 10)
On the semiconductor substrate, a semiconductor laminated structure formed by laminating a plurality of semiconductor layers is formed,
Forming a metal layer on the semiconductor multilayer structure;
Forming a recess-forming opening in the metal layer;
Forming a recess through the recess forming opening,
Widen the opening for forming the recess,
A method of manufacturing a semiconductor device, comprising: forming a gate electrode having an umbrella part and a shaft part supporting the umbrella part in the recess.

(Appendix 11)
The method of manufacturing a semiconductor device according to claim 10, wherein the step of forming the recess is performed by wet etching.
(Appendix 12)
After forming the metal layer and before forming the recess forming opening, an insulating film is formed on the metal layer,
12. The method for manufacturing a semiconductor device according to appendix 10 or 11, wherein a recess forming opening is formed in the metal layer and the insulating film.

(Appendix 13)
The semiconductor device according to any one of appendices 10 to 12, wherein an insulating film is formed at least in a portion exposed on the surface of the semiconductor multilayer structure before or after the gate electrode is formed. Production method.
(Appendix 14)
14. The method of manufacturing a semiconductor device according to any one of appendices 10 to 13, wherein each of the plurality of semiconductor layers includes a compound semiconductor.

(Appendix 15)
15. The method of manufacturing a semiconductor device according to any one of appendices 10 to 14, wherein the semiconductor substrate includes InP.
(Appendix 16)
16. The method of manufacturing a semiconductor device according to any one of appendices 10 to 15, wherein the metal layer is in ohmic contact with the uppermost semiconductor layer of the semiconductor multilayer structure.

(Appendix 17)
17. The method of manufacturing a semiconductor device according to any one of appendices 10 to 16, wherein the gate electrode is in Schottky contact with the semiconductor layer exposed in the recess.
(Appendix 18)
The etching is performed so that the thickness of the metal layer on the side of the gate electrode is thinner than the thickness of the side of the drain electrode or the source electrode in order to widen the opening for forming the recess. The manufacturing method of the semiconductor device of any one of -17.

(Appendix 19)
19. The method of manufacturing a semiconductor device according to appendix 18, wherein the etching is performed so that an end of the metal layer on the gate electrode side is gradually thinned.

It is a typical sectional view showing the composition of the semiconductor device (InP-HEMT) concerning a 1st embodiment of the present invention. (A), (B) is typical sectional drawing for demonstrating the subject of the semiconductor device (InP-HEMT) concerning 1st Embodiment of this invention. (A)-(C) are typical sectional drawings used when demonstrating the effect of the semiconductor device (InP-HEMT) concerning 1st Embodiment of this invention compared with the thing of another structure, (A) is a structure including only an InGaAs cap layer, (B) is a structure including an InGaAs cap layer and a metal layer, and the metal layer does not enter under the umbrella portion of the gate electrode, and (C) is an InGaAs cap layer. And a structure in which the metal layer is provided below the umbrella portion of the gate electrode. (A)-(K) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device (InP-HEMT) concerning 1st Embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device (InP-HEMT) concerning 2nd Embodiment of this invention. (A)-(I) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device (InP-HEMT) concerning 2nd Embodiment of this invention. (A)-(C) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device (InP-HEMT) concerning the modification of 2nd Embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device (InP-HEMT) concerning 3rd Embodiment of this invention. It is a schematic diagram which shows the structure of the semiconductor device (InP-HEMT) concerning the modification of 3rd Embodiment of this invention. (A)-(D) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device (InP-HEMT) concerning 3rd Embodiment of this invention. (A) is typical sectional drawing which shows the structure of the conventional GaN-HEMT, (B) is typical sectional drawing which shows the structure of the semiconductor device (GaN-HEMT) concerning 4th Embodiment of this invention. (C) and (D) are schematic cross-sectional views showing the configuration of a semiconductor device (GaN-HEMT) according to a modification of the fourth embodiment of the present invention.

Explanation of symbols

1 InP substrate (semiconductor substrate)
2 Buffer layer 3 Channel layer (electron travel layer, carrier travel layer)
4 Electron supply layer (carrier supply layer)
5 Stopper layer (etching stop layer)
6 Cap layer (contact layer)
6A Opening 7 Recess 8 Gate electrode 8A Umbrella 8B Shaft 9 Metal layer 9A Opening 9X Recess forming opening 9Y A portion protruding above the recess in the metal layer (eave structure)
10 drain electrode 11 source electrode 12, 13, 14, 16 resist film 15 semiconductor laminated structure 17 insulating film (protective film)
17A Opening 17X Opening for recess formation 17Y Projecting part of insulating film above recess (eave structure)
18 Insulating film (protective film)
18A Opening 20 Insulating film 30 Semiconductor laminated structure 31 Metal layer 31A Opening 32, 32X Recess 33 Gate electrode 33A Umbrella 33B Shaft 34 Drain electrode 35 Source electrode 36 SiC substrate (semiconductor substrate)
37 channel layer (electron traveling layer, carrier traveling layer)
38 Electron supply layer (carrier supply layer)
38A Opening 39 Insulating film (protective film)
39A Opening 40 Insulating film (protective film)

Claims (10)

A plurality of semiconductor layers stacked, and a semiconductor stacked structure having a recess;
A metal layer formed on the semiconductor multilayer structure and having an opening at a position corresponding to the recess;
A gate electrode provided in the recess and having an umbrella part and a shaft part supporting the umbrella part;
A drain electrode and a source electrode formed on the metal layer and provided on both sides of the gate electrode ;
An insulating film formed on the metal layer and having an opening ;
The opening of the metal layer is equal to or larger than the size of the opening of the recess,
The opening of the insulating film is the same as or larger than the size of the opening of the metal layer,
The metal layer is formed so as to enter under the umbrella part of the gate electrode ,
The semiconductor device , wherein the insulating film is not in contact with the umbrella portion of the gate electrode . The uppermost semiconductor layer of the semiconductor multilayer structure is a semiconductor cap layer,
The semiconductor device according to claim 1, wherein the recess is formed in the semiconductor cap layer.   3. The semiconductor device according to claim 1, wherein the metal layer has a thickness on the gate electrode side thinner than a thickness on the drain electrode or source electrode side. On the semiconductor substrate, a semiconductor laminated structure formed by laminating a plurality of semiconductor layers is formed,
Forming a metal layer on the semiconductor multilayer structure;
Forming a recess-forming opening in the metal layer;
Forming a recess through the recess forming opening,
Widen the opening for forming the recess,
A method of manufacturing a semiconductor device, comprising: forming a gate electrode having an umbrella part and a shaft part supporting the umbrella part in the recess.   The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the recess is performed by wet etching. After forming the metal layer and before forming the recess forming opening, an insulating film is formed on the metal layer,
6. The method of manufacturing a semiconductor device according to claim 4, wherein a recess forming opening is formed in the metal layer and the insulating film.   The semiconductor device according to claim 4, wherein an insulating film is formed at least on a portion exposed on the surface of the semiconductor multilayer structure before or after the gate electrode is formed. Manufacturing method.   The method of manufacturing a semiconductor device according to claim 4, wherein each of the plurality of semiconductor layers includes a compound semiconductor.   The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor substrate contains InP.   The etching is performed so that a thickness on the gate electrode side of the metal layer is thinner than a thickness on the drain electrode or source electrode side in order to widen the recess forming opening. The manufacturing method of the semiconductor device of any one of 4-9.

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