CN107887383A - GaN-based monolithic power inverter and manufacturing method thereof - Google Patents
GaN-based monolithic power inverter and manufacturing method thereof Download PDFInfo
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- CN107887383A CN107887383A CN201711081961.XA CN201711081961A CN107887383A CN 107887383 A CN107887383 A CN 107887383A CN 201711081961 A CN201711081961 A CN 201711081961A CN 107887383 A CN107887383 A CN 107887383A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000002161 passivation Methods 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 39
- 238000002360 preparation method Methods 0.000 claims abstract description 19
- 238000000407 epitaxy Methods 0.000 claims description 28
- 239000000463 material Substances 0.000 claims description 17
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 230000010354 integration Effects 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 238000012163 sequencing technique Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000005036 potential barrier Methods 0.000 claims description 3
- 229910002058 ternary alloy Inorganic materials 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 113
- 238000002347 injection Methods 0.000 description 10
- 239000007924 injection Substances 0.000 description 10
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052738 indium Inorganic materials 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910002059 quaternary alloy Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910004541 SiN Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
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- 230000004069 differentiation Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
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- 239000011241 protective layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Ceramic Engineering (AREA)
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- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a GaN-based monolithic power inverter and a manufacturing method thereof, wherein the power inverter comprises: a heterojunction epitaxial substrate; a passivation layer formed on the heterojunction epitaxial substrate, with a plurality of hollow regions between the passivation layers; enhancement mode power triode structure forms in a plurality of hollow regions, includes: the first source electrode and the first drain electrode are in ohmic contact with the thin barrier layer, and the first grid electrode is insulated from the thin barrier layer through a first grid dielectric layer positioned below the first grid electrode; and a depletion mode power transistor structure formed in the remaining hollow region, including: the second source electrode and the second drain electrode are in ohmic contact with the thin barrier layer, and the second grid electrode is insulated from the passivation layer through a second grid dielectric layer positioned below the second grid electrode or directly contacts the passivation layer. The power converter is simple in preparation process, diversified in structure and capable of improving the yield of devices.
Description
Technical field
The disclosure belongs to technical field of semiconductor device, is related to a kind of GaN base monolithic power inverter and preparation method thereof.
Background technology
The power inverting that the cascade of enhanced (normally OFF) and depletion type (normall ON) pliotron is formed
Device (power Inverter) is the elementary cell of inverter circuit, applied to various DC/AC conversion modules.But at present same
Realize that high-performance is enhanced and depletion type GaN base power diode technology difficulty is larger, constrains GaN base power on substrate simultaneously
Integrated circuit is to high-effect, the development of small intelligent application direction.Therefore, need badly provide it is a kind of it is new on the same substrate can be same
Shi Shixian is enhanced and the monolithic integrated power inverter and preparation method of depletion type, and manufacture craft is simple, conveniently, helps
In the application and development that promote GaN base power integrated circuit.
The content of the invention
(1) technical problems to be solved
Present disclose provides a kind of GaN base monolithic power inverter and preparation method thereof, at least partly to solve above institute
The technical problem of proposition.
(2) technical scheme
According to an aspect of this disclosure, there is provided a kind of GaN base monolithic power inverter, including：Heterogenous junction epitaxy serves as a contrast
Bottom, including：The hetero-junctions that GaN cushions and thin barrier layer are formed, two-dimensional electron gas is produced in the interface of hetero-junctions；Passivation
Layer, is formed at heterogenous junction epitaxy substrate, multiple hollow areas between passivation layer be present；Enhanced power triode knot
Structure, some hollow areas being formed in multiple hollow areas, including：First source electrode, the first drain electrode and first grid, this first
Source electrode, the first drain electrode realize Ohmic contact with thin barrier layer, and the first grid passes through the first gate dielectric layer for being disposed below
Realize and insulate with thin barrier layer；And depletion type pliotron structure, other hollow sections being formed in multiple hollow areas
Domain, including：Second source electrode, the second drain electrode and second grid, second source electrode, the second drain electrode realize that ohm connects with thin barrier layer
Touch, the second grid realizes insulation with passivation layer by the second gate dielectric layer being disposed below or directly contacts passivation layer.
In some embodiments of the present disclosure, GaN base monolithic power inverter, in addition to：Isolated area is injected, is arranged at the
Between one drain electrode and the second source electrode and the first source electrode and the edge of the second drain electrode, heterogenous junction epitaxy is extended to from passivation layer
In the GaN cushions of substrate.
In some embodiments of the present disclosure, the hetero-junctions of heterogenous junction epitaxy substrate is formed on epitaxial substrate, the extension
Substrate is one kind in following material：Si, SiC, sapphire or GaN wafer.
In some embodiments of the present disclosure, the material of thin barrier layer is one kind in following material：AlGaN, AlInN tri-
First alloy or AlInGaN quaternary alloy；And/or the thickness t of thin barrier layer meets：0 ＜ t≤6nm.
In some embodiments of the present disclosure, passivation layer is one kind in following material：SiN, SiO2Or SiON；And/or
The thickness of passivation layer is between 5nm~120nm.
In some embodiments of the present disclosure, hollow area includes successively：First source contact openings area, first grid opening
Area, the first drain openings area, the second source contact openings area and the second drain openings area；First source electrode, the first drain electrode, the second source
Pole, the second drain electrode are correspondingly formed opens in the first source contact openings area, the first drain openings area, the second source contact openings area, the second drain electrode
Mouth region, realize Ohmic contact；First gate dielectric layer, at least two side of covering first grid open region and bottom and its both sides
Portion of the passivating layer, interval be present with source electrode, drain electrode；Second gate dielectric layer, the passivation between the second source electrode and the second drain electrode
On layer.
According to another aspect of the disclosure, there is provided a kind of preparation method of GaN base monolithic power inverter, including：
Passivation layer is prepared on heterogenous junction epitaxy substrate, wherein, the heterogenous junction epitaxy substrate includes：GaN cushions and thin barrier layer shape
Into hetero-junctions, hetero-junctions interface produce two-dimensional electron gas；Etch Passivation, be prepared the first source contact openings area,
First grid open region, the first drain openings area, the second source contact openings area and the second drain openings area；In the first source contact openings
Area, the first drain openings area, the second source contact openings area and the second drain openings area the first source electrode of corresponding deposition, the first drain electrode, the
Two source electrodes and the second drain electrode, make Ohmic contact；And the first gate dielectric layer and first grid are made in first grid open region,
The second gate dielectric layer and second grid are made on passivation layer between the second source electrode and the second drain electrode or only make second gate
Pole；Complete the monolithic of GaN base depletion type and reinforced metal insulating barrier semiconductor HEMT (MIS-HEMTs)
It is integrated.
In some embodiments of the present disclosure, also comprise the following steps after Ohmic contact has been made：In the first drain electrode
And second between source electrode and the first source electrode and the edge of the second drain electrode carry out ion implanting isolation.
In some embodiments of the present disclosure, in Etch Passivation, the first source contact openings area is prepared, first grid is opened
In the step of mouth region, the first drain openings area, the second source contact openings area and the second drain openings area：First grid open region with
First source contact openings area, the first drain openings area are opened simultaneously；Or opened according to sequencing, wherein, first
Source contact openings area and the first drain openings area are first opened, or first grid open region is first opened.
In some embodiments of the present disclosure, passivation layer with the following method in one kind prepared：MOCVD, LPCVD
Or PECVD；And/or Etch Passivation uses F base plasma etchings, realize etching from cut-off on the surface of thin barrier layer.
(3) beneficial effect
It can be seen from the above technical proposal that GaN base monolithic power inverter that the disclosure provides and preparation method thereof, tool
There is following beneficial effect：
(1) using the hetero-epitaxy substrate of the hetero-junctions formed comprising GaN cushions and thin barrier layer, on the boundary of hetero-junctions
Two-dimensional electron gas is produced at face, formation need not etch the enhanced grid of Al (In, Ga) N barrier layers, and the two dimension beyond grid is electric
Sub- gas is realized by passivation layer to be recovered, and is reduced the manufacture difficulty of the enhanced grid of GaN base, is effectively increased device yield；
(2) selective etch passivation layer is used, while realizes enhanced and depletion type MIS-HEMTs integrated making, work
Skill is simple, cost is cheap；
(3) source electrode, drain electrode, grid etc. can simultaneously be opened or opened step by step, simplified manufacture craft, more entered one
Step, depletion type MIS-HEMT can be the gate mediums that side adds enhanced MIS-HEMT under the gate, form double layer gate dielectric,
This layer of gate medium can not be added, individual layer gate medium is only served as by passivation layer, structure diversification, technique is simple, has promoted GaN base
Monolithic power integrated circuit to it is more efficient can and small compact application development.
Brief description of the drawings
Figure 1A is a kind of structural representation according to embodiment of the present disclosure GaN base monolithic power inverter.
Figure 1B is another structural representation according to embodiment of the present disclosure GaN base monolithic power inverter.
Fig. 2 is the preparation method flow chart according to embodiment of the present disclosure GaN base monolithic power inverter.
Fig. 3 is the structure according to corresponding to each step in the preparation method of embodiment of the present disclosure GaN base monolithic power inverter
Schematic diagram.
【Symbol description】
10- heterogenous junction epitaxy substrates；
101- epitaxial substrates；102-GaN cushions；
The thin barrier layers of 103-；111- two-dimensional electron gas；
20- passivation layers；
The first source contact openings of 201- area；The first drain openings of 202- area；
203- first grids open region；The second source contact openings of 204- area；
The second drain openings of 205- area；
The source electrodes of 301- first；302- first drains；
The source electrodes of 304- second；305- second drains；
401- first injects isolated area；402- second injects isolated area；
403- the 3rd injects isolated area；
The gate dielectric layers of 501- first；The gate dielectric layers of 502- second；
601- first grids；602- second grids.
Embodiment
Present disclose provides a kind of GaN base monolithic power inverter and preparation method thereof, by using ultra-thin potential barrier Al
(In, Ga) N/GaN heterogenous junction epitaxy substrates, in deposit polycrystalline SiN thereon, SiO2, SiON passivation layers, without etch Al (In,
Ga) N barrier layers, GaN base depletion type and reinforced metal insulating barrier semiconductor HEMT (MIS- can be achieved
HEMTs, metal-insulator-semiconductor high-electron-mobility transistors) monolithic
Integrated and manufacture；Realize that GaN base is enhanced and the industrialization preparation of depletion type pliotron and single-chip integration on the whole, have
Push and moved GaN power integrated circuits towards high-effect, small compact direction is developed.
For the purpose, technical scheme and advantage of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the disclosure is further described.
In first exemplary embodiment of the disclosure, there is provided a kind of GaN base monolithic power inverter.
Figure 1A is a kind of structural representation according to embodiment of the present disclosure GaN base monolithic power inverter；According to Figure 1B
Another structural representation of embodiment of the present disclosure GaN base monolithic power inverter.
With reference to shown in Figure 1A and Figure 1B, a kind of GaN base monolithic power inverter of the disclosure, including：Heterogenous junction epitaxy serves as a contrast
Bottom 10, including：The hetero-junctions that GaN cushions 102 and thin barrier layer 103 are formed, Two-dimensional electron is produced in the interface of hetero-junctions
Gas 111；Passivation layer 20, is formed on heterogenous junction epitaxy substrate 10, multiple hollow areas between passivation layer be present；It is enhanced
Pliotron structure, some hollow areas being formed in multiple hollow areas, including：First source electrode 301, first drains
302 and first grid 601, first source electrode 301, first drain electrode 302 realizes Ohmic contact with thin barrier layer 103, and this first
Grid 601 is realized by the first gate dielectric layer 501 being disposed below with thin barrier layer 103 to insulate；And depletion type power three
Pole pipe structure, other hollow areas being formed in multiple hollow areas, including：Second source electrode 304, second drain electrode 305 and the
Two grids 602, second source electrode 304, second drain electrode 305 realize Ohmic contact with thin barrier layer 103, the second grid 602
Insulation is realized with passivation layer 20 by the second gate dielectric layer 502 being disposed below or directly contacts passivation layer 20.
The concrete structure of the GaN base monolithic power inverter is introduced with one embodiment below.
GaN base monolithic power inverter in the present embodiment, including：
Heterogenous junction epitaxy substrate 10；
Passivation layer 20, it is formed on heterogenous junction epitaxy substrate 10, multiple hollow areas is formed between passivation layer 20, should
Hollow area includes successively：First source contact openings area 201, first grid open region 203, the first drain openings area 202, the second source
The drain openings area 205 of pole open region 204 and second；
First source electrode 301, at least cover the portion of the passivating layer 20 of the first source contact openings area 201 and its both sides；
First drain electrode 302, at least cover the portion of the passivating layer 20 of the first drain openings area 202 and its both sides；
Second source electrode 304, at least cover the portion of the passivating layer 20 of the second source contact openings area 204 and its both sides；
Second drain electrode 305, at least cover the portion of the passivating layer 20 of the second drain openings area 205 and its both sides；
Isolated area is injected, is arranged between the first drain electrode 302 and the second source electrode 304 and the first source electrode 301 and second leaks
The edge of pole 305, in the GaN cushions 102 for extending to heterogenous junction epitaxy substrate 10 from passivation layer 20；
First gate dielectric layer 501, at least cover the partial deactivation of the two side and bottom and its both sides of grid open region 203
Layer 20, exist with source electrode 301, drain electrode 302 and be spaced；
First grid 601, it is formed on the first gate dielectric layer 501；And
Second grid 602, between the second source electrode 304 and the second drain electrode 305, it is formed on passivation layer 20, forms
The structure of individual layer gate medium, the single-chip integration of GaN base depletion type and enhanced MIS-HEMTs transistors is realized, as shown in Figure 1A；
Can be double-deck in the structure of other GaN base monolithic power inverters, in depletion type MIS-HEMTs transistors
Gate dielectric structure, as shown in Figure 1B, the second gate medium 502 are formed on passivation layer 20, and second grid 602 is located at second gate Jie
On matter 502, the double layer gate dielectric structure being made up of the gate dielectric layer 502 of passivation layer 20 and second is formd, realizes that GaN base exhausts
The single-chip integration of type and enhanced MIS-HEMTs transistors.
In the present embodiment, heterogenous junction epitaxy substrate 10 is epitaxial structure, is followed successively by from bottom to top：Epitaxial substrate 101, GaN
Cushion 102, and thin barrier layer 103；Two dimension electricity is produced at the heterojunction boundary that GaN cushions 102 contact with barrier layer
Sub- gas 111, as shown in Figure 1A.
In the present embodiment, epitaxial substrate 101 is optional but the one or more that are not limited in following material：Si, SiC, Lan Bao
Stone or GaN wafer etc..
In the present embodiment, thin barrier layer 103 is optional but the one or more that are not limited in following material：AlGaN, AlInN
Ternary alloy three-partalloy or AlInGaN quaternary alloys, its thickness is between 0~6nm, to be carried out exemplified by Al (In, Ga) N in the present embodiment
Explanation.
In the present embodiment, using protective layer of the passivation layer 20 as the two-dimensional electron gas beyond grid, avoid existing
Depletion type is prepared in technology and during enhanced MIS-HEMTs to the etching of barrier layer, be favorably improved the yield rate of device；Simultaneously
The passivation layer also carries out the first source contact openings area 201, the first drain openings area 202, first grid opening as hard mask plate
The making of the hollow areas such as area 203, the second source contact openings area 204 and the second drain openings area 205.
In the present embodiment, the material of the passivation layer 20 is optional but one kind for being not limited in following material：SiN, SiO2Or
SiON, its thickness is between 5nm~120nm.
In the present embodiment, passivation layer can with the following method in one kind prepared：MOCVD(metal-organic
Chemical vapor deposition), LPCVD (low pressure chemical vapor deposition) or
PECVD (plasma-enhanced chemical vapor deposition) etc..
In the present embodiment, drained by carrying out the first source contact openings area 201, first using passivation layer 20 as hard mask plate
The hollow areas such as open region 202, first grid open region 203, the second source contact openings area 204 and the second drain openings area 205
Making, then above-mentioned hollow area make the first source electrode 301, first drain the 302, second source electrode 304, second drain electrode 305,
Realize Ohmic contact.
Shown in reference picture 1A, in the present embodiment, injection isolated area is respectively labeled as first according to the difference of position
Inject isolated area 401, second and inject the injection isolated area 403 of isolated area 402 and the 3rd, wherein, the first injection isolated area 401
In the edge of the first source electrode 301, in the GaN cushions 102 that extend to heterogenous junction epitaxy substrate 10 from passivation layer 20；Second
The edge that isolated area 402 is located at the second drain electrode 305 is injected, the GaN of heterogenous junction epitaxy substrate 10 is extended to from passivation layer 20
In cushion 102；3rd injection isolated area 403 is between the first drain electrode 302 and the second source electrode 304, from passivation layer 20 always
Extend in the GaN cushions 102 of heterogenous junction epitaxy substrate 10；These injection isolated areas realize the isolation of active area, help
In raising breakdown voltage, while device edge is arranged at, helps to reduce place electric leakage, improve the temperature stability of device.
In the present embodiment, the material of the first gate dielectric layer 501 and the second gate dielectric layer 502 can be selected but be not limited to following material
One or more in material：Al2O3, SiN, SiON or SiO2Deng.
In second exemplary embodiment of the disclosure, there is provided a kind of making side of GaN base monolithic power inverter
Method.
Fig. 2 is the preparation method flow chart according to embodiment of the present disclosure GaN base monolithic power inverter.Fig. 3 is according to this
Structural representation corresponding to each step in the preparation method of open embodiment GaN base monolithic power inverter.
With reference to shown in Fig. 2 and Fig. 3, the preparation method of the GaN base monolithic power inverter of the disclosure, including：
Step S202：Passivation layer is prepared on heterogenous junction epitaxy substrate；
In the present embodiment, heterogenous junction epitaxy substrate 10 is epitaxial structure, is followed successively by from bottom to top：Epitaxial substrate 101, GaN
Cushion 102, and thin barrier layer 103；Two dimension electricity is produced at the heterojunction boundary that GaN cushions 102 contact with barrier layer
Sub- gas 111.
In reference picture 3 shown in (a), one layer of passivation layer 20 is deposited on the epitaxial structure of heterogenous junction epitaxy substrate 10.
In the present embodiment, epitaxial substrate 101 is optional but the one or more that are not limited in following material：Si, SiC, Lan Bao
Stone or GaN wafer etc.；Thin barrier layer 103 is optional but the one or more that are not limited in following material：AlGaN, AlInN ternary
Alloy or AlInGaN quaternary alloys, its thickness is between 0~6nm, with ultra-thin potential barrier Al (In, Ga) N/GaN in the present embodiment
Illustrated exemplified by heterogenous junction epitaxy substrate.
In the present embodiment, passivation layer 20 can with the following method in one kind prepared：MOCVD(metal-
Organic chemical vapor deposition), LPCVD (low pressure chemical vapor
) or PECVD (plasma-enhanced chemical vapor deposition) etc. deposition.
Step S204：Etch Passivation, be prepared the first source contact openings area, first grid open region, first drain electrode open
Mouth region, the second source contact openings area and the second drain openings area；
Multiple hollow areas are etched in the passivation layer 20 as shown in (a) in Fig. 3, the hollow area is from left to right successively
Including：First source contact openings area 201, first grid open region 203, the first drain openings area 202, the second source contact openings area 204
And the second drain openings area 205, the two-dimensional electron gas 111 below corresponding open region also disappears, in Fig. 3 shown in (b).
In the present embodiment, enhanced MIS-HEMT gate openings area can be with source contact openings area, drain openings area simultaneously
Opened, can also be opened according to sequencing, wherein it is possible to be that source contact openings area and drain openings area first open,
Can also be that gate openings area first opens.That is, first grid open region and the first source contact openings area, the first drain openings area be simultaneously
Opened；Or opened according to sequencing, wherein, the first source contact openings area and the first drain openings area first open,
Or first grid open region is first opened.
Here lithographic method can use etch tool of the prior art, it is preferred that be carved using F bases plasma
Erosion, on the surface of the thin barrier layers such as Al (In, Ga) N etching can be realized from cut-off.
Step S206：In the first source contact openings area, the first drain openings area, the second source contact openings area and the second drain openings
Area's the first source electrode of corresponding deposition, the first drain electrode, the second source electrode and the second drain electrode, make Ohmic contact；
In reference picture 3 shown in (c), in the first source contact openings area 201, the first drain openings area 202, the second source contact openings area
204 and second corresponding deposition the first source electrode 301, first drain electrode the 302, second source electrode 304 of drain openings area 205 and the second drain electrode
305, Ohmic contact is made, now, the corresponding two-dimensional electron gas 111 filled with electrode zone is recovered.
Step S208：First drain electrode the second source electrode between and the first source electrode and second drain electrode edge carry out ion
Injection isolation；
In reference picture 3 shown in (d), in the GaN cushions 102 for extending to heterogenous junction epitaxy substrate 10 from passivation layer 20
Carry out ion implanting；The region of injection isolation is：The edge of first source electrode 301, the edge of the second drain electrode 305 and the first drain electrode
302 and second between source electrode 304, and the first injection isolated area 401, second of (d) injects isolated area 402 and the in reference picture 3
Shown in three injection isolated areas 403.These injection isolated areas realize the isolation of active area, are favorably improved breakdown voltage, simultaneously
Device edge is arranged at, helps to reduce place electric leakage, improves the temperature stability of device.
Step S210：The first gate dielectric layer and first grid are made in first grid open region, in the second source electrode and second
The second gate dielectric layer and second grid are made on passivation layer between drain electrode or only makes second grid, GaN base is completed and exhausts
The single-chip integration of type and enhanced MIS-HEMTs transistors；
The structure of respective production as shown in Figure 1A, in step S210：In reference picture 3 shown in (e), now by dotted portion
It is considered as and is not present, makes the first gate dielectric layer 501 in first grid open region 203, first gate dielectric layer 501 is at least covered
The portion of the passivating layer 20 of the two side of first grid open region 203 and bottom and its both sides, drained with the first source electrode 301, first
302 have interval；In Fig. 3 shown in (f), now dotted portion is considered as and is not present, on the first gate dielectric layer 501
Side deposits first grid 601, and second grid 602 is made on the passivation layer 20 between the second source electrode 304 and the second drain electrode 305.
The structure of respective production as shown in Figure 1B, in step S210：In reference picture 3 shown in (e), dotted portion is considered as
In the presence of, first grid open region 203 make the first gate dielectric layer 501, first gate dielectric layer 501 is at least covered the first grid
The portion of the passivating layer 20 of the two side of pole open region 203 and bottom and its both sides, exist with the first source electrode 301, first drain electrode 302
Interval；The second gate dielectric layer 502 is made on passivation layer 20 between the second source electrode 304 and the second drain electrode 305；Referring next to figure
In 3 shown in (f), dotted portion is now considered as presence, in the disposed thereon first grid 601 of the first gate dielectric layer 501, second
Second grid 602 is made on gate dielectric layer 502.
In summary, present disclose provides a kind of GaN base monolithic power inverter and preparation method thereof, by using comprising
The hetero-epitaxy substrate for the hetero-junctions that GaN cushions and thin barrier layer are formed, two-dimensional electron gas is produced in the interface of hetero-junctions,
The enhanced grid of Al (In, Ga) N barrier layers need not be etched by being formed, and the two-dimensional electron gas beyond grid realized by passivation layer it is extensive
It is multiple, the manufacture difficulty of the enhanced grid of GaN base is reduced, effectively increases device yield；Using selective etch passivation layer, together
Shi Shixian is enhanced and depletion type MIS-HEMTs integrated making, and technique is simple, cost is cheap；Source electrode, drain electrode, grid etc. can
Opened or opened step by step simultaneously, simplify manufacture craft, further, depletion type MIS-HEMTs can be in grid
Lower section adds enhanced MIS-HEMTs gate medium, forms double layer gate dielectric, this layer of gate medium can not also be added, only by blunt
Change layer and serve as individual layer gate medium, structure diversification, technique is simple, has promoted GaN base monolithic power integrated circuit to more efficient energy
With small compact application development.
It should be noted that the direction term mentioned in embodiment, such as " on ", " under ", "front", "rear", "left", "right"
Deng, be only refer to the attached drawing direction, be not used for limiting the protection domain of the disclosure.Through accompanying drawing, identical element is by identical
Or similar reference represents.When understanding of this disclosure may be caused to cause to obscure, conventional structure or structure will be omitted
Make.And the shape and size of each part do not reflect actual size and ratio in figure, and only illustrate the content of the embodiment of the present disclosure.
In addition, in the claims, any reference symbol between bracket should not be configured to limitations on claims.
Furthermore word "comprising" or " comprising " do not exclude the presence of element or step not listed in the claims.Positioned at member
Word "a" or "an" before part does not exclude the presence of multiple such elements.
Specification and the word of ordinal number such as " first ", " second ", " the 3rd " etc. used in claim, with modification
Corresponding element, itself is not meant to that the element has any ordinal number, does not also represent the suitable of a certain element and another element
Order in sequence or manufacture method, the use of those ordinal numbers are only used for enabling the element with certain name and another tool
The element for having identical name can make clear differentiation.
Particular embodiments described above, the purpose, technical scheme and beneficial effect of the disclosure are carried out further in detail
Describe in detail bright, should be understood that the specific embodiment that the foregoing is only the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution and improvements done etc., the guarantor of the disclosure should be included in
Within the scope of shield.
Claims (10)
1. a kind of GaN base monolithic power inverter, including：
Heterogenous junction epitaxy substrate, including：The hetero-junctions that GaN cushions and thin barrier layer are formed, is produced in the interface of hetero-junctions
Two-dimensional electron gas；
Passivation layer, is formed at heterogenous junction epitaxy substrate, multiple hollow areas between passivation layer be present；
Enhanced power audion, some hollow areas being formed in multiple hollow areas, including：First source electrode,
One drain electrode and first grid, first source electrode, the first drain electrode realize Ohmic contact with thin barrier layer, and the first grid passes through position
Realize and insulate in the first gate dielectric layer below and thin barrier layer；And
Depletion type pliotron structure, other hollow areas being formed in multiple hollow areas, including：Second source electrode,
Two drain electrodes and second grid, second source electrode, the second drain electrode realize Ohmic contact with thin barrier layer, and the second grid passes through position
Insulation is realized with passivation layer or directly contact passivation layer in the second gate dielectric layer below.
2. GaN base monolithic power inverter according to claim 1, in addition to：
Isolated area is injected, is arranged between the first drain electrode and the second source electrode and the first source electrode and the edge of the second drain electrode, from blunt
Change layer to extend in the GaN cushions of heterogenous junction epitaxy substrate.
3. GaN base monolithic power inverter according to claim 1, wherein, the hetero-junctions of the heterogenous junction epitaxy substrate
It is formed on epitaxial substrate, the epitaxial substrate is one kind in following material：Si, SiC, sapphire or GaN wafer.
4. GaN base monolithic power inverter according to claim 1, wherein：
The material of the thin barrier layer is one kind in following material：AlGaN, AlInN ternary alloy three-partalloy or AlInGaN quaternarys are closed
Gold；And/or
The thickness t of the thin barrier layer meets：0 ＜ t≤6nm.
5. GaN base monolithic power inverter according to claim 1, wherein：
The passivation layer is one kind in following material：SiN, SiO2Or SiON；And/or
The thickness of the passivation layer is between 5nm~120nm.
6. GaN base monolithic power inverter according to claim 1, wherein, the hollow area includes successively：First source
Pole open region, first grid open region, the first drain openings area, the second source contact openings area and the second drain openings area；First
Source electrode, the first drain electrode, the second source electrode, the second drain electrode are correspondingly formed in the first source contact openings area, the first drain openings area, the second source
Pole open region, the second drain openings area, realize Ohmic contact；First gate dielectric layer, at least cover the two of first grid open region
Side wall and the portion of the passivating layer of bottom and its both sides, interval be present with source electrode, drain electrode；Second gate dielectric layer, positioned at the second source electrode
And second drain electrode between passivation layer on.
7. a kind of preparation method of GaN base monolithic power inverter as described in any one of claim 1 to 6, including：
Passivation layer is prepared on heterogenous junction epitaxy substrate, wherein, the heterogenous junction epitaxy substrate includes：GaN cushions and thin potential barrier
The hetero-junctions that layer is formed, two-dimensional electron gas is produced in the interface of hetero-junctions；
Etch Passivation, the first source contact openings area, first grid open region, the first drain openings area, the second source electrode is prepared
Open region and the second drain openings area；
The corresponding deposition the in the first source contact openings area, the first drain openings area, the second source contact openings area and the second drain openings area
One source electrode, the first drain electrode, the second source electrode and the second drain electrode, make Ohmic contact；And
The first gate dielectric layer and first grid are made in first grid open region, the passivation between the second source electrode and the second drain electrode
The second gate dielectric layer and second grid are made on layer or only make second grid；Complete GaN base depletion type and reinforced metal
The single-chip integration of insulating barrier semiconductor HEMT (MIS-HEMTs).
8. preparation method according to claim 7, wherein, also comprise the following steps after Ohmic contact has been made：
First drain electrode the second source electrode between and the first source electrode and second drain electrode edge carry out ion implanting isolation.
9. preparation method according to claim 7, wherein, in Etch Passivation, the first source contact openings area, is prepared
In the step of one gate openings area, the first drain openings area, the second source contact openings area and the second drain openings area：
Opened simultaneously with the first source contact openings area, the first drain openings area the first grid open region；Or
Opened according to sequencing, wherein, the first source contact openings area and the first drain openings area first open, or first grid
First open open region.
10. according to the preparation method described in any one of claim 7 to 9, wherein：
The passivation layer with the following method in one kind prepared：MOCVD, LPCVD or PECVD；And/or
The Etch Passivation uses F base plasma etchings, realizes etching from cut-off on the surface of thin barrier layer.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110970498A (en) * | 2018-09-29 | 2020-04-07 | 苏州能讯高能半导体有限公司 | Semiconductor device and preparation method thereof |
| CN111710651A (en) * | 2020-08-20 | 2020-09-25 | 浙江集迈科微电子有限公司 | Integrated GaN device and preparation method thereof |
| CN112345614A (en) * | 2019-08-08 | 2021-02-09 | 中国科学院微电子研究所 | Detector based on gallium nitride-based enhanced device and manufacturing method thereof |
| CN112466941A (en) * | 2020-11-27 | 2021-03-09 | 南方科技大学 | Preparation method of E/D-mode GaN HEMT integrated device |
| CN113053826A (en) * | 2021-03-19 | 2021-06-29 | 厦门市三安集成电路有限公司 | Integrated enhancement mode and depletion mode HEMT device and preparation method thereof |
| CN113823681A (en) * | 2021-08-30 | 2021-12-21 | 瑶芯微电子科技(上海)有限公司 | HEMT device based on grid field plate and double-source field plate and preparation method thereof |
| CN113871477A (en) * | 2021-08-30 | 2021-12-31 | 瑶芯微电子科技(上海)有限公司 | Double-heterojunction HEMT device based on grid field plate and source field plate and preparation method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102938413A (en) * | 2012-11-21 | 2013-02-20 | 西安电子科技大学 | Algan/gan heterojunction enhanced device and manufacturing method thereof |
| CN102368501B (en) * | 2011-10-20 | 2013-11-27 | 中山大学 | Preparation method of Gbased enhanced MOSHFET device |
| CN105355555A (en) * | 2015-10-28 | 2016-02-24 | 中国科学院微电子研究所 | GaN-based enhanced power electronic device and preparation method thereof |
| CN105895680A (en) * | 2015-02-12 | 2016-08-24 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| US20170133368A1 (en) * | 2015-11-10 | 2017-05-11 | Qorvo Us, Inc. | High bandgap schottky contact layer device |
| CN106887454A (en) * | 2017-03-14 | 2017-06-23 | 西安电子科技大学 | GaN base fin grid enhancement device and preparation method thereof |
-
2017
- 2017-11-06 CN CN201711081961.XA patent/CN107887383B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368501B (en) * | 2011-10-20 | 2013-11-27 | 中山大学 | Preparation method of Gbased enhanced MOSHFET device |
| CN102938413A (en) * | 2012-11-21 | 2013-02-20 | 西安电子科技大学 | Algan/gan heterojunction enhanced device and manufacturing method thereof |
| CN105895680A (en) * | 2015-02-12 | 2016-08-24 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| CN105355555A (en) * | 2015-10-28 | 2016-02-24 | 中国科学院微电子研究所 | GaN-based enhanced power electronic device and preparation method thereof |
| US20170133368A1 (en) * | 2015-11-10 | 2017-05-11 | Qorvo Us, Inc. | High bandgap schottky contact layer device |
| CN106887454A (en) * | 2017-03-14 | 2017-06-23 | 西安电子科技大学 | GaN base fin grid enhancement device and preparation method thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110970498A (en) * | 2018-09-29 | 2020-04-07 | 苏州能讯高能半导体有限公司 | Semiconductor device and preparation method thereof |
| CN110970498B (en) * | 2018-09-29 | 2022-07-26 | 苏州能讯高能半导体有限公司 | Semiconductor device and preparation method thereof |
| CN112345614A (en) * | 2019-08-08 | 2021-02-09 | 中国科学院微电子研究所 | Detector based on gallium nitride-based enhanced device and manufacturing method thereof |
| CN111710651A (en) * | 2020-08-20 | 2020-09-25 | 浙江集迈科微电子有限公司 | Integrated GaN device and preparation method thereof |
| CN112466941A (en) * | 2020-11-27 | 2021-03-09 | 南方科技大学 | Preparation method of E/D-mode GaN HEMT integrated device |
| CN113053826A (en) * | 2021-03-19 | 2021-06-29 | 厦门市三安集成电路有限公司 | Integrated enhancement mode and depletion mode HEMT device and preparation method thereof |
| CN113823681A (en) * | 2021-08-30 | 2021-12-21 | 瑶芯微电子科技(上海)有限公司 | HEMT device based on grid field plate and double-source field plate and preparation method thereof |
| CN113871477A (en) * | 2021-08-30 | 2021-12-31 | 瑶芯微电子科技(上海)有限公司 | Double-heterojunction HEMT device based on grid field plate and source field plate and preparation method thereof |
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