JPH0778829A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method of a semiconductor device which can prevent the damage of the semiconductor device in the case of working a fine pattern, regarding the manufacturing method of a semiconductor device containing an insulated-gate field-effect transistor (IGFET) of high level of integration. CONSTITUTION:In the manufacturing method of a semiconductor device containing an insulated-gate field-effect transistor, the following are formed; a gate insulating film 2a on a semiconductor substrate 1, a gate electrode layer 3 facing the substrate 1, in a specified area, via the gate insulating film 2a, a layer insulating film 4, a wiring layer 6 connected with the gate electrode layer 3, a conductive material layer on the wiring layer 6, and a resist layer. By patterning the resist layer, a resist mask 9 containing a wiring pattern is formed with an antenna ratio larger than or equal to 10 to the area of a gate electrode. By applying the resist mask 9 to an etching mask, at least the conductive material layer is subjected to plasma etching. The resist mask 9 is eliminated, and the wiring layer 6 is subjected to plasma etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a highly integrated insulated gate field effect transistor (IGFET).

[0002]

2. Description of the Related Art With the miniaturization of LSIs (Large Scale Integrated Circuits), it is desired to improve pattern transfer accuracy. Since the mask pattern is faithfully transferred to the work layer such as wiring, R
IE (reactive ion etching), ECR (electron cyc
Anisotropic dry etching such as plasma etching is often used. These anisotropic dry etchings use plasma or ions.

The plasma process is likely to be accompanied by electrical stress such as damage due to non-uniformity of plasma (J. Appl. P.
hys. 72 (1992) pp. 4865-4872). In particular, miniaturization and insulated gate field effect transistor (IGFET)
Gate insulating films have become thinner, and often have a thickness of 10 nm or less, and are easily affected and damaged by electrical stress. For example, when a Fowler-Nordheim (FN) tunnel current flows through the gate insulating film, a defect corresponding to the integrated current amount occurs and the threshold voltage is changed. Furthermore, when dielectric breakdown occurs, a short circuit between the gate electrode and the semiconductor substrate occurs.

A gate oxide film having a thickness of 10 nm has a thickness of 10 to 15
There is a high risk of destruction by applying a voltage of V or higher. Potential Vdc on the surface of the workpiece placed in the plasma
Reaches 100 to 1000 V, and it is not easy to suppress the uniformity within 5%.

Therefore, the risk of destroying the gate insulating film by the plasma process is very high. These risks exist not only in patterning the wiring layer but also in contact hole opening and contact hole cleaning by plasma sputtering.

In the past, these damage phenomena have all been attributed to non-uniform electrical or magnetic properties associated with the plasma used. Therefore, the solution has been to generate and use a uniform plasma as a means for preventing damage.

More specifically, it has been proposed to homogenize the plasma potential and homogenize the bias voltage by preventing the position dependence of electron mobility. For example, in a configuration in which a magnetic flux traverses the surface of a workpiece, a configuration has been proposed that prevents the surface vertical component of the magnetic field from changing in the central portion and the peripheral portion.

[0008]

The present inventors have newly found that even if the nonuniformity of the plasma is corrected, the damage is caused by the processing pattern.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent damage to the semiconductor device even when processing a fine pattern.

[0010]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including an insulated gate field effect transistor, which comprises a step of forming a gate insulating film and an electrode layer on a semiconductor substrate. A step of patterning the electrode layer to form a gate electrode layer facing the semiconductor substrate via the gate insulating film in a predetermined area; and a step of forming an interlayer insulating film covering the gate electrode layer, A step of forming a wiring layer connected to the gate electrode layer on the interlayer insulating film, a step of forming a conductive material layer on the wiring layer, and a step of applying a resist layer on the conductive material layer, The resist layer is patterned to form a resist mask including a wiring pattern having an antenna ratio of about 10 or more with respect to an area of a portion of the gate electrode layer facing the semiconductor substrate. A first etching step of plasma-etching at least the conductive material layer using the resist mask as an etching mask, a removing step of removing the resist mask after the first etching step, and at least a gate electrode layer after the removing step. A second etching step of plasma etching a part of the wiring layer connected to the.

The semiconductor device manufacturing method of the present invention is
A method of manufacturing a semiconductor device including a conductive film pattern having a pattern interval of 1 μm or less, comprising a step of forming an electrode layer on a partial surface of a semiconductor substrate via a thin insulating film, and an interlayer insulating film covering the electrode layer. And a step of forming a conductive film connected to the electrode layer on the interlayer insulating film,
A step of forming an insulating mask material layer on the conductive film, a step of applying a resist layer on the insulating film mask material layer, a step of patterning the resist layer, and a step of patterning the insulating mask material layer using the resist layer as a mask. And a step of removing the resist layer and a step of patterning the conductive film by plasma etching using the insulating mask material layer as a mask, the thickness of the insulating mask material layer being a minimum pattern interval of 1
It is set to / 2 or less.

The method of manufacturing a semiconductor device according to the present invention is
When the wiring layer connected to the insulated gate of the insulated gate field effect transistor or the insulating layer thereabove is processed by using plasma with uniform characteristics on the surface of the workpiece, ions that are incident almost perpendicularly to the surface of the wiring layer An rf bias having a frequency of 1 MHz or less is applied to the workpiece so that the electrons and the electrons have almost the same amount.

A method of manufacturing a semiconductor device according to the present invention is
Semiconductor device for simultaneously forming a first wiring layer, which is a wiring layer connected to a gate electrode on a gate insulating film formed on a semiconductor region of the first conductivity type, and a second wiring layer connected to the semiconductor region In the method for manufacturing the above, when patterning the first wiring layer and the second wiring layer, an electrically separated third wiring layer is left therebetween.

[0014]

In the processing of the conductive pattern which is connected to the gate electrode on the thin insulating film and has a high antenna ratio with respect to the intrinsic gate region, the gate structure is damaged even if the plasma is made uniform. By making the material conductive, it is possible to prevent damage to the gate structure. Here, the antenna ratio means the ratio of the exposed area of the conductive pattern to the area of the gate electrode (intrinsic gate region) on the thin insulating film.

This is because if the mask is non-conductive, the imbalance of positive charges and negative charges incident on the conductive layer under the mask immediately causes charge-up of the conductive layer, but the mask becomes conductive. This is considered to be because if it is a property, it is not necessary to balance the charges only with the conductive layer under the mask, and it is sufficient to balance the positive charges and the negative charges in the entire mask and the layer to be processed.

When the antenna ratio is 10 or more and charge-up occurs once, it is almost 10 in the region where the insulation strength is weak.
A current that is more than doubled flows, and the characteristics of the semiconductor device easily change. By balancing the charges, a tunnel current can be prevented and a semiconductor device having desired characteristics can be manufactured.

Even if the mask is non-conductive, damage can be prevented as long as the side surface area is negligible. It is considered that this is because the absolute amount of negative charges incident on the side surface of the non-conductive mask is small. More specifically, if the mask thickness is ½ or less of the minimum pattern interval, the effect of preventing damage becomes great.

It is considered that the conventional uniform plasma has equal amounts of positive and negative charges incident on the plane. However, the uniformity is not guaranteed when the incident direction is taken into consideration. Therefore, it is considered that non-uniformity exists when only the charges vertically incident on the openings provided between the non-conductive masks having a narrow mask interval are considered.

If this non-uniformity is eliminated, positive charges and negative charges are balanced and damage can be prevented. In order to adjust the balance between the positive charges and the negative charges that vertically enter the workpiece from plasma, it is effective to set the frequency of the rf bias to 1 MHz or less. Furthermore, it is effective to apply a divergent magnetic field and an auxiliary mirror magnetic field.

Forming the divergent magnetic field and the auxiliary cusp magnetic field is effective in balancing the electric charges that are vertically incident on the workpiece.

[0021]

[Practical Examples] Conventionally, it has been known that the presence of non-uniformity in plasma in plasma etching is likely to cause damage to an object to be etched.

Such nonuniformity of plasma can be measured by detecting the destruction rate of a MOS diode having a so-called antenna structure or the shift of its flat band voltage.

Here, the antenna structure means a structure in which a structure sensitive to a charged state is electrically connected to a conductive member having a large area exposed to plasma. That is,
When an antenna having a large exposed area receives electric charges from plasma, the electric charges change the electric potential of the structure sensitive to the charged state.

The flat band voltage means the voltage required to drive the band bent by the charges trapped in the insulating layer or the like into a flat state. When a charge having one polarity is injected and trapped in the structure of interest during the plasma process, the flat band voltage changes. If the flat band voltage shift is detected, the MO
The amount of charges trapped in the gate insulating film can be known from the FN tunnel current flowing through the S diode.

When establishing the process conditions, a large number of MOS diode structures having an antenna structure are formed on the surface of the object to be processed, and the change or destruction rate of these flat band voltages is measured to obtain the object to be processed. It is possible to detect the imbalance between the positive charges and the negative charges incident on the surface of the object.

However, the balance between the positive charges and the negative charges thus detected relates to the unit area on the plane, and does not convey information about the incident direction of the incident charges.

The photoresist is usually an insulator, and its aspect ratio tends to increase as the processing pattern becomes finer. Therefore, even if the positive and negative charges incident on the surface of the resist layer are well balanced, if there is a difference in the distribution in the incident direction, the amount of charges incident on the conductive workpiece below the resist layer. Will change.

2A and 2B are a sectional view and a plan view showing the antenna structure. In FIG. 2A, a thick field oxide film 102b is selectively formed on the surface of a semiconductor substrate 101 formed of, for example, p-type Si. The field oxide film 102b is formed so as to surround the active region 108 shown in FIG.

A thin gate oxide film 1 is formed on the surface of the active region 108.
02a is formed, and the gate electrode 103 made of, for example, polycrystalline Si is formed thereon. Gate electrode 103
Extends across the central portion of the active region 108 as shown in FIG. 2 (B) and extends over the field oxide film on both sides thereof.

The gate oxide film is removed on the surface of the active region 108 on both sides of the gate electrode 103 to form source / drain electrodes. SiO 2 to cover the gate electrode 103
The contact hole 1 for exposing a part of the gate electrode 103 is formed with the interlayer insulating film 104 formed of ₂ etc.
05 is formed. A gate wiring layer 106 connected to the gate electrode 103 through the contact hole 105 is formed on the interlayer insulating film 104. The wiring layer 106 is the active layer 1
The gate electrode 103 has an area Af that is at least 10 times as large as the area Ag of the gate electrode 103 on 08.

Semiconductor substrate 101, gate insulating film 102
a, the characteristics of the insulated gate structure formed by the gate electrode 103 are affected by the Fowler-Nordheim (FN) tunnel current flowing through the gate insulating film 102a.

FIG. 2C schematically shows current-voltage characteristics of the MOS capacitor. The horizontal axis shows the voltage applied to the MOS capacitor on a linear scale, and the vertical axis shows the current flowing through the MOS capacitor on a logarithmic scale. A leak current I _L first flows as the applied voltage increases. When the applied voltage reaches a certain value (the electric field in the gate insulating film reaches a certain level of strength), the tunnel current I _FN flows through the gate insulating film. When the applied voltage is further increased, the current rapidly increases at a certain voltage, and the breakdown current I _B
Flows. When the dielectric breakdown current I _B flows, the MOS capacitor is destroyed, but even if this dielectric breakdown current does not flow, if the tunnel current I _FN flows, the characteristics of the MOS capacitor change. The influence of the tunnel current on the MOS capacitor increases in accordance with the amount of current flowing.

When patterning a wiring layer having an antenna structure as shown in FIGS.
When the balance between the positive charge and the negative charge incident on 06 is lost,
Charge-up of the processed layer 106 may occur. The processed layer 106 is electrically connected to the gate electrode 103,
The gate electrode 103 and the wiring layer 106 have a potential difference with respect to the semiconductor substrate 101.

The wiring layer 106 is disposed between the semiconductor substrate 101 and the thick oxide films 102 and 104,
The gate electrode 103 faces the semiconductor substrate 101 via only the thin gate insulating film 102a. Therefore, as the voltage between the semiconductor substrate 101 and the wiring layer 106 increases, a tunnel current flows exclusively between the gate electrode 103 and the semiconductor substrate 101 via the gate insulating film 102a.

The tunnel current flowing through the gate insulating film 102a increases as the ratio (antenna ratio) of the area Af of the wiring layer 106 is larger than the area Ag of the intrinsic gate electrode. Therefore, when a wiring layer having a large antenna ratio is processed, if the balance of incident positive and negative charges is lost, the insulated gate structure easily changes its properties.

FIG. 2D schematically shows a process of processing the gate wiring layer. In the processing of the gate wiring layer, not only a single wiring is processed but also various wirings are often processed simultaneously. A photoresist pattern 110 is formed on the wiring layer 106 formed on the entire surface of the interlayer insulating film 104, and the wiring layer 106 is etched by using the photoresist pattern 110 as an etching mask.

At the beginning of the etching process, the wiring layer 1
Often, any part of 06 (for example, a scribe region) is in electrical contact with the semiconductor substrate 101.
However, the etching rate decreases in the region where the pattern density is high due to the microloading effect. Therefore, even if the etching is completed in the part where the pattern interval is wide, it is still continued in the region where the pattern interval is narrow.

In such a state, as shown in FIG. 2D, the wiring layer connected to the gate electrode 103 is connected to the surrounding wiring and electrically separated from the wiring outside thereof. Occurs. That is, the wiring layer 106 shown in the figure
Are electrically isolated and connected only to the gate electrode 103. In such a situation, when the amount of positive and negative charges incident on the wiring layer 106 is unbalanced, the wiring layer 106 is easily charged up.

The wiring layer 106, and hence the gate electrode 10
When the potential of 3 reaches a certain level or more with respect to the semiconductor substrate 101, a tunnel current starts flowing through the gate insulating film 102a.

In the wiring layer 106 having a flat surface as shown in FIG. 2A, charge imbalance does not occur if the amounts of incident positive charges and negative charges are equal. However,
As shown in FIG. 2D, in the case of the wiring layer covered with the photoresist pattern, if the positive charge and the negative charge that enter the wiring layer 106 through the opening of the photoresist pattern 110 are unbalanced, the charge is charged. Up will occur.

Therefore, even if the amounts of positive and negative charges incident on the plane are equal, if the angular distributions are different, the obliquely incident components are likely to be trapped by the photoresist pattern 110, and are vertically incident on the wiring layer 106. Charges up to the polarity with many components.

In the case of FIG. 2D, the area Af of the wiring layer, which is the reference of the antenna ratio, is the area of the portion exposed in the opening of the photoresist pattern 110. When a wiring layer having a large antenna ratio is processed, an amplified current flows through the gate insulating film 102a, so that the characteristics of the insulated gate structure are easily changed.

FIG. 3 schematically shows the structure of an experimental sample prepared by the present inventors based on such a viewpoint.
FIG. 3 (A) shows a schematic plan view of one unit of the experimental sample, and FIG. 3 (B) shows a partial schematic sectional view thereof.

As shown in FIG. 3A, a conductive pattern 20 is formed on the surface of the semiconductor substrate with an insulating film interposed therebetween. The conductive pattern 20 has a gate portion 20a coupled to the semiconductor substrate through a thin gate oxide film, and a wide antenna portion 20b arranged on the thick oxide film. We have
Based on the above viewpoint, a plurality of resist patterns having different pattern intervals were formed on the conductive pattern 20.

FIG. 3B schematically shows the sectional structure of the experimental sample. An oxide film 2 is formed on the surface of the semiconductor substrate 1. The oxide film 2 is a thin gate oxide film 2a in the gate portion and a thick field oxide film 2b in the other portions.

A conductive pattern 20 as shown in FIG. 3A is formed on the oxide film 2. A resist pattern 21 made of a stripe-shaped insulating resist is formed on the conductive pattern 20. The conductive pattern 20 is separated on the oxide film 2 and is insulated from the semiconductor substrate 1.

A plurality of samples having different aspect ratios of the resist pattern 21 were prepared. More specifically,
A sample with an aspect ratio of 0 without the resist pattern 21, a sample with an aspect ratio of 0.7, and an aspect ratio of about 2
The sample was mainly used. More specifically, the width and interval of the resist pattern were set to about 0.7 μm, and the height was set to 0.5 μm and 1.6 μm.

The gate oxide film 2a surrounded by the field oxide film 2b has a thickness of about 8 nm and an area of 1 × 1 μm.
m, and the area of the antenna portion 20b was set to about 1 × 1 mm. That is, the so-called antenna ratio is 100
It is 10,000.

These samples were put into an antenna structure having no resist pattern and plasma homogenized by a flat band voltage, and the degree of damage was measured. The plasma was ECR plasma, and an rf bias of 2.3 W / cm ² was applied to the substrate.

The sample was exposed to the plasma thus set for about 30 seconds to examine the degree of damage. As shown in the graph of the experimental results in FIG. 4A, when the aspect ratio is 0 without the resist pattern, almost no destruction of the MOS gate oxide film is observed, and the conventional plasma damage can be prevented by uniformization. Have proved. That is, in other words, it can be said that uniform plasma is generated.

However, as the aspect ratio is increased to about 0.7 and about 2.0, the breakdown rate of the gate, that is, the occurrence of damage is remarkably increased. This phenomenon indicates the presence of damage that cannot be prevented by so-called uniform plasma.

As is clear from FIG. 4A, according to the conventional judgment criteria, the damage phenomenon is caused by the plasma having no problem of nonuniformity, and the destruction rate is higher as the height of the resist pattern is higher. It is getting bigger.

If there is no resist pattern, it is considered that positive charges of ions and negative charges of electrons have reached the antenna conductor in equal amounts from the plasma. This explains the conventional idea that no damage occurs in the absence of non-uniformity.

However, when the resist pattern exists, the substrate rf bias accelerates the beam substantially perpendicularly to the substrate, and the incident ions reach the antenna conductor, while the scattered ions are scattered and have a large lateral velocity component. It is considered that a part of the beam hits the resist pattern and cannot reach the antenna conductor.

As a result, it is considered that the positive charges excessively entered the antenna conductor and destroyed the connected MOS diode. It is considered that the degree of this electron shielding becomes stronger as the resist pattern becomes higher, and the experimental result of FIG. 4A can be reasonably explained.

The sample used in this experiment is designed to experimentally clarify that damage is caused when the etching of the wiring layer is non-uniform even if the plasma is uniform. The background is the following experimental findings of the present inventors.

That is, the damage which is a problem in the etching of the wiring layer is large in the portion which does not depend on the over-etching time. Further, damage is unlikely to occur even in the initial stage of etching. These facts indicate that damage is likely to occur during a certain period immediately before the etching end point. Furthermore, this damage was observed only in the pattern in which the wiring interval was narrow.

In the etching of aluminum alloy, there is a so-called microloading effect in which the etching rate decreases in a pattern with a narrow interval. Therefore, when a pattern in which a portion with a narrow wiring interval and a portion with a large wiring distance are present at the same time is etched, conductors remain in the portion with a narrow wiring distance even if etching is completed in the portion with a large wiring distance. Then, the conductor may be connected to the gate electrode.

Since the etching is completed in the portion where the wiring interval is wide, this conductor is often electrically separated from other conductors. Therefore, if there is an imbalance in the amount of charges that enter this conductor, an excessive voltage will be applied to the gate electrode.

When the conductor is spread over the entire surface of the substrate as in the initial stage of etching, the conductor and the substrate are often connected by a scribe line or the like. In such a case, the substrate is kept at the same potential as the conductor, and there is no potential difference above and below the gate insulating film. In such a situation, no damage can occur.

Even if the conductor is not directly connected to the substrate, if the conductor is spread over a wide area,
The potentials of the conductors are averaged, and a large potential difference with the substrate potential is unlikely to occur.

FIG. 4B is a schematic diagram for explaining this situation. In the etching of aluminum alloy, there is a so-called microloading effect in which the etching rate is reduced in a pattern having a narrow mask interval. Therefore, the conductor remains in the portion where the wiring interval is narrow, and the conductor is etched and removed in the portion where the wiring interval is wide.

In such a situation, a state occurs in which some conductors around the gate electrode are connected to each other and are electrically separated from distant conductors. FIG. 4 (B) shows
This situation is shown.

The insulating layer 2 is formed on the semiconductor substrate 1,
The gate electrode layer 3 is formed on the insulating layer 2.
Although the surface of the gate electrode layer 3 is covered with the interlayer insulating film 4, a via hole is formed on a part of the gate electrode layer 3, and the wiring layer 6 is connected through the via hole.

The wiring layer 6 was initially deposited over the entire surface of the substrate, but patterning proceeded by etching using the photoresist 9 as a mask, and in the state shown in the drawing, the portion connected to the gate electrode layer 3 and its portion. Only the wiring layers on both sides are connected to each other.

The pattern interval between the photoresist patterns 9a, 9b, 9c is narrow, and even after the wiring layer 6 disappears, the wiring layer 6 between the photoresist patterns 9a, 9b and 9c remains between the photoresist layers 9a, 9b and 9c due to the microloading effect. There is.

Positive charges 10 of ions and negative charges 11 of electrons are incident on such a wiring layer 6, but the electrons have many lateral components due to scattering. Therefore, many electrons are incident on the side surface of the photoresist layer 9, and as a reaction to this, the positive charges of ions are greater than the charges incident on the wiring layer 6.

Therefore, a large amount of positive charges flow into the gate electrode layer 3 connected to the wiring layer 6, and the gate electrode layer 3 is positively charged. When the potential due to charging exceeds a predetermined value, tunnel current or insulation breakdown discharge through the gate insulating film 2a is started, and the gate insulating film 2a is destroyed.

The experimental results shown in FIG. 4A are considered to explain such a situation. The structure of the experimental sample is configured as shown in FIG. 3 for simplification. The configurations of the three types of samples are shown in more detail in FIG.

FIG. 5A shows the case where the aspect ratio is 0. A gate insulating film 2a and a field insulating film 2b around the gate insulating film 2a are formed on the semiconductor substrate 1, and a gate electrode layer 20 is formed thereon. No photoresist layer is formed on the gate electrode layer 20, and the aspect ratio is 0.

In FIG. 5B, a pattern interval of 0.7 μm and a pattern width of 0.7 are formed on the gate electrode layer 20 having the same structure.
A stripe-shaped resist pattern 21 of μm is formed. The height of the resist pattern is 0.5 μm, and the aspect ratio is about 0.7.

In FIG. 5C, a resist pattern similar to that of FIG. 5B is formed, but the height of the resist pattern is set to 1.6 μm. The resist pattern interval and the pattern width are each 0.7 μm, as in FIG. 5B. Therefore, the aspect ratio is about 2
Becomes

FIG. 5D schematically shows the shape of the gate electrode layer 20 exposed from the resist pattern. It is assumed that ions and electrons are present in a plasma state on such a sample surface, positively charged ions are incident on the surface almost perpendicularly, and negatively charged electrons are incident obliquely.

Then, when the aspect ratio is 0 in FIG. 5A, the same amount of ions and electrons are incident on the gate electrode layer 20, but in the cases of FIGS. 5B and 5C, it is oblique. A part of the electrons incident in the direction enter the side surface of the resist pattern 21 and are trapped there.

On the other hand, the positively charged ions that have passed through the openings on the surface of the resist pattern 21 travel in a substantially vertical direction, and thus enter the gate electrode layer 20 almost as they are. Therefore, the positive charge is larger in the amount of charge incident on the gate electrode layer 20.

As the height of the resist pattern 21 increases, the amount of negative charges trapped on the side surface increases, and the amount of positive charges incident on the gate electrode layer 20 also increases.

As described above, in a fine pattern having a pattern interval of about 1 μm or less, even if the plasma is uniform in the plane, if the movement direction of the electric charge in the plasma is anisotropic, the resist pattern is formed. In the etching of the covered conductive layer, an imbalance in the amount of incident charges occurs.

In the above experiment, a striped pattern was used, but the mechanism that causes excess positive charge due to electron blocking and leads to damage is not limited to such a case. FIG. 6 shows an example of another situation in which damage is recognized by an experiment, and the above experimental results can be analogically applied as the mechanism.

FIG. 6A shows a contact hole etching process. The gate electrode layer 20 is covered with an interlayer insulating film 22, and a resist pattern 24 is formed thereon. In the etching of the contact hole, the etching target is the interlayer insulating film 22, and the etching ends when the wiring layer 20 is exposed.
Are often electrically isolated.

When the gate electrode layer 20 is partially exposed, etching continues, and if there is an imbalance in the charges that enter the gate electrode layer 20 from above, an excessive potential is generated in the gate electrode layer 20. I will end up.

FIG. 6B shows a process of plasma cleaning the contact hole. Immediately before embedding a wiring layer of metal or the like in the contact hole formed by etching the contact hole as shown in FIG. 6A, the inside of the contact hole is cleaned with plasma.

In this situation, the gate electrode layer 20 is exposed in the contact hole, and the periphery of the contact hole is surrounded by the interlayer insulating film 22. When the positive and negative charges entering the gate electrode layer 20 from the upper part of the contact hole are unbalanced, an excessive potential is generated in the gate electrode layer 20, as in the case of FIG.

As described above, it has been found that the semiconductor device is damaged when the insulating material is used as the plasma etching mask and the etching is performed using the plasma in which the positive and negative charges in the plasma have different velocity distributions. . Therefore, as a measure for preventing damage, the method shown in FIG. 1 can be considered.

FIG. 1A shows the case where a conductive material is used as an etching mask. On the surface of the Si substrate 1, S including the gate insulating film 2a and the field insulating film 2b is formed.
An insulating film ₂ such as iO ₂ is formed, and a gate electrode layer 3 is formed thereon. The surface of the gate electrode layer 3 is covered with the interlayer insulating film 4.

A contact hole 5 is formed in the interlayer insulating film 4 and the gate electrode layer 3 is exposed. The wiring layer 6 is connected to the gate electrode layer 3 in the contact hole 5 and is formed on the interlayer insulating film 4.

An amorphous carbon (aC) layer 7 is formed as a conductive mask layer on the wiring layer 6. a
A resist layer is applied on the C layer 7 and patterned to form a resist mask. Using the resist mask as an etching mask, the aC layer 7 is patterned. At least at the end of etching,
The resist layer on the aC layer 7 is removed and the aC layer is exposed.

Since this etching mask has conductivity, all the charges incident on the etching mask can also flow to the wiring layer 6. Therefore, as long as uniform plasma is used, the positive charges and the negative charges incident on the wiring layer 6 and the aC layer 7 can be balanced.

FIG. 1B shows a case where the insulating mask 13 is used as an etching mask, and the thickness thereof is selected as a predetermined condition. The insulating mask 13 is thinner than the openings 8 between the patterns, and more specifically, it is set to ½ or less. Therefore, even if the electron 11 is obliquely incident on the pattern, the probability that the electron 11 is incident on the insulating mask 13 is extremely low.

FIG. 1C shows a case where the plasma condition itself is adjusted so that the positive charge and the negative charge are equal and the light is incident in the vertical direction. Even if the conventional resist mask 9 is formed on the wiring layer 6 and etching is performed, if the ions 10 and the electrons 11 are incident in the same amount in the vertical direction, charge-up of the wiring layer 6 does not occur and damage is prevented. can do.

In order to make equal amounts of ions and electrons incident in the vertical direction, it is effective to first generate a uniform plasma as in the conventional case and further set the rf bias to a low frequency of 1 MHz or less. Furthermore, it is effective to form a cusp magnetic field with the diffusion magnetic field and the auxiliary magnetic field. It is also effective to form a mirror magnetic field using a diffusion magnetic field and an auxiliary magnetic field.

FIG. 1D shows a structure in which the gate electrode or the wiring layer connected to the gate electrode is hard to be electrically separated from the substrate even at the end of etching. Wiring layer 6
Is directly formed on the Si substrate 1 at a substrate contact or the like and constitutes a ground wiring or the like. in this case,
If the gate electrode layer 3 and the wiring layer 6 are separated, damage may occur.

Due to the micro-loading effect, the phenomenon that the etching is not finished in the portion where the pattern interval is narrow and the etching is finished in the portion where the pattern interval is wide is positively utilized. That is, the wiring layer 6 and the gate electrode layer 3 which are directly connected to the substrate by the scribe line or the like are all coupled to each other with a constant narrow pattern interval.

When there is a wide space in the middle, dummy wirings are formed within the space to prevent wide pattern space. Hereinafter, these methods will be described more specifically.

7A to 7D and 8A to 8D.
FIG. 6A is a cross-sectional view showing the main steps of a method for manufacturing a semiconductor device according to an example of the present invention. FIG. 7A shows a step of forming the oxide film 2 on the Si substrate 1. For example, after oxidizing the surface of the Si substrate 1 by about 5 nm, a thickness of about 11
A 5 nm silicon nitride film is deposited and patterned to leave the silicon nitride film only on the regions where the field oxide film is not formed.

If necessary, impurities for forming wells are introduced by ion implantation and thermally diffused. Further, channel stop impurities are ion-implanted. The patterned silicon nitride film is used as an oxidation resistant mask, and the field oxide film 2b having a thickness of about 350 nm is formed by a selective oxidation method by hydrogen combustion oxidation.
To form. Then, the silicon nitride film used as the oxidation resistant mask is removed.

Next, the active region is formed to a thickness of about 1 in dry oxygen.
A 5 nm sacrificial oxide film is formed, and an impurity for controlling the threshold value (VTH) of the MOS transistor is ion-implanted. next,
The sacrificial oxide film is removed with a dilute HF aqueous solution. A gate oxide film 2a having a thickness of about 8 nm is formed on the exposed Si substrate in the active region by oxidation in a dry oxygen atmosphere. In this way
The oxide film shown in FIG. 7A is formed.

As shown in FIG. 7B, a gate electrode layer is formed on the oxide film 2 and patterned to form the gate electrode 3.
To create. More specifically, for example, an amorphous silicon film having a thickness of about 50 nm and a tungsten silicide film having a thickness of about 150 nm are stacked by CVD. Impurities are ion-implanted into the gate electrode film thus formed to form a gate electrode film. A cap oxide film having a thickness of about 60 nm is formed on the gate electrode film by low pressure CVD, and the cap oxide film and the gate electrode film are patterned together to form the gate electrode 3.

After patterning the gate electrode 3, impurities are ion-implanted to introduce the impurities into the source / drain (S / D) regions arranged before and after the gate electrode in the figure, and S
Create a / D area.

When forming the S / D region, first, an LDD region is formed by lightly ion-implanting impurities, an oxide film is grown by low pressure CVD, and anisotropic etching is performed to form a sidewall spacer. And then S / D
The S / D region may be formed by further ion-implanting an impurity for forming a region and activating the impurity by rapid thermal annealing (RTA) at 1000 ° C., for example.

Further, in order to reduce the resistance of the electrode, metal silicide is formed in a self-aligned manner (salicide), if necessary.
You may. For example, a Ti film may be deposited to a thickness of about 30 nm and reacted with Si in the active region by heat treatment to form a TiSi layer.

After forming the gate electrode 3 in this manner, the interlayer insulating film 4 is formed by CVD. As the interlayer insulating film, a composite film of a silicon nitride oxide film formed by plasma CVD and a spin-on-glass (SOG) film or the like can be used.

As shown in FIG. 7C, a resist film 9a is formed on the interlayer insulating film 4 and exposed and developed to form an opening 5a for forming a contact hole. Resist film 9a
Is used as an etching mask to etch the interlayer insulating film 4 to form a contact hole 5 penetrating the interlayer insulating film 4 and exposing the gate electrode 3. After that, the resist film 9a is removed by ashing or the like.

As shown in FIG. 7D, a wiring layer 6 is deposited on the interlayer insulating film 4 having the contact holes 5 formed therein by, for example, sputtering. The wiring layer 6 is formed by stacking an Al layer having a thickness of about 1 μm by sputtering on a barrier metal composed of, for example, a Ti layer having a thickness of about 20 nm and a TiN layer having a thickness of about 50 nm. Wiring layer 6
An amorphous carbon (a-C) film 7 is formed on the above by sputtering or plasma enhanced CVD.

In the structure of FIG. 7D, the Si substrate 1
A field oxide film 2b that defines an active region is formed on the surface of, and a gate oxide film 2a is formed on the channel region of the active region. Gate electrode layer 3 is formed to extend from above gate oxide film 2a to above field oxide film 2b. However, at this stage, the antenna ratio of the gate electrode layer 3 still has a low value.

A source region and a drain region are formed on both sides of the gate electrode 3 in the direction perpendicular to the plane of the drawing, and a MOS transistor is formed. The wiring layer 6 connected to the gate electrode 3 through the contact hole 5 is formed on the entire surface of the substrate and has a large antenna ratio of 10 or more. Even after patterning the wiring layer 6, the antenna ratio has an extremely high value depending on the length of the wiring. The antenna ratio is, for example, 100 or more, sometimes 1000 or more, and sometimes 10,000 or more. The aC layer 7 has a thickness of, for example, about 0.2 μm, and can be regarded as a sufficiently conductive material with respect to charge-up.

Next, as shown in FIG. 8A, a resist layer 9 is applied on the aC layer 7, and exposed and developed to form a resist pattern. The resist pattern has a minimum pattern interval of about 0.8 μm.

As shown in FIG. 8B, using the resist pattern 9 as an etching mask, the aC layer 7 is selectively etched by plasma containing CF ₄ . a
-After the etching of the C layer 7, the wiring layer 6 of aluminum alloy is etched by about 0.9 μm with plasma containing chlorine.

At this stage, the wiring layer 6 remains about 0.1 μm even in the etched portion, and maintains the connected state on the substrate 1. Therefore, even if the positive charge and the negative charge that locally enter the wiring layer 6 are unbalanced, the potential of the entire wiring layer 6 is kept stable.

After etching most of the wiring layer 6, the resist layer 9 is removed by plasma downflow of oxygen. The oxygen plasma downflow has excellent etching selectivity, and can etch the resist layer 9 and leave the aC layer 7 without etching.

Next, as shown in FIG. 8C, the wiring layer 6 is continuously etched using the aC layer 7 as an etching mask. For example, etching of the wiring layer 6 is completed with plasma containing chlorine.

In the state shown in FIG. 8C, the etching mask covering the wiring layer 6 is made of the conductive aC layer 7
Therefore, the charges incident on the aC layer 7 can also flow to the wiring layer 6. If the uniformity of plasma is maintained, no charge is accumulated in the wiring layer 6 and the gate electrode layer 3.

After the completion of etching the wiring layer 6, the aC layer 7 is removed using oxygen plasma. FIG. 8D shows a state of the wiring layers 6a and 6b which have been etched in this way.

In the etching process shown in FIG. 8B, the electrons incident on the resist layer 9 are blocked, so that an imbalance in the amount of charges incident on the wiring layer 6 and the gate electrode layer 3 may occur. Since the wiring layer 6 is connected over the entire surface of the substrate, the local imbalance is averaged and neutralized as a whole.

For this reason, the etching shown in FIG. 8B does not cause damage. However, when the etching of the wiring layer 6 is completed in the portion where the mask interval is wide, the wiring layer 6 is separated by each pattern, and charge-up occurs. Therefore, the etching of FIG. 8B needs to be stopped before the wiring layer 6 is divided.

At the end of etching, the state shown in FIG. 8C is obtained. Therefore, even if electrons are incident on the aC layer 7 from the side surface, the electrons pass through the aC layer 7 and reach the wiring layer 6. Reached
Ions that enter the wiring layer 6 are neutralized.

As described above, by using the conductive aC layer as the auxiliary mask for etching, it is possible to prevent the insulating mask from being damaged by electron blocking. Note that a
The -C layer was sputtered under the conditions of 10 mTorr and 1.5 kW to grow to a thickness of about 0.5 μm, and its resistivity was measured to be about 0.25 Ωcm.

The current due to charged particles from the plasma is 1
It is about 0 mA / cm ² , which is 1 even considering the instantaneous maximum value.
It is considered to be about A / cm ² . Therefore, when the aC layer having such a resistivity is used as a mask, the film thickness is 1
Even if it is μm, the potential difference in the film thickness direction is 25 μV at best,
It can prevent damage sufficiently.

Further, in order to prevent the gate insulating film from being damaged, it suffices that there is no potential difference on the order of 1 V. Therefore, even if it is a conductive film having a resistivity of about 10 ⁴ Ωcm or less, it is used at a thickness of 1 μm. For example, it can be used as a conductive mask.

Incidentally, by reducing the thickness of the resist pattern,
A method may be considered in which the resist pattern disappears during etching and the conductive pattern is automatically exposed, but this is not preferable from the viewpoint of maintaining pattern accuracy.

That is, during etching, lateral etching occurs at the upper end of the etching mask, and so-called facets occur. If etching is continued until the resist pattern disappears, the facets recede and the resist pattern changes.

In FIG. 8, the main part of the etching, particularly the first half, was etched using a resist mask as an etching mask. However, when the conductive mask has a sufficient thickness, the etching is started. It is also possible to remove the resist mask before.

FIG. 9 shows a method of manufacturing a semiconductor device according to another embodiment of the present invention. In FIG. 9 (A), FIG.
As in the case of (A), a is placed on the wiring layer 6 of aluminum alloy or the like.
The -C layer 7 is formed. In the present embodiment, a-
The thickness of the C layer 7 is set to about 0.7 μm. The structure of the other parts is similar to that of FIG.

As shown in FIG. 9B, using the resist mask 9, the aC layer 7 is selectively etched by plasma containing CF ₄ . After that, the resist mask 9 is removed by oxygen plasma downflow. Figure 9
(B) shows this state.

Next, as shown in FIG. 9C, the aluminum alloy wiring layer 6 is etched by plasma containing chlorine using the aC layer 7 as an etching mask. In this etching, since the etching mask is conductive,
The electrons incident on the side surface of the aC layer 7 are also immediately transmitted to the wiring layer 6 and can be neutralized with the ions incident on the wiring layer 6.

If the uniformity of plasma is maintained, a-
The amounts of the positive charges and the negative charges that are incident on the entire C layer 7 and the wiring layer 6 are almost the same, and a good balance of charges is maintained. Therefore, damage is unlikely to occur.

As shown in FIG. 9D, after the wiring layer 6 is etched, the aC layer 7 is removed by plasma containing oxygen. If a plasma downflow of oxygen is used for removing the resist on the aC layer, the etching rate of the aC layer can be slowed down, which is suitable for selective etching. Furthermore C
Addition of F ₄ increases the resist ashing rate.

The damage due to the plasma etching is due to the existence of an insulating resist mask on the electrically isolated conductive layer, and the electrons incident on the resist are trapped there.

If the etching mask for etching can be formed with a sufficiently thin thickness, the amount of electrons incident on the side surface of the etching mask is also relatively reduced and the degree of damage is reduced.

10A to 10C show a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 10 (A)
In the same manner as in the above-described embodiment, the insulating film 2 is formed on the surface of the Si substrate 1, and the gate electrode layer 3 and the interlayer insulating film 4 are formed on the insulating film 2. Interlayer insulating film 4 and opening 5
Having a thickness of 1 μm, for example, on the gate electrode layer 3 exposed by
The wiring layer 6 formed of the aluminum alloy is deposited.

On the wiring layer 6, for example, a thickness of about 0.3 μm
A SiO ₂ film 13 of m is formed by plasma CVD. A resist layer is applied on the SiO ₂ film 13 to form a resist pattern 9 having a minimum mask interval of 0.8 μm.

Using the resist pattern 9 as an etching mask, the SiO ₂ film 13 is selectively etched by plasma containing CF ₄ . After etching the SiO ₂ film 13, the resist pattern 9 is removed using oxygen plasma. When the resist is removed and the aC layer is left, it is preferable to use plasma downflow with good selectivity, but this resist removal step may be performed by simple oxygen plasma because the base is SiO ₂ .

FIG. 10B shows a state in which the resist pattern has been removed. An etching mask 13 of a SiO ₂ film is formed on the wiring layer 6. Considering the mask opening, the height of the mask is about 0.3 μm while the opening width is about 0.8 μm, and the area exposed in the opening is the area of the wiring layer 6 of the SiO ₂ film 13. Compared to the area of
Remarkably large.

As shown in FIG. 10C, the wiring layer 6 of aluminum alloy is etched with plasma containing chlorine using the SiO ₂ film 13 as a mask. Since the uniformity of plasma is guaranteed on the upper surface of the SiO ₂ film 13, the amounts of incident positive charges and negative charges are equal and the charges are neutralized.

Regarding the electrons and ions incident on the side surface of the SiO ₂ film 13, the balance of charges is not guaranteed, but Si
Since the O ₂ film 13 is thin, the imbalance of generated charges is small. Therefore, the imbalance between the positive charges and the negative charges incident on the wiring layer 6 below the SiO ₂ film 13 is also reduced.

It is considered that the electron shielding is reduced by reducing the height of the mask, and the height of the opening itself is reduced, so that the microloading effect is also reduced.

FIG. 11 is a schematic sectional view of a plasma etching apparatus for explaining plasma etching according to another embodiment of the present invention. The airtight plasma chamber 31 is provided with a gas introduction port 32 and an exhaust port 33. The gas inlet 32 is connected to the etching gas source, and the exhaust port 3
3 is connected to the exhaust device.

A plasma generating chamber 35 is connected above the plasma chamber 31, and the microwave introducing pipe 3 is connected.
4 and an airtight window. Plasma generation chamber 3
A main coil 36 is arranged around 5 and a divergent magnetic field can be formed in the plasma chamber 31 and the plasma generation chamber 35.

By introducing a microwave into the plasma generation chamber 35 from the microwave introduction pipe 34 and generating a magnetic field by the main coil 36, ECR plasma having a desired shape can be generated in the plasma generation chamber 35. . The plasma moves into the plasma chamber 31 and collides with the substrate arranged on the susceptor 41.

A ring-shaped outer coil 38 and inner coil 39 are arranged below the susceptor 41. Further, the susceptor 41 is connected to the rf bias source 42.

Using such a divergent magnetic field type ECR plasma etching apparatus, conditions under which the amounts of ions and electrons moving in the direction perpendicular to the substrate were equal were obtained. Specifically, a sample on which a dense striped pattern having a pattern interval of 0.8 μm was formed was placed as a substrate, and the occurrence of damage was detected.

A large number of MOS capacitors with antennas having an antenna area ratio of 10 ⁶ were formed on the substrate surface, and the aluminum alloy of the antenna conductor was etched with Cl ₂ + BCl ₃ gas at a pressure of 0.6 Pa. Table 1 summarizes the occurrence of damage in the divergent magnetic field type ECR plasma device.

The rf bias frequency is typically 13.
Using two types of 56MHz and 400kHz, the coil 38
The current flowing through the coil 39 was changed. The coil 38 is
A cusp magnetic field that is opposite to the magnetic field formed by the main coil 36 is generated, and the coil 39 generates a mirror magnetic field that has the same direction as the magnetic field generated by the main coil 36.

[0143]

[Table 1]

As is clear from the results shown in the table, when the rf bias frequency is set low, damage is reduced and good results are obtained. Even if the rf bias frequency is high, the damage is suppressed depending on the magnetic field conditions of the coils 38 and 39. Such condition dependence is due to the threshold Vth of a MOS transistor having a similar antenna structure.
The same tendency was obtained in the evaluation by.

As described above, the damage caused here is caused by the fact that it is difficult for electrons to reach the conductor between the antenna patterns generated by the microloading effect, and the positive charges of ions become excessive. it is conceivable that.
Since the microloading effect basically did not change even if the frequency was lowered, it is considered that the movement state of the electrons changed due to the change in frequency.

That is, the frequency of the substrate bias is set low,
It is considered that, by lowering the frequency to 1 MHz or less, electrons are accelerated toward the substrate at least in the vicinity of the pattern, and the blocking of the resist pattern is reduced.

The divergent magnetic field type ECR etching apparatus used here does not cause plasma nonuniformity according to the conventional definition even when the rf bias is set to 13.56 MHz.

It is considered that the same tendency holds when the helicon wave plasma is used, the inductively coupled plasma is used, the trans coupled plasma is used, and the DECR plasma is used.

When the substrate is exposed to the plasma from such a high-density plasma source and rf power is applied under the substrate for processing, the bias frequency is set to about 1 MHz or less to suppress damage. It is thought that it can be done.

FIG. 12 is a schematic sectional view of a plasma etching apparatus for explaining plasma etching according to another embodiment of the present invention. In this plasma etching apparatus, the outer auxiliary coil 38a and the inner auxiliary coil 3 are provided above the plasma chamber 31 and outside the main coil 36.
9a is arranged. Other configurations are similar to those of the etching apparatus shown in FIG.

Using the divergent magnetic field type ECR plasma etching apparatus shown in FIG. 12, conditions under which the amounts of ions and electrons moving in the direction perpendicular to the substrate were equal were obtained. Specifically, a large number of samples each having a stripe pattern with a pattern interval of 0.8 μm were formed on a substrate, and etching was performed to detect damage. The antenna ratio of the sample was set to 10 ⁶ as in the above-mentioned examples.

The aluminum alloy of the antenna conductor was etched with Cl ₂ + BCl ₃ gas having a pressure of 0.53 Pa. The bias frequency of the rf bias source 42 is 400 k
The frequency was set to Hz, and the currents passed through the outer coil 38a and the inner coil 39a were changed. The current that forms the mirror magnetic field in the same direction as the magnetic field formed by the main coil 36 is "+", and the direction of the current that forms the cusp magnetic field in the opposite direction is "-".

Table 2 collectively shows the results of the experiment.

[0154]

[Table 2]

As is clear from the results shown in Table 2, when the outer coil 38a and the inner coil 39a generate a mirror magnetic field in the same direction as the magnetic field formed by the main coil 36,
Damage is reduced and good results are obtained. Under the preconditions shown in the table, plasma nonuniformity according to the conventional definition does not occur. Therefore, it is considered that the generated damage is caused by the fact that electrons are hard to reach the conductor between the antenna patterns generated by the microloading effect and the positive charges of the ions become excessive. Auxiliary coil 38
The microloading effect basically did not change depending on the currents flowing through a and 39b. Therefore, it is assumed that the amount of ions and electrons moving in the direction perpendicular to the substrate at least in the vicinity of the pattern becomes equal due to the formation of the mirror magnetic field. Conceivable.

A current of 20 A is applied only to the inner coil in the same direction as the main coil, and the rf bias source is set to 13.56.
When it was set to MHz, damage occurred. FIG. 13 is a plan view for explaining a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 13A shows a wiring pattern to be created. The wiring 51 is connected to the gate electrode and represents a wiring group having a large antenna ratio. The wiring 52 is a power wiring and is connected to the semiconductor substrate or the well. No wiring is required between the wiring 51 and the wiring 52 on the integrated circuit to be created. Therefore, the wiring 51 and the wiring 52
Wide gaps occur between.

In such a case, according to the conventional technique, the wide space between the wiring 51 and the wiring 52 is easily removed in the etching process, and even when the etching is completed, the etching in the wiring group 51 is microscopic. Does not end due to loading effects.

In such a case, the wiring group 51 and the wiring 52
Interpolation or a dummy pattern 53 is provided between the patterns to keep the intervals between the patterns as uniform as possible. More specifically,
The interpolation pattern 53 is arranged so as to have an interval equal to the minimum pattern interval of the wiring group 51.

When such a pattern is etched,
Each interval of the wiring group 51, the interpolation pattern 53, and the wiring group 5
Since the interval between 1 and the interval between the interpolation pattern 53 and the power supply wiring 52 are substantially equal, the same degree of microloading effect occurs and the etching progresses uniformly. Therefore, it is possible to prevent the wiring layer from being partially cut and excessive charges from flowing into the gate electrode.

FIG. 13B shows a case where the signal wiring 54 exists between the wiring group 51 having a large antenna ratio and the power supply wiring 52, and a relatively large area is arranged on both sides of the signal wiring 54.

Also in this case, the interpolation patterns 53a and 53b are provided in the regions on both sides of the signal wiring 54, and the space portions on both sides of the interpolation patterns 53a and 53b are substantially equal to the pattern interval in the wiring group 51 having a large antenna ratio. To set.

As described above, by forming the patterns having the uniform minimum pattern intervals by inserting the interpolation patterns, the microloading effect is uniformly generated, and the wiring group 51 having a large antenna ratio is separated from the power wiring 52. It can be near the end of etching. Therefore, the nonuniformity of the accumulated charge generated in the gate electrode is corrected, and the damage is suppressed.

The embodiment described above is particularly effective when forming a wiring layer having a high antenna ratio. FIG. 14 shows an example of a circuit configuration in which the antenna ratio tends to be high. FIG. 14A is an equivalent circuit of a NAND circuit. A 2-input NAND circuit is connected between the power supply wiring V _DD and the ground wiring V _SS . Two p-channel MOS transistors Qp1 and Qp
The second source is connected to the power supply wiring V _DD , and the drains are commonly connected. The n-channel MOS transistors Qn1 and Qn2 connected in series are connected to this drain, and the source of Qn1 is connected to the ground wiring V _SS .

The wiring of the input signal IN1 is p channel MO.
The wiring of the other input signal IN2 is connected to the gate electrodes of the S transistor Qp1 and the n-channel MOS transistor Qn1 and to the gate electrodes of the p-channel MOS transistor Qp2 and the n-channel MOS transistor Qn2.

The output signal OUT is derived from the interconnection point between the drains of the two p-channel MOS transistors Qp1 and QWp2 and the n-channel MOS transistor Qn2.

Such a logic circuit receives an input signal from the preceding logic circuit. The logic circuit of the previous stage does not always exist close to each other, and the input signal wiring becomes extremely long in some cases. In particular, microprocessors, ASICs
(Application specific IC), ASSP (applicatio
n specific standard product), gate arrays, etc.

In a general-purpose memory device, at the time of designing, the antenna ratio is inspected to change the element layout and wiring, and it is possible to take protective measures such as lowering the antenna ratio and inserting a protective element. This is due to the relatively low degree of automation of design work.

On the other hand, in the logic circuit device, automation by CAD is advancing from function to logic design, gate level design, and layout design. here,
Even if the antenna ratio is inspected, changing the wiring and inserting the protective element entails a large increase in design cost. Therefore, in the logic circuit device, it is difficult to take damage countermeasures by changing the device design.

FIG. 14B shows the NAND of FIG. 14A.
It is a top view which shows the structural example of a circuit. An n-type well 61 for forming a p-channel MOS transistor and an n-channel MO
The p-well 62 for forming the S transistor is formed close to each other. Gate wires 63 and 64 are arranged on the n well 61 and the p well 62 so as to penetrate therethrough.

Ions are implanted using the gate wirings 63 and 64 as masks to form p-type source regions Sp1 and Sp2 and p-type drain region Dp in the n-well 61. In the p-well 62, the gate wiring 63,
By ion implantation using 64 as a mask, an n-type source region Sn1, a drain region Dn1 and a source / drain region S / Dn are formed.

Wirings 65 to 70 are formed as a first wiring layer on this structure. After forming an interlayer insulating film covering the first wiring layer and forming a contact hole, a second insulating film is formed.
A wiring layer is formed. The electrodes 71 to 74 are wirings formed by the second wiring layer. Further, an interlayer insulating film is formed so as to cover the second wiring layer, and a contact hole is formed therein. A third wiring layer is formed on the second wiring layer.
The wirings 75 to 77 represent the third wiring layer.

For example, when forming the first wiring layer after forming the gate electrodes 63 and 64, the electrodes 67 and 68 are formed in a state of being connected to the gate electrodes 63 and 64. In the case shown, the antenna ratio is not so high at this stage. However, when forming the second wiring layer, the wirings 72 and 73 have an extremely long length depending on the design.
When making the wirings 72 and 73, the antenna ratio is the gate electrode 6
It depends on the exposed surface area of the wires 72, 73 to the 3, 64 intrinsic gate regions. Further, until the wirings 72 and 73 are separated, the connected wiring region also plays a role of effectively increasing the antenna ratio.

In addition, when the third wiring layer is formed, the wiring 75,
76 is connected to the gate wirings 63 and 64 via the wirings 72 and 73. It is highly possible that a wiring having a high antenna ratio is also formed when the wiring layer is formed. The wiring 77 also causes an increase in the antenna ratio.

FIG. 15 is a sectional view schematically showing the structure of such a multilayer wiring. The structure up to the first wiring layer 106 is formed by a structure similar to that shown in FIG.
An interlayer insulating film 115, a second wiring layer 117, an interlayer insulating film 119, and a third wiring layer 120 are formed on this. The third, second and first wiring layers 120, 117 and 106 are connected to the gate electrode. In this way, the above-described embodiment is particularly effective when a logic circuit is created.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example,
The gate electrode of the MOS transistor or the wiring layer connected to the gate electrode is not only made of polycrystalline Si, but also metal such as refractory metal polycide (for example, a stack of polycrystalline Si and a refractory metal (for example, W) silicide), silicide, or the like. , T
It can also be formed by iN or the like. Of course, amorphous Si may be used during the manufacturing process.

The etching of a-C is carried out by using CF ₄ , C
It can be performed using an etching gas such as l ₂ or BCl ₃ . Etching of Al and Al alloy is C
It can be performed using a gas containing Cl such as l ₂ and HCl. Further, the etching of the resist and a-C is performed with O ₂
Can be performed by etching using. The plasma etching can be performed using various plasmas such as rf plasma and μ wave plasma.

The case where amorphous carbon is used as the conductive mask has been described, but when the wiring layer is Al, W can be used as the conductive mask and Br-based gas can be used as the etchant.

When the wiring layer is W, Al, TiN or the like can be used as the conductive mask and F-based gas can be used as the etchant. The same combination is possible when the wiring layer is W silicide or polycide. The combination of the wiring layer and the conductive mask should have high etching selectivity and have sufficient conductivity for the mask.

The case where the pattern interval is 0.7 μm and 0.8 μm has been described. However, when the pattern interval is about 1 μm or less, a remarkable microloading effect occurs, so that the present invention is applied. it can.

It will be apparent to those skilled in the art that other various modifications, improvements, combinations, and the like can be made.

[0182]

As described above, according to the present invention,
Damage caused by plasma can be prevented in etching processing of a dense wiring pattern, formation of contact holes, cleaning of the inside of the contact holes, and the like.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining the basic concept of the present invention.

FIG. 2 is a sectional view, a plan view and a graph for explaining an antenna structure and a tunnel current.

3A and 3B are a plan view and a cross-sectional view for explaining an experimental sample.

FIG. 4 is a graph and a cross-sectional view for explaining an experimental result and an analysis.

5A and 5B are a cross-sectional view and a plan view showing experimental conditions and their analysis.

FIG. 6 is a cross-sectional view showing another situation in which experimental results can be applied.

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 11 is a schematic sectional view of a plasma etching apparatus for explaining an embodiment of the present invention.

FIG. 12 is a schematic sectional view of a plasma etching apparatus for explaining an embodiment of the present invention.

FIG. 13 is a plan view of a wiring pattern for explaining an example of the present invention.

FIG. 14 is an equivalent circuit diagram and a configuration diagram of a NAND circuit suitable for use in an embodiment of the present invention.

FIG. 15 is a schematic cross-sectional view showing the structure of a multilayer wiring semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Insulating film 2a Gate insulating film 2b Field insulating film 3 Gate electrode layer 4 Interlayer insulating film 5 Contact hole 6 Wiring layer 7 a-C layer 8 Inter-pattern opening 9 Resist mask 10 Ion 11 Electron 13 Insulating mask 20 Conductivity Pattern 20a Gate part 20b Antenna part 21 Resist pattern 22 Interlayer insulating film 24 Resist film 31 Chamber 36 Main coil 38, 39 Coil 42 rf bias source 51 (Large antenna ratio) Wiring group 52 Power supply wiring 53 Interpolation pattern 54 Signal wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/336 7514-4M H01L 29/78 301 Y (72) Inventor Masaaki Aoyama Kozoji, Kasugai City, Aichi Prefecture 2-Chome 1844-2 within Fujitsu VIELS Co., Ltd.

Claims (15)

[Claims] 1. A method of manufacturing a semiconductor device including an insulated gate field effect transistor, the method comprising: forming a gate insulating film and an electrode layer on a semiconductor substrate; patterning the electrode layer to form a predetermined area. Forming a gate electrode layer facing the semiconductor substrate via a gate insulating film, forming an interlayer insulating film covering the gate electrode layer, and insulating the wiring layer connected to the gate electrode layer with the interlayer insulating film. Forming on the film, forming a conductive material layer on the wiring layer, applying a resist layer on the conductive material layer, patterning the resist layer to form the semiconductor of the gate electrode layer Forming a resist mask including a wiring pattern having an antenna ratio of about 10 or more with respect to the area of the portion facing the substrate; and etching the resist mask. A first etching step of plasma etching at least the conductive material layer as
A method of manufacturing a semiconductor device, comprising a removing step of removing the resist mask after the etching step, and a second etching step of plasma-etching at least a part of the wiring layer connected to the gate electrode layer after the removing step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating layer is a plurality of insulating layers with another wiring layer interposed therebetween. 3. The semiconductor device according to claim 1, wherein the first etching step is etching of a conductive material layer, and the second etching step is etching of the wiring layer using the conductive material layer as a mask. Manufacturing method. 4. The semiconductor device according to claim 1, wherein the first etching step is etching of the conductive material layer and the main portion of the wiring layer, and the second etching step is etching of the remaining portion of the wiring layer. Manufacturing method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material layer is made of carbon. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the removing step is performed by downflow of oxygen plasma. 7. A method of manufacturing a semiconductor device including a conductive film pattern having a pattern interval of 1 μm or less, wherein a step of forming an electrode layer on a partial surface of a semiconductor substrate via a thin insulating film, the electrode layer A step of forming an interlayer insulating film covering the
Forming a conductive film connected to the electrode layer on the interlayer insulating film, forming an insulating mask material layer on the conductive film, and applying a resist layer on the insulating film mask material layer, It includes a step of patterning the resist layer, a step of patterning the insulating mask material layer using the resist layer as a mask, a step of removing the resist layer, and a step of patterning the conductive film by plasma etching using the insulating mask material layer as the mask. A method of manufacturing a semiconductor device, wherein the thickness of the insulating mask material layer is set to be 1/2 or less of a minimum pattern interval. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the interlayer insulating film has a contact hole exposing the electrode layer. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the interlayer insulating layer is a plurality of insulating layers with another wiring layer interposed therebetween. 10. When a wiring layer connected to an insulated gate of an insulated gate field effect transistor or an insulating layer thereabove is processed by using plasma having uniform characteristics on the surface of a workpiece, the wiring layer is substantially perpendicular to the surface of the wiring layer. Frequency of 1MHz or less so that ions and electrons incident on
A method of manufacturing a semiconductor device, wherein an f bias is applied to a workpiece. 11. The method of manufacturing a semiconductor device according to claim 10, further comprising applying a divergent magnetic field and a mirror magnetic field whose magnetic flux density gradually decreases toward the workpiece. 12. A cusp is generated so that plasma is generated under a divergent magnetic field whose magnetic flux density gradually decreases toward the workpiece, and the ions and the electrons that are substantially vertically incident on the surface of the workpiece are approximately equal in amount. A method for manufacturing a semiconductor device, wherein a magnetic field is applied to etch a workpiece. 13. A first wiring layer, which is a wiring layer connected to a gate electrode on a gate insulating film formed on a semiconductor region of the first conductivity type, and a second wiring layer connected to the semiconductor region. A method of manufacturing a semiconductor device, which is produced at the same time, wherein when electrically patterning the first wiring layer and the second wiring layer, an electrically isolated third wiring layer is left therebetween. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the distance between the third wiring layer and the first and second wiring layers is selected to be substantially equal to the minimum pattern distance in other portions. 15. A semiconductor substrate, an insulated gate structure formed on the semiconductor substrate, an interlayer insulating film covering the insulated gate structure, and a first wiring formed on the interlayer insulating film and connected to the gate structure. And a second wiring arranged apart from the first wiring, and an interpolating wiring which is formed between the first wiring and the second wiring with a substantially equal interval and is not used as a wiring. A semiconductor device having a wiring layer including a region.