JP2000173980A - Dry etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dry etching method whereby a wiring pattern can be formed with ensuring a sufficient remaining quantity of resist, without giving damage to a base in manufacturing a semiconductor device. SOLUTION: The etching method comprises steps of forming a resist on a conductor layer, patterning the resist after the exposure and development of the resist, applying a first etching to the conductor layer through the resist used as a mask to remove the conductor layer at regions with relatively wide pattern spacings, executing a second plasma etching in the condition that the straight advancing properly of the ion beam is lower than that in the first plasma etching, thereby removing the conductor layer at regions with relatively narrow pattern spacings, and removing the resist.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a dry etching method for forming a pattern in the manufacture of a semiconductor device, and more particularly to a dry etching method capable of performing etching without damaging a base.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, Al-based wiring such as aluminum (Al) or an Al alloy, or a titanium (Ti) -based metal layer forming a barrier layer or an adhesion layer serving as a base of an Al-based wiring is used. The patterning is usually performed by dry etching using a resist as a mask.
Dry etching of a metal wiring layer including a barrier layer or an adhesion layer has a high etching selectivity to a resist,
In addition, it is necessary to perform the etching under the etching condition in which the plasma does not damage the base.

One type of plasma etching apparatus that performs etching by generating high-density plasma is a magnetic field microwave plasma etching apparatus (hereinafter, referred to as an ECR etching apparatus). When dry etching is performed using an ECR etching apparatus, a very limited region where the ion current density is highest in the plasma and the directionality of ions is uniform is generated. This area is the ECR area (or ECR area)
Position). The position where the ECR region is formed is uniquely determined by the device configuration, the microwave output, the position of the solenoid coil for generating the magnetic field, the magnetic flux density, and the like.

[0004] Etching using an ECR etching apparatus usually involves a distance (EC) between a substrate (wafer) and an ECR region.
(R point) is kept constant. For example, in order to pattern the wiring layer, etching on the wiring layer and over-etching for eliminating non-uniformity of the surface to be etched and flattening the surface are performed. In many cases, the etching conditions are changed and the distance between the substrate and the ECR region is not changed.

Hereinafter, a general method for forming an Al wiring will be described by taking as an example a case where an Al wiring is formed on an interlayer insulating film. First, for example, CVD (c) is formed on a semiconductor substrate on which impurity diffusion regions such as source / drain regions are formed.
chemical vapor deposition)
An interlayer insulating film made of silicon oxide or the like is deposited by a method. An interlayer insulating film made of silicon oxide and A
A Ti / TiN (titanium nitride) laminated film functioning as an adhesion layer for preventing delamination from the wiring or a barrier layer for preventing compatibility between silicon and Al is formed. The formation of the Ti / TiN laminated film is performed by, for example, sputtering or metal CVD.

A wiring layer made of Al or an Al alloy is formed on the Ti / TiN laminated film by, for example, sputtering. After applying a resist on the entire surface of the Al wiring layer, the resist is exposed and developed by a lithography technique, and a wiring pattern is transferred to the resist. After dry etching is performed on the Al wiring, the TiN layer, and the Ti layer using the resist as a mask, the resist is removed by, for example, an ashing process using oxygen plasma. Through the above steps, an Al wiring is formed.

[0007]

However, according to the above-mentioned conventional dry etching method, when the distance between the substrate and the ECR region is short, the underlying substrate of the wiring layer is damaged by the electron shading effect or the microloading effect. There is a problem of being given. The electronic shading effect and the microloading effect will be described with reference to FIG. In FIG. 6, the semiconductor substrate 1
An element isolation region (LOCOS) 2 is formed on the surface of
A gate electrode 4 made of, for example, polysilicon is formed on an active region separated from the periphery by the OCOS 2 via a gate insulating film 3.

A contact hole 6 connected to the gate electrode 4 is provided in the interlayer insulating film 5 covering the entire surface. The contact hole 6 is provided above the interlayer insulating film 5 and in the contact hole 6 via a barrier layer or an adhesion layer (not shown). An Al layer 7 serving as an upper wiring is formed. As shown in FIG. 6A, the Al layer 7 is etched using the resist 8 as a mask. This etching is performed by plasma etching using chlorine gas or the like. When the frequency of a high-frequency power supply for generating plasma is high (2 MHz or more), plasma damage occurs to the base due to the electron shading effect.

[0009] The electron shading effect occurs due to the difference in the behavior of electrons and ions in gas plasma. The mobilities of positive ions and electrons under a high-frequency electric field are significantly different, and electrons having higher mobilities reach the electrode earlier.
Therefore, the electrode is negatively charged (self-bias voltage), and an ion sheath for accelerating positive ions is formed on the electrode surface.

As a result, the ions are incident on the etching surface with the energy of the potential difference of the self-bias voltage in addition to the plasma potential, and are almost perpendicular to the wafer. On the other hand, since the electrons also collide with the side wall of the pattern, the side wall of the resist pattern is negatively charged as shown in FIG. This negative charge forms an electric field that acts as a barrier to the electrons. Therefore, the electrons are decelerated by the electric field near the electrodes and rebounded, and cannot reach the inside of the pattern, so that only ions enter between the Al wirings 7.

In the etching for forming a pattern, the etching rate is not uniform over the entire surface, and the etching rate changes depending on the density of the pattern. The etching rate is relatively high in a region where the pattern interval is wide, and the etching rate is relatively low in a region where the pattern interval is narrow and the pattern is densely formed. Therefore, as shown in FIG. 6B, there is a state where the Al wiring 7 'remains in the region where the pattern interval is narrow (microloading effect) even if the etching is completed in the region where the pattern interval is wide.

Ions dissociated from the etching gas are irradiated between the patterns until the Al wiring 7 ′ at the portion where the pattern interval is narrow is removed, and the contact with the Al wiring layers 7, 7 ′ and the polysilicon gate electrode 4 is made. Hole 6) and further move to semiconductor substrate 1 via gate insulating film 3. This current causes damage to the surface (antenna) of the densely formed pattern, the gate insulating film 3, and the like.

The above-described electron shading effect and microloading effect are the main causes of plasma damage. The electron shading effect becomes more remarkable as the wiring space becomes smaller, and may cause abnormalities in the cross-sectional shape of the Al wiring (side etching). Therefore, these problems cause a reduction in the reliability of the semiconductor device.

To suppress the electronic shading effect,
There is a method of increasing the distance between the substrate and the ECR region. However, when the distance between the substrate and the ECR region is increased, ions are accelerated and ion energy increases, so that the etching rate of the resist increases. When the etching rate of the resist increases, the etching selectivity of the metal wiring layer to the resist decreases, leading to deterioration of the pattern, or a shortage of the necessary resist (for example, 200 nm) at the end point of the etching.

The present invention has been made in view of the above problems, and therefore, the present invention provides a method for forming a wiring pattern while securing a sufficient remaining amount of resist without damaging a base in the manufacture of a semiconductor device. It is an object of the present invention to provide a dry etching method capable of performing the dry etching method.

[0016]

In order to achieve the above object, a dry etching method according to the present invention comprises the steps of: forming a resist on a conductive layer; exposing and developing the resist; Performing a patterning step;
Performing a first plasma etching on the conductive layer using the resist as a mask to remove the conductive layer in a region having a relatively large pattern interval; Performing a second plasma etching process on the conductive layer under etching conditions that reduce the conductive layer in a region where the pattern interval is relatively narrow, and a step of removing the resist. Features.

In the dry etching method according to the present invention, preferably, the second plasma etching is performed by setting a distance between the resist surface and the plasma high-density region larger than that of the first plasma etching. And Dry etching method of the present invention, more preferably, the adjustment of the distance between the resist surface and the plasma high-density region,
It is characterized in that it is performed by controlling the magnetic field intensity distribution in the etching reaction chamber. The dry etching method according to the present invention is preferably characterized in that the control of the magnetic field intensity distribution is performed using a solenoid coil having a plurality of stages. In the dry etching method according to the present invention, preferably, the conductive layer is made of a metal containing aluminum.

As a result, a highly anisotropic pattern is formed in the first etching performed with the substrate placed near the plasma generating section. Thereafter, the distance between the substrate and the ECR region is increased in the overetching step, so that the resist is not excessively etched. Further, by increasing the distance between the substrate and the ECR region, the electron shading effect can be reduced. Therefore, it is possible to prevent the Al wiring from remaining in the region where the pattern interval is small, and prevent the occurrence of a leak current to the substrate and the gate breakdown.

[0019]

Embodiments of the dry etching method according to the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 shows an example of an ECR etching apparatus that can be used in the dry etching method of this embodiment. The apparatus shown in FIG. 1 includes an application electrode 11, an installation electrode 12,
High frequency power supply 13, microwave power supply (magnetron) 1
4, microwave waveguide 15, solenoid coil 16a,
16b and a reaction chamber (bell jar) 17 at least. Further, the inside of the reaction chamber 17 can be evacuated to a high vacuum by a vacuum system (not shown).

In the apparatus shown in FIG. 1, a reaction chamber 1 made of quartz is used.
A substrate (wafer) 18 to be etched is set in 7, and an etching gas is introduced from a gas inlet 19. 2.45 GHz generated from microwave power supply 14
Of the reaction chamber 17 through the microwave waveguide 15.
And the etching gas is turned into plasma. Further, high frequency is applied using the high frequency power supply 13 to etch the substrate 18 or the layer formed on the substrate surface.

The distance between the substrate and the ECR area is
Is determined by the current values of the upper-stage coil 16a and the lower-stage coil 16b arranged so as to go around. The upper coil 16a and the lower coil 16b receive power supply independently, and control the magnetic field intensity distribution in the reaction chamber 17. The ECR region is moved in the axial direction of the reaction chamber 17 by adjusting the amount of power supplied to the coils of each stage. Etching conditions other than the distance between the substrate and the ECR region, for example, the composition and flow rate of the etching gas, the substrate temperature, the pressure, and the like may be appropriately selected.

FIGS. 2A and 2B are cross-sectional views showing the steps of the dry etching method of this embodiment. FIG.
As shown in (A), a Ti layer 9 and a TiN layer 10 as a barrier layer and an adhesion layer are stacked on the semiconductor substrate 1 by a film forming method such as sputtering. An Al wiring 7 is formed thereon by sputtering or the like, and a resist 8 is applied on the Al wiring 7. The resist 8 is exposed and developed by a photolithography process. Subsequently, FIG.
As shown in (B), the Al wiring 7, the TiN layer 10 and the Ti layer 9 are etched using the resist 8 as a mask.

In the dry etching method of this embodiment, the electron shading effect is suppressed by controlling the distance between the substrate and the ECR region in two stages. In order to eliminate the imbalance between the electrons and the ions between the wiring patterns as shown in FIG. 6, electrons which cannot enter between the wiring patterns due to the electron shading effect are made to enter between the patterns, or are injected between the patterns. It is necessary to reduce ions to be generated. By increasing the distance between the substrate and the ECR region, it is possible to reduce ions that enter between the Al wiring patterns.

As shown in the schematic diagram of FIG.
By the irradiation of 0, the plasma density in the ECR region 21 becomes maximum. When the distance between the substrate 18 and the ECR region 21 is increased, during the movement of the ions from the ECR region 21 to the substrate 18, the direction of movement of the ions 23 is bent by the influence of the lines of magnetic force 22, and the straightness of the ions 23 is reduced. Further, recombination with the electrons 24 occurs, and the ion density decreases. Further, radicals having a shorter lifetime than the ions 23 tend to disappear before reaching the substrate 18. The etching reaction includes a reaction by ions, a reaction by radicals, and a reaction by ions and radicals (ion-assisted reaction), and the reduction of radicals reduces the influence of radicals including ion-assisted reactions. As described above, by increasing the distance between the substrate and the ECR region, the incidence of ions 23 between the wirings can be reduced, and plasma damage can be prevented.

(Embodiment 2) The correlation between the distance between the substrate and the ECR region in the dry etching step and the etching of the resist will be described below with reference to FIGS. 4 shows the etching rate of the resist, and FIG. 5 shows the remaining amount of the resist remaining on the pattern shoulder after the etching.

The evaluation of the resist etching rate and the remaining amount of the resist was performed using the samples shown in FIGS. 2 (A) and 2 (B). The thickness of the Ti layer 8 is set to 20 nm,
Was 90 nm, the thickness of the Al wiring 7 was 500 nm, and the thickness of the resist 8 was 1.0 μm. The etching process of the Al wiring is performed until the Ti layer 8 is removed.
An overetch step was performed. The over-etch process is
The etching was performed for 25% of the time required for etching the Al wiring 7. Then, the remaining amount was observed by SEM (scanning electron microscope). The etching condition is a reaction chamber pressure of 8 mTo.
rr, an applied high-frequency output of 70 W, and an etching process gas BCl ₃ / Cl ₂ = 40/60 sccm. These etching conditions were common to the Al wiring etching step and the overetch step.

FIG. 4 shows the resist etching rate when the distance between the substrate and the ECR region is changed. A
The distance between the substrate and the ECR region was not changed in the l-wiring etching step and the over-etching step. As shown in FIG. 4, when the distance between the substrate and the ECR region is increased, ions are accelerated, so that the etching rate of the resist is increased. The distance between the substrate and the ECR area is 30 to 40
When it is increased in the range of mm, the etching rate of the resist increases from 300 nm / min to about 500 nm / min.

FIG. 5 shows the remaining resist amount when the distance between the substrate and the ECR region is changed. Substrate and ECR
When the Al wiring etching step and the over-etching step are performed while keeping the distance to the region constant, (a)
Increasing the distance between the substrate and the ECR region increases the etching rate of the resist, so that the remaining amount of the resist decreases. In the case of the sample shown in FIG. 2, it is necessary to secure the remaining resist amount after etching of 200 nm or more. Therefore, if the distance between the substrate and the ECR region is set to 40 mm in both the etching step and the over-etching step of the Al wiring, the remaining amount of the resist is insufficient, and good patterning cannot be performed.

On the other hand, if the distance between the substrate and the ECR region is 30 mm in the Al wiring etching step and 40 mm in the over-etching step (b), the distance is 25 mm.
A resist remaining amount of about 0 nm is secured, which satisfies the specifications. By increasing the distance between the substrate and the ECR region in the over-etching step as in b, the electron shading effect can be suppressed, and plasma damage such as gate destruction can be prevented.

According to the dry etching method of the embodiment of the present invention, a pattern having high anisotropy is formed by the first etching performed by disposing the substrate in the vicinity of the ECR region. In the substrate and EC
Since the distance to the R region is increased, the resist is not excessively etched. Further, by increasing the distance between the substrate and the ECR region, the electron shading effect can be reduced. Therefore, A
It is possible to prevent the l wiring from remaining and prevent the occurrence of a leak current to the substrate and gate destruction.

The embodiment of the dry etching method of the present invention is not limited to the above description. For example, in a semiconductor device having a multilayer wiring structure, an adhesion layer (Ti layer or the like) may be laminated not only on the lower layer but also on the upper layer of the Al wiring in order to increase the affinity between the Al wiring and the interlayer insulating film. The dry etching method of the present invention can also be applied to various laminated films.
In addition, when reducing the rectilinearity of ions in the second plasma etching step, in addition to increasing the distance between the etching surface and the plasma high-density region, changing other etching conditions such as microwave output and reaction chamber pressure. Can also be performed. In addition, various changes can be made without departing from the gist of the present invention.

[0032]

According to the dry etching method of the present invention, in the manufacture of a semiconductor device, it is possible to form a wiring pattern without damaging the base and ensuring a sufficient remaining amount of resist.

[Brief description of the drawings]

FIG. 1 shows E used in a dry etching method of the present invention.
It is the schematic of a CR etching apparatus.

FIGS. 2A and 2B are cross-sectional views showing steps of a dry etching method of the present invention.

FIG. 3 is a diagram schematically illustrating an effect when a distance between a substrate and an ECR region is increased in the dry etching method of the present invention.

FIG. 4 is a graph showing a resist etching rate when a distance between a substrate and an ECR region is changed in the dry etching method of the present invention.

FIG. 5 is a graph showing the remaining resist amount when the distance between the substrate and the ECR region is changed in the dry etching method of the present invention.

FIG. 6 is a diagram illustrating an electron shading effect and a microloading effect in a conventional dry etching method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... LOCOS, 3 ... Gate insulating film,
4 gate electrode, 5 interlayer insulating film, 6 contact hole, 7 Al layer, 8 resist, 9 Ti layer, 10 T
iN layer, 11 application electrode, 12 ground electrode, 13 high-frequency power supply, 14 microwave power supply, 15 microwave waveguide, 16a, 16b solenoid coil, 17 reaction chamber, 18 substrate (wafer), 19 ... Gas inlet, 2
0: microwave, 21: ECR region, 22: magnetic field line, 2
3 ... ion, 24 ... electron.

Claims (5)

[Claims] A step of forming a resist on the conductor layer; a step of exposing and developing the resist to pattern the resist; and a step of forming a first plasma on the conductor layer using the resist as a mask. A step of performing etching to remove the conductive layer in a region where the pattern interval is relatively large; and forming a second conductive layer on the conductive layer under etching conditions in which the straightness of ions is reduced as compared with the first plasma etching. A dry etching method comprising: performing a plasma etching of the above to remove the conductive layer in a region where a pattern interval is relatively narrow; and removing the resist. 2. The dry etching method according to claim 1, wherein the second plasma etching is performed by setting a distance between the resist surface and the plasma high-density region larger than that of the first plasma etching. 3. The dry etching method according to claim 2, wherein the adjustment of the distance between the resist surface and the plasma high-density region is performed by controlling a magnetic field intensity distribution in an etching reaction chamber. 4. The dry etching method according to claim 2, wherein the control of the magnetic field intensity distribution is performed using a solenoid coil having a plurality of stages. 5. The dry etching method according to claim 1, wherein said conductor layer is made of a metal containing aluminum.