JP3362093B2 - How to remove etching damage - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to removing damages to a silicon layer when forming a contact hole in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art A semiconductor wafer used for manufacturing semiconductor devices is subjected to a CVD process for forming a thin film of a desired substance on the surface of the semiconductor wafer, an etching process for forming a fine circuit pattern on the semiconductor wafer, and the like. Then, these steps are repeated to form a predetermined circuit.
Here, various semiconductor manufacturing apparatuses using plasma are used to perform these processes. This device, by plasma discharge to the reaction gas under reduced pressure,
The semiconductor wafer is processed by generating reactive species such as ions and radicals that are not stably obtained under normal pressure to promote a predetermined chemical reaction.

In such a semiconductor manufacturing apparatus, it is important from the viewpoint of yield to process the semiconductor wafer under the condition that the damage due to the contamination is small. Regarding the problem of semiconductor wafer contamination in plasma processing, for example, “Monthly Semiconductor World”, March 1991, published by Press Journal, Inc.
(Published February 20, 2013), P153-P159.

In the above-mentioned etching process, in order to establish conduction between the underlying conductive layer and the conductive layer above it, a contact hole is formed at a predetermined position of the interlayer insulating film deposited on the underlying conductive layer, and the upper conductive layer is formed. A technique is adopted in which the upper layer and the underlying conductive layer are connected by burying this also in the contact hole when forming. When the underlying conductive layer is a silicon layer such as single crystal silicon that becomes a semiconductor substrate or polycrystalline silicon that forms a gate electrode, etc., even a part of the silicon layer is etched when the contact hole is formed. Due to the over-etching, the silicon layer is damaged by deposition of contaminants such as reaction products. If the upper conductive layer is formed while leaving such a damaged part as it is, the contact resistance of the upper and lower conductive layers becomes high due to the damaged part and ohmic contact cannot be made, so that the desired specifications can be satisfied. As a result, the product becomes defective.

Therefore, a technique for removing such a damaged portion is required. Examples of applicable technologies include CHF
A process gas whose volume ratio of ₃ and O ₂ was adjusted to 1: 9 was introduced into the chamber at 400 sccm to generate plasma, and the semiconductor wafer placed there was plasma-treated to damage it. It is conceivable to remove parts.

[0006]

However, according to the technique described above, the damaged portion is removed because the etching rate of the interlayer insulating film with respect to the underlying silicon layer is high, but the interlayer insulating film is also etched at the same time. Side etching progresses because the diameter of the contact hole expands.

When the diameter of the contact hole is increased, if there is a wiring close to the contact hole, this is exposed in the contact hole and an electrical short circuit occurs. 16 MD
In a semiconductor device manufactured by a microfabrication technique of 0.5 μm rule or less such as RAM, the contact hole has a small hole diameter and there is almost no margin, so that such a phenomenon occurs more remarkably.

Therefore, an object of the present invention is to provide a technique capable of removing a damaged portion formed in an underlying silicon layer when forming a contact hole in an interlayer insulating film while suppressing side etching of the contact hole to a minimum. To provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the etching damage removing method according to the present invention is an etching damage removing method for removing a damaged portion received in a base silicon layer when a contact hole is formed in an interlayer insulating film on a silicon wafer. , CF ₄ to the semiconductor wafer having the damage portion upper bottom in the plasma generating chamber is placed in a chamber configured in the processing chamber, the content of CF ₄ is 60 to 80 volume%
A processing gas consisting of + O ₂ is introduced into the chamber at an introduction pressure of 0.5 to 1.0 Torr and a flow rate of 65 to 95 sccm, the temperature of the semiconductor wafer is set to 20 to 80 ° C., and high frequency power is set to 50 to 20 ° C.
It is characterized by applying 0 W to generate plasma to remove the damaged portion.

In this case, CF in the processing gas
₄ or CHF ₃ content of about 70% by volume, introduction pressure of about
It is desirable that the flow rate be 0.7 Torr and the flow rate be approximately 80 sccm. The frequency of the applied high frequency power is, for example,
2MHz, 13.56MHz and 2.45GHz can be used. The chamber may be separated into a plasma generation chamber in which plasma is generated and a processing chamber in which a semiconductor wafer is installed by a plate electrode.

By such means, the side etch amount of the contact hole can be suppressed to a minimum value of 0.025 μm or less, and the adjacent wiring is not exposed in the contact hole, so that the wiring layers can be mutually connected. It becomes possible to prevent an electrical short circuit between them.

The content of CF ₄ or CHF ₃ is about
The amount of side etch can be minimized by setting the volume to 70 vol%, the introducing pressure to about 0.7 Torr, and the flow rate to about 80 sccm.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view showing an etching apparatus using an etching damage removing technique according to an embodiment of the present invention, FIG. 2 is a sectional view showing a semiconductor wafer having a damaged portion in a silicon layer, and FIG. 2 is an enlarged cross-sectional view showing the contact hole of the semiconductor wafer, and FIGS. 4 to 6 are graphs showing the relationship between the etching conditions for removing the damaged portion of the silicon layer and the resulting side etch amount.

The etching apparatus shown in FIG. 1 removes a damaged portion 24 formed in the underlying silicon layer 23 by forming a contact hole 22 in a BPSG film (interlayer insulating film) 21 applied to the surface of the semiconductor wafer 1. The chamber 2 constituting the main body of the apparatus has a discharge tube 4 in which a plasma generation chamber 3 is formed, which is used for that purpose (see FIGS. 2 and 3). For example, a processing gas supply port 5 is opened at the top of the discharge tube 4 made of quartz, and the processing gas G composed of CF ₄ + O ₂ is introduced into the plasma generation chamber 3. It should be noted that the components inside the chamber 2 are covered with a cover such as ceramic or fluororesin to prevent contamination.

On the outer periphery of the discharge tube 4, a first sheet electrode 6a and a second sheet electrode 6b for exciting plasma discharge in the plasma generating chamber 3 are arranged in a comb-like shape having a convex portion and a concave portion. Has been done. This first sheet electrode 6a
In order to supply electric power to the first sheet electrode 6a, one end of a high frequency power source (hereinafter referred to as "RF power source") 7 is connected. Therefore, R is applied to the first sheet electrode 6a.
The F power source 7 supplies a high frequency of about 100 kHz to 3 GHz, eg, 13.56 MHz, with a power of about 50 to 200 W, eg, 100 W. However, the frequency may be 2 MHz or another usable band such as 2.45 GHz. Also, the second
The sheet electrode 6b is grounded and dropped to the ground level.

A processing chamber 8 is formed below the chamber 2, that is, below the plasma generating chamber 3. This processing room 8
Is a wafer chuck 9 for holding the semiconductor wafer 1.
Is provided, and the damaged portion 24 of the silicon layer 23 described above is removed by the neutral active species introduced from the plasma generation chamber 3 described above.

The semiconductor wafer 1 is attached to the wafer chuck 9 that holds the circuit forming surface of the semiconductor wafer 1 upward.
Is incorporated into the heater 10 to heat it to, for example, about 20 to 80 ° C. to improve the processing speed. Further, in order to set the pressure inside the chamber 2 to a low pressure, an exhaust port 11 is provided on the bottom wall of the processing chamber 8 and the exhaust port 11 is connected to a vacuum pump (not shown).

The plasma generation chamber 3 and the processing chamber 8 are separated by a flat plate electrode 12 that captures ions generated in the plasma generation chamber 3, and damage to the semiconductor wafer 1 due to ion bombardment is prevented in advance. Through holes 13 are formed in the flat plate electrode 12 in a lattice pattern or in a radial pattern, and the neutral active species generated in the plasma generation chamber 3 are provided in the through holes 1.
It is introduced into the processing chamber 8 through 3.

On the semiconductor wafer 1 processed by the etching apparatus, deposition of contaminants such as reaction products and crystal defects due to over-etching at the time of forming the contact holes 22 in the BPSG film 21 as shown in FIG.
The underlying silicon layer 23 has a damaged portion 24 having a thickness of, for example, about 10 nm to be removed as shown in FIG. Further, as shown in FIG. 2, the wiring 25 already formed is located in the vicinity of the opened contact hole 22.

In order to remove the damaged portion 24, the semiconductor wafer 1 is placed on the wafer chuck 9 in the processing chamber 8.
To place. Next, the chamber 2 is evacuated to CF ₄
The processing gas G composed of + O ₂ is introduced into the plasma generation chamber 3 through the processing gas supply port 5. At this time, the chamber 2 is evacuated to an introduction pressure of 0.5 to 1.0 Torr, and the processing gas G is introduced at a flow rate of 65 to 95 sccm with a CF ₄ content of 60 to 80% by volume. Such conditions are derived for the following reasons.

That is, the damaged portion 24 shown in FIG.
Before removing the contact hole 22 (A),
Assuming that the hole diameter after removal shown in FIG. 3B is (A ′), the side etch amount is defined by (A′−A). And 0.
Assuming a device designed with a size of 5 μm rule or less, it is necessary to suppress the side etch amount to 0.025 μm or less in order to prevent an electrical short between adjacent wirings. Therefore, the above-mentioned numerical values are defined by examining the relationship between the content rate of CF ₄ , the introduction pressure and the flow rate, and the side etch amount. That is, when the content of CF ₄ is set to about 60 to 80% by volume, the side etch amount becomes 0.025 μm or less, which is less than or equal to the above target value.
The best value is shown at about 70% by volume (Fig. 4). Regarding the introduction pressure, when the pressure is set to about 0.5 to 1.0 Torr, the side etch amount becomes 0.025 μm or less, which is about 0.7 Torr.
The best value for rr is shown (Fig. 5). The processing gas flow rate is below the target value at about 65 to 95 sccm, and shows the best value at about 80 sccm (FIG. 6).

Therefore, if the damaged portion 24 of the silicon layer 23 is removed under these conditions, preferably at the best values, the side etch amount of the contact hole 22 becomes a device having a rule of 0.5 μm or less. This is because it will be kept within a tolerable range, that is, it will be minimized. It should be noted that in the case of a device with a 0.1 μm rule or less, which is expected in the future, the conditions can be further narrowed down and processed.

Then, the RF power supply 7 supplies 100 W of power at a frequency of 13.56 MHz to the first sheet electrode 6a. As a result, plasma of the reactive gas is generated in the plasma generation chamber 3.

In the plasma generation chamber 3, electrons are accelerated at high speed by a high frequency electric field generated by the high frequency discharge to generate ions and neutral active species, which are directed toward the processing chamber 8 located below. The ions are trapped by the plate electrode 12, while the neutral active species are penetrated by the through holes 13 of the plate electrode 12.
And is introduced into the processing chamber 8 to act on the semiconductor wafer 1 placed there. Then, according to the above-mentioned conditions,
The damaged portion 24 of the silicon layer 23 is removed in a state where the side etch amount of the contact hole is minimized to 0.025 μm or less (FIG. 3B).

[0028] Thus, according to the embodiment of the present invention, CF ₄ + O the content of CF ₄ is 60 to 80 volume%
_The processing gas G consisting of 2 is introduced into the chamber 2 at an introduction pressure of 0.5 to 1.0 Torr and a flow rate of 65 to 95 sccm, and the semiconductor wafer 1
By removing the damaged portion 24 generated in the silicon layer 23, the side etching amount of the contact hole 22 can be minimized. As a result, the adjacent wiring 25 is not exposed in the contact hole 22, and it is possible to prevent electrical short-circuits between the wiring layers even in a device having a fine structure such as 0.5 μm rule or less. By setting the CF ₄ content to about 70% by volume, the introduction pressure to about 0.7 Torr, and the flow rate to about 80 sccm, the side etch amount becomes almost minimum.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the embodiment of the present invention, the processing gas G made of CF ₄ + O ₂ is used. However, when the processing gas made of CHF ₃ + O ₂ is used, the same conditions are obtained. Equally good results have been obtained.
Therefore, the damaged portion 24 may be removed by the processing gas.

The damaged portion 24 is, for example, MOS (M
The present invention may be applied to the removal of the damaged portion 24 in the polycrystalline silicon because it occurs in the polycrystalline silicon that constitutes the gate electrode of the et al oxide semiconductor FET).

Further, in the embodiment of the present invention,
Although the BPSG film is deposited as the interlayer insulating film, another interlayer insulating film such as a PSG film or an SOG film can be used.

In the etching apparatus according to the embodiment of the present invention, the plasma generating chamber 3 in which plasma is generated and the processing chamber 8 in which the semiconductor wafer 1 is installed are separated,
Although the so-called downflow type in which the neutral active species in the plasma generation chamber 3 is introduced into the processing chamber 8, the device structure is not limited to this, and other types using reactive gas plasma are used. It can be widely applied to etching apparatuses having various structures.

[0034]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1). That is, according to the etching damage removing technique of the present invention, a processing gas of CH ₄ + O ₂ or CHF ₃ + O having a CF ₄ or CHF ₃ content of 60 to 80% by volume is used. Introducing a process gas consisting of ₂
Since the damaged portion of the silicon layer is removed by introducing into the chamber at 0.5 to 1.0 Torr and a flow rate of 65 to 95 sccm, the side etch amount of the contact hole can be suppressed to the minimum.

(2) As a result, adjacent wirings are not exposed in the contact holes, and it is possible to prevent electrical shorts between the wiring layers.

(3) The CF ₄ or CHF ₃ content is about 70% by volume, the introduction pressure is about 0.7 Torr, and the flow rate is about 80 sc.
By setting to cm, the side etch amount can be minimized.

[Brief description of drawings]

FIG. 1 is a sectional view showing an etching apparatus using an etching damage removing technique according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a semiconductor wafer having a damaged portion in a silicon layer.

FIG. 3A shows a silicon layer having a damaged portion,
(B) is a sectional view showing a silicon layer from which a damaged portion is removed.

FIG. 4 is a graph showing a relationship between a CF ₄ content of a processing gas and a side etch amount when removing a damaged portion of a silicon layer.

FIG. 5 is a graph showing the relationship between the introduction pressure of the processing gas and the side etch amount when removing the damaged portion of the silicon layer.

FIG. 6 is a graph showing a relationship between a processing gas flow rate and a side etch amount when removing a damaged portion of a silicon layer.

[Explanation of symbols]

1 Semiconductor wafer 2 chamber 3 Plasma generation chamber 4 discharge tubes 5 Processing gas supply port 6a First sheet electrode 6b Second sheet electrode 7 High frequency power supply 8 processing room 9 Wafer chuck 10 heater 11 exhaust port 12 Flat plate electrode 13 through holes 21 BPSG film (interlayer insulating film) 22 Contact holes 23 Silicon layer 24 Damaged part 25 wiring G processing gas

Continuation of the front page (56) References JP-A-6-283460 (JP, A) JP-A-3-185823 (JP, A) JP-A-6-188229 (JP, A) JP-A-63-53928 (JP , A) JP-A-56-158874 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/3065 H01L 21/28

Claims (6)

(57) [Claims] 1. A method of removing etching damage, which removes a damaged portion of a base silicon layer when a contact hole is formed in an interlayer insulating film on a silicon wafer, wherein a semiconductor wafer having the damaged portion is formed on an upper surface of the semiconductor wafer. Is a plasma generating chamber and the lower part is a processing chamber, and a process gas composed of CF ₄ + O ₂ having a CF ₄ content of 60 to 80% by volume is introduced at an inlet pressure of 0.5 to 1.0 Torr and a flow rate. 65 ~ 95sc
Introduced into the chamber in cm, the temperature of the semiconductor wafer is 20 ~ 80 ℃, high-frequency power is applied 50 ~ 200W to generate plasma to remove the damaged portion characterized by etching damage Removal method. 2. The method for removing etching damage according to claim 1, wherein the content rate of CF _{4 in} the processing gas is about 70% by volume, the introduction pressure is about 0.7 Torr, and the flow rate is about 80 sccm.
And a method for removing etching damage. 3. A method of removing etching damage, which removes a damaged portion received in an underlying silicon layer when a contact hole is formed in an interlayer insulating film on a silicon wafer, wherein a semiconductor wafer having the damaged portion is formed on an upper surface of the semiconductor wafer. CHF ₃ + O ₂ but the lower the plasma generation chamber is placed in a chamber formed in the processing chamber, the content of CHF ₃ is 60 to 80 volume%
Introducing a processing gas consisting of 0.5 to 1.0 Torr and a flow rate of 65 to
Introduced into the chamber at 95sccm, the temperature of the semiconductor wafer is set to 20 ~ 80 ℃, high-frequency power is applied 50 ~ 200W to generate plasma to remove the damaged portion characterized by etching Removal method. 4. The method for removing etching damage according to claim 3, wherein the CHF ₃ content in the processing gas is about 70% by volume, the introduction pressure is about 0.7 Torr, and the flow rate is about 80 sc.
A method for removing etching damage, which is characterized in that it is cm. 5. The method for removing etching damage according to claim 1, 2, 3 or 4, wherein the frequency of the applied high frequency power is 2 MHz, 13.56 MHz or 2.45.
A method for removing etching damage, which is characterized in GHz. 6. The method for removing etching damage according to claim 1, 2, 3, 4, or 5, wherein the chamber is provided with a plasma generation chamber for generating plasma and the semiconductor wafer. The etching damage removing method is characterized in that it is separated from the processing chamber to be treated by a plate electrode.