JPH1041508A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the short circuit of a gate electrode and wiring without giving a burden on the structure such as the longitudinal dimension, etc. SOLUTION: After a polycrystalline silicon 103 and a WSix layer 104 are deposited, an offset insulating layer 105 is formed and patterned to have a gate electrode size (a). A condition is imposed that at least the side surface of the WSix layer 104 is etched when the polycrystalline silicon 103 and the WSix layer 104 are etched by using the offset oxide layer 105 as a mask (b). Gate electrodes 110a, 110b having a shape in which the offset oxide layer 105 is overhung on the WSix layer 104 are obtained. Then, after side walls are formed on the side surfaces of the gate electrodes, an interlayer insulating film is formed, and a contact hole is formed and is filled with a wiring layer. Even after the etching for the contact hole formation, a sufficient thickness of the side wall between the shoulder part of the gate electrode and the wiring layer is guaranteed and the withstand voltage is ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a self-aligned contact structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, VLSI (Very Large Scale Int.
In the field of semiconductor devices such as egration), with the progress of high integration and high performance, silicon oxide (Si
Technical requirements for dry etching of an O ₂ ) -based material layer are becoming increasingly severe.

[0003] Under such circumstances, a self-aligned contact (Self Aligned Contact) which can eliminate a design margin on a mask for alignment in a contact hole process.
t; hereinafter, referred to as SAC. ) Technology is attracting attention. The development of the SAC technology has been particularly active in the field of manufacturing semiconductor devices of the generation after the 0.25 μm rule.

One of the factors that draws attention to this SAC technology is that there is a limitation in the performance of an exposure apparatus (stepper), and the other is that the area of a chip or a cell is further reduced by using the SAC. Is what you can do. Specifically, regarding the former factor, the 0.25 μm currently available
The exposure apparatus for mass production of m-rule semiconductor devices has a problem that it is difficult to further miniaturize the wiring layer. This is because the variation in the alignment of the stepper is not sufficiently improved. Since the variation in the alignment is large, the design margin of the alignment needs to be increased. As a result, there arise problems such as an increase in the width of the wiring or an excessively small contact hole diameter to prevent opening.

FIG. 11 shows a structure of a contact hole forming portion in a conventional semiconductor device. The semiconductor device includes a gate oxide film 202 formed on the silicon substrate 201, a gate oxide film 202 polycrystalline silicon layers are stacked on 203 and tungsten silicide (WSi _X) layer 204 made of the gate electrode 205a, 2
05b. The gate electrode 205a and the gate electrode 205b are patterned so as to be separated by a predetermined horizontal distance. Offset oxide film 209 is formed on the WSi _X layer 204 is formed, also, the gate electrode 2
On both sides of the offset films 05a and 205b and the offset oxide film 209, sidewall films 206 made of an insulating film are formed. The interlayer insulating film 2 is formed so as to cover these structures.
07 is formed.

In the process of manufacturing such a semiconductor device, in order to form a contact hole reaching the silicon substrate 201 between the gate electrode 205a and the gate electrode 205b, patterning is performed so as to have an opening in the contact hole formation region. A photoresist film 208 is formed, and the interlayer insulating film 207 is removed by etching using the photoresist film 208 as an etching mask.

At this time, if the variation in the positioning of the stepper is large as described above, the contact hole opening diameter of the photoresist film 208 must be reduced in order to process a contact that can reliably connect the silicon substrate 201. Must be large. At this time, if the distance between the gate electrodes is reduced, a contact hole formed by etching reaches a part of the gate electrodes 205a and 205b as shown in FIG. Here, if the etching of the interlayer insulating film 207 for forming the contact hole is performed only for the thickness of the interlayer insulating film 207, the original SAC structure can be formed. However, in practice, over-etching is required as shown in the figure to sufficiently expose the silicon substrate 201. Therefore, most sputtering efficient corners (part of one corner of WSi _X layer 204) is cut, in the worst case, that portion (wiring short portion 211) is exposed. For this reason, a short circuit occurs between the wiring buried in the contact hole and the gate electrode 205a or 205b. Therefore, it is indispensable to solve this problem when miniaturizing elements.

[0008] SAC is a technique which is said to eliminate the need for a design margin for this alignment. There are several methods for forming this SAC structure, all of which have the disadvantage that the process is slightly more complicated than the conventional method of performing only exposure. However, it is considered that the adoption of the SAC technology is inevitable in consideration of the flow of miniaturization that will continue in the future.

Among such SAC forming methods, a method of using a silicon nitride (Si ₃ N ₄ ) film as an etching stopper film when forming a contact hole is being actively studied. This method is advantageous in that the number of exposure steps does not increase, so that the cost increase is relatively small.
In addition, there is a method of using a metal film as an etching stopper film. However, an extra exposure process is required, and the manufacturing process is complicated.

FIG. 12 shows an etching stopper film made of Si.
The method of manufacturing a semiconductor device using a ₃ N ₄ film is used to represent an. In this semiconductor device, the gate electrodes 205a, 205
b, offset oxide film 209 and sidewall film 2
After the formation of 06, an etching stopper film 210 made of a Si ₃ N ₄ film is formed, and then an interlayer insulating film 207 is formed. In this semiconductor device, the gate electrode 2 is formed by a Si ₃ N ₄ film (etching stopper film 210) having a high selectivity with respect to SiO ₂ constituting the interlayer insulating film 207.
Since the sidewall films 206 on both sides of the gate electrodes 05a and 205b are protected, the sidewall films 206 are prevented from being etched when a contact hole is opened between the gate electrodes 205a and 205b. And
By removing the etching stopper film 210 (Si ₃ N ₄ ) at the bottom of the contact after forming the contact hole,
A self-aligned contact hole is created. As described above, S using Si ₃ N ₄ as an etching stopper film
By employing the AC structure, no alignment margin is required.

However, in a method of putting SAC using a Si ₃ N ₄ film into practical use, it is essential to develop a difficult etching technique. More specifically, in order to stop the etching on the thin Si ₃ N ₄ film (etching stopper film 210), selection of Si ₃ N _{4 is performed} at the time of etching the SiO ₂ film (interlayer insulating film 207). Attempts have been made to increase the ratio. The process for increasing the selectivity with respect to the Si ₃ N ₄ film is slightly different depending on the discharge method of the apparatus. However, basically, a CF (fluorocarbon) -based protective film is used and the etching rate of the SiO ₂ film is reduced. The method of preventing deterioration by using high-density plasma is effective.

[0012]

However, the SAC
There are still many problems in the technology when viewed comprehensively. For example, after etching a SiO ₂ film with a high selectivity with respect to a Si ₃ N ₄ film as an etching stopper film, the Si ₃ N
_Although it is necessary to perform an etching process for _four films, the SAC technology including the subsequent processes is still insufficient in perfection. This generally means that when etching a Si ₃ N ₄ film, S
Since conditions similar to the etching of the iO ₂ film are used,
Even if the interlayer insulating film (SiO ₂ film) is etched with the selectivity relative to the Si ₃ N ₄ film being considerably increased, the corner portion (gate electrode 205) having the highest sputtering efficiency is obtained.
This is because the side wall film 206 at the corners (a, 205b) is shaved to a certain extent and becomes thinner. Further, when etching for removing the Si ₃ N ₄ film is performed thereafter, the side wall film 206 still has the corner portions. This is because the etching proceeds fastest. Therefore, in the worst case, FIG.
As shown in FIG. 3, the gate electrode 205a and the gate electrode 20
The corner portion 5b is exposed, and a short circuit portion 211 is generated.

In order to avoid such a short circuit in the wiring, it is necessary to take a method of sufficiently increasing the thickness of the offset oxide film 209 covering the gate electrodes 205a and 205b to secure a vertical dimensional margin. The fact is that you can't get it.

The present invention has been made in view of the above problems, and has as its object to provide a self-aligned contact that can prevent a short circuit between a gate electrode and a wiring without burdening a structure such as a vertical dimension. An object of the present invention is to provide a semiconductor device having a structure and a method of manufacturing the same.

[0015]

According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a semiconductor substrate via a gate oxide film and patterned to a predetermined size; and a gate electrode formed on the gate electrode. An insulating layer having a high etching selectivity with respect to the gate electrode. The gate electrode is formed by stacking a high melting point metal layer such as tungsten silicide on a polycrystalline silicon layer, for example. At this time,
At least the lateral dimension of the refractory metal layer is made smaller than the lateral dimension of the insulating layer, and the insulating layer is formed so as to protrude outward (overhang) from the refractory metal layer. The side surface of the high melting point metal layer may be formed in a tapered shape in which the upper side is narrow and the lower side is wide. As the refractory metal layer, for example, tungsten silicide is used.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a gate electrode layer on a gate oxide film formed on a semiconductor substrate, and a step of forming a high etching selectivity on the gate electrode layer with respect to the gate electrode layer Forming an insulating layer having, and patterning the insulating layer having a predetermined size, and etching the gate electrode layer using the patterned insulating layer as an etching mask, the etching of the gate electrode layer in the gate electrode layer etching step The side surfaces are also etched so that the insulating layer protrudes outside the gate electrode layer after the etching. When the gate electrode layer is formed by stacking a polycrystalline silicon layer and a high melting point metal layer, etching is performed so that at least the side surfaces of the high melting point metal layer are etched,
Further, the side surface of the refractory metal layer may have a tapered shape in which the upper side is narrow and the lower side is wide. When tungsten silicide is used as the refractory metal layer, the etching of the side surface of the tungsten silicide layer can be promoted by increasing the flow rate of oxygen gas in the etching step. Further, when a quartz-based constituent material is disposed in the etching chamber, the sputtering amount of the quartz-based constituent material is increased in the etching step, and a large amount of oxygen radical having high activity is supplied into the plasma. Side etching of the tungsten silicide layer can be promoted.

In the semiconductor device and the method of manufacturing the same according to the present invention, since the insulating layer is formed so as to protrude outside the gate electrode, it is necessary to form a contact hole in an interlayer insulating film formed thereafter. The insulating layer covering the shoulder (corner) of the gate electrode can be prevented from being extremely thin by etching.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, an etching apparatus capable of generating high-density plasma will be described as an example of a plasma processing apparatus used for manufacturing a semiconductor device according to the present invention.

FIG. 8 shows an RF (high frequency) bias application type E
1 shows a schematic structure of a CR (Electron Cyclotron Resonance) plasma etching apparatus. In this apparatus, the microwave generated by the magnetron 11 reaches the chamber 19 through the waveguide 12 and further reaches the wafer 15 on the wafer stage 17 via the quartz bell jar 13. The solenoid coil 14 is provided around the chamber 19. The wafer 15 on the wafer stage 17 is fixed by a clamp 16. The wafer stage 17 is connected to a high frequency power supply 18 so that a high frequency voltage of a predetermined frequency is applied.

FIG. 9 shows the main structure of an MCR (magnetically sealed reactor) type etching apparatus. This apparatus applies 13.56 MHz RF from a high-frequency power supply 21 to a quartz side wall electrode 30 and discharges the upper electrode 29 as an anode. Then, a multipole magnet (shown in FIG. ) To confine the magnetic field and form a relatively high-density plasma. In addition, a substrate bias of 450 kHz is applied to the wafer stage 27 from the high-frequency power supply 28, thereby enabling independent control of incident ion energy.

FIG. 10 shows a main structure of an ICP (inductively coupled plasma) type etching apparatus. This apparatus includes a quartz plate 3 provided above a wafer stage 37.
13. A high frequency power supply 33 applies 13.56 MHz RF to the inductive coupling coil 21 spirally wound on the coil 2 to form high density plasma. A wafer 35 clamped by a clamp 36 is placed on the wafer stage 37, and a high-frequency voltage is applied from a high-frequency power supply 38.

Although not shown, FIGS.
0, the high-frequency power supplies 18, 28,
The wafer stages 17, 27, 37 connected to
It has a structure in which a coolant for temperature control (for example, Florinert, trade name) circulates, and further includes a single-pole electrostatic chuck.

Next, a method of manufacturing a semiconductor device having a self-aligned contact using the above-described device will be described.

FIGS. 1 and 2 show a method of manufacturing a semiconductor device according to an embodiment of the present invention. This embodiment is applied to a case where a self-aligned contact structure is formed without using an etching stopper.

First, as shown in FIG. 1A, after a gate oxide film 102 is formed on a silicon substrate 101 by a thermal oxidation method, for example, a low pressure CVD (Chemical Vapor Dep.
osition) method to form the polysilicon layer 103 by 100 n.
was formed to a thickness of about m, forming a WSi _X layer 104 to a thickness of about 100nm by addition, for example, a plasma CVD method on it. Next, for example, by normal pressure CVD
₂ film is formed to a thickness of about 250 nm, and then the Si film is formed using an i-line stopper and a normal SiO ₂ film etching apparatus.
The O ₂ film is processed into a desired gate pattern having a width of 0.35 μm, which is used as an offset oxide film 105.

Next, as shown in FIG. 1B, for example, an ECR type etching apparatus shown in FIG.
_{The X} layer 104 is etched. The etching conditions at this time are set, for example, as follows. Discharge gas: Cl ₂ / O ₂ = 75/12 sccm Container pressure: 0.4 Pa Microwave output: 1200 W RF bias: 70 W (800 kHz) Wafer temperature: 20 ° C. Over etching: 20%

[0028] Thus, at the time of etching the WSi _X layer 104, because of the accelerated side etching of WSi _X layer 104 also enhances microwave power to increase the flow ratio of O _2, as shown in FIG. 1 (b) Offset oxide film 1
05 undercut shape occurs immediately below the result offset oxide film 105 is shaped overhanging on the WSi _X layer 104 as.

Next, as shown in FIG. 1C, the polycrystalline silicon layer 103 is etched using the offset oxide film 105 as an etching mask, similarly using an ECR type etching apparatus (FIG. 8). The etching conditions at this time are set, for example, as follows. Discharge gas: Cl ₂ / O ₂ = 75/5 sccm Container pressure: 0.4 Pa Microwave output: 900 W RF bias: 30 W (800 kHz) Wafer temperature: 20 ° C. Over etching: 40%

As described above, when the polycrystalline silicon layer 103 is etched, the ordinary anisotropic condition is used, so that the polycrystalline silicon layer 103 is not subjected to side etching, and as shown in FIG. And offset oxide film 1
It is etched vertically with almost the same width as 05.

In this manner, two gate electrodes 110a and 110b arranged at a fine interval are formed.

Next, as shown in FIG. 2A, an SiO ₂ film for a side wall is
After being formed to a thickness of about 00 nm, anisotropic etch-back is performed using a normal SiO ₂ film etching apparatus, and LD
A sidewall film 106 for forming a D (Lightly Doped Drain) structure is formed. Further, an interlayer insulating film 107 made of a SiO ₂ film is formed on the entire surface by, eg, normal pressure CVD.
After being formed to a thickness of about 0 nm, the photoresist film 10
Then, a contact hole pattern having a diameter of 0.45 μm is formed in the photoresist 108 using an i-line stepper.

Next, as shown in FIG.
Using a type of SiO ₂ etching apparatus (FIG. 8), the interlayer insulating film 107 is etched using the photoresist film 108 as an etching mask to form a contact hole. The etching conditions at this time are set, for example, as follows. Discharge gas: CHF ₃ / CH ₂ F ₂ = 35/15 sccm Container pressure: 0.27 Pa Microwave output: 1200 W RF bias: 150 W (800 kHz) Wafer temperature: 20 ° C. Over etching: 30%

Despite sufficient over-etching, the gate electrodes 110a, 110
the film thickness of the SiO ₂ film which covers the corner portions of the WSi _X layer 104 b (sidewall 106) is sufficiently ensured.

Next, as shown in FIG. 2C, after the photoresist 108 is completely removed by ashing, a wiring layer 109 made of polycrystalline silicon is formed by, for example, a low pressure CVD method, and this is patterned. . At this time, since a sufficient distance is secured between the gate electrodes 110a and 110b and the wiring layer 109 by the sidewall film 106 having a sufficient film thickness even after etching, sufficient withstand voltage characteristics ( (Breakdown voltage 50V or more)
Can be obtained.

As described above, in the present embodiment, a good self-aligned contact can be formed without using an etching stopper, and the withstand voltage characteristics between the gate electrode and the wiring are sufficient.

Next, another embodiment of the present invention will be described.

In this embodiment, a self-aligned contact is formed without using an etching stopper, as in the above embodiment. First, as shown in FIG. 3A, after a gate oxide film 102 is formed on a silicon substrate 101 by a thermal oxidation method, a polycrystalline silicon layer 103 is formed to a thickness of about 100 nm by, for example, a low pressure CVD method. Then, WS is further formed thereon by, for example, a plasma CVD method.
The i _X layer 104 formed to a thickness of about 100 nm. Next, for example, an SiO ₂ film is formed to a thickness of 250 nm by a normal pressure CVD method.
After being formed to a film thickness of about
_{Using a two-} film etching apparatus, the SiO ₂ film
It is processed into a desired gate pattern having a width of μm, and this is used as an offset oxide film 105.

Next, as shown in FIG.
Using type etching apparatus (FIG. 8), WSi _X layer 104 offsets oxide film 105 as an etching mask
Is etched. The etching conditions at this time are set, for example, as follows. Discharge gas: Cl ₂ / O ₂ = 75/12 sccm Container pressure: 0.4 Pa Microwave output: 1200 W RF bias: 70 W (800 kHz) Wafer temperature: 20 ° C. Over etching: 20%

[0040] Thus, at the time of etching the WSi _X layer 104, because of the accelerated side etching of WSi _X layer 104 also enhances microwave power to increase the flow ratio of O _2, shown in FIG. 3 (b) undercut shape immediately below the offset oxide film 105 occurs as a result offset oxide film 105 is overhanging shape is formed on the WSi _X layer 104 obtained as.

Up to this point, the above embodiment (FIG. 1)
(A) and (b)).

Next, as shown in FIG. 3C, the polycrystalline silicon layer 103 is etched using the offset oxide film 105 as an etching mask, similarly using an ECR type etching apparatus (FIG. 8). The etching conditions at this time are set, for example, as follows. Discharge gas: Cl ₂ / O ₂ = 75/2 sccm Container pressure: 0.4 Pa Microwave output: 1200 W RF bias: 30 W (800 kHz) Wafer temperature: 20 ° C. Over etching: 40%

As described above, in this embodiment, at the time of etching the polycrystalline silicon layer 103, the flow rate ratio of O ₂ is reduced as compared with the case of the above embodiment (FIG. 1C).
Since as side etching when the same amount of WSi _X layer 104 is controlled to occur, as shown in FIG. 3 (c), the offset even until WSi _X layer 104 not only polycrystalline silicon layer 103 It is vertically etched with a width smaller than oxide film 105. That is, the gate electrode 110 having a width smaller than the offset oxide film 105 serving as an etching mask and having a vertical side surface.
a 'and 110b' are obtained.

In this manner, two gate electrodes 110a 'and 110b' arranged at a fine interval are formed.

Next, as shown in FIG. 4A, an SiO ₂ film for a side wall is
After being formed to a thickness of about 00 nm, anisotropic etch-back is performed using a normal SiO ₂ film etching apparatus, and LD
A sidewall film 106 for forming a D structure is formed. Further, an interlayer insulating film 107 made of a SiO ₂ film is formed on the entire surface to a thickness of about 300 nm by, for example, normal pressure CVD, and then a photoresist film 108 is applied and formed. A 0.45 μm diameter contact hole pattern is formed. And EC
Using an R type SiO ₂ etching apparatus (FIG. 8), the interlayer insulating film 107 is etched using the photoresist film 108 as an etching mask. The etching conditions at this time are set, for example, as follows. Discharge gas: CHF ₃ / CH ₂ F ₂ = 35/15 sccm Container pressure: 0.27 Pa Microwave output: 1200 W RF bias: 150 W (800 kHz) Wafer temperature: 20 ° C. Over etching: 30%

[0046] Despite done this way a sufficient over-etching, as shown in FIG. 4 (a), a gate electrode 110a ', 110b' SiO ₂ film which covers the corner portions of the WSi _X layer 104 ( The thickness of the side wall 106) is sufficiently ensured.

Next, as shown in FIG. 4B, after the photoresist 108 is completely removed by ashing, a wiring layer 109 made of polycrystalline silicon is formed by, for example, a low pressure CVD method, and a predetermined shape is formed. Is patterned. At this time, since a sufficient distance is secured between the gate electrodes 110a 'and 110b' and the wiring layer by the sidewall film 106 having a sufficient film thickness even after etching, sufficient withstand voltage characteristics (breakdown) (Voltage 50V or more)
Is obtained.

As described above, also in the present embodiment, a good self-aligned contact can be formed without using an etching stopper, and the withstand voltage characteristics between the gate electrode and the wiring are sufficient.

Next, referring to FIGS. 1, 5 and 6,
Another embodiment of the present invention will be described.

In this embodiment, a self-aligned contact is formed using an etching stopper. Here, the first few steps are similar to those of the above-described embodiment (FIG. 1), and will be described with reference to FIG.

First, as shown in FIG. 1A, after a gate oxide film 102 is formed on a silicon substrate 101 by a thermal oxidation method, a polycrystalline silicon layer 103 is formed to a thickness of about 100 nm by, for example, a low pressure CVD method. is formed with a thickness, WSi _X layer 104 further thereon by, for example, a plasma CVD method
Is formed to a thickness of about 100 nm. Then, for example, after forming a SiO ₂ film to a thickness of about 250nm by atmospheric pressure CVD, desired gate of 0.35μm width the SiO ₂ film by using an i-line stopper and ordinary SiO ₂ film etching apparatus It is processed into a pattern, and this is
5 is assumed.

Next, as shown in FIG. 1 (b), using the etching apparatus of MCR type 9, to etch the WSi _X layer 104 offsets oxide film 105 as an etching mask. The etching conditions at this time are set, for example, as follows.

Discharge gas: Cl ₂ = 60 sccm Container pressure: 0.4 Pa Source output: 1200 W RF bias: 50 W (450 kHz) Wafer temperature: 70 ° C. Over etching: 20%

As described above, at the time of etching the WSi _x layer 104, by increasing the source output and increasing the sputter amount of the side wall electrode 20, oxygen radicals (plasma) from the quartz surface constituting the side wall electrode 20 to the plasma are increased. order to increase the supply of highly active free oxygen atoms O ^*), and so as to facilitate the side etching of the WSi _X layer 104,
Figure 1 undercut shape immediately below the offset oxide film 105 occur as in (b), however, results offset oxide film 105 is overhanging shape is formed on the WSi _X layer 104 obtained as.

Next, as shown in FIG. 1C, the polycrystalline silicon layer 103 is etched using the offset oxide film 105 as an etching mask, also using an MCR type etching apparatus (FIG. 8). The etching conditions at this time are set, for example, as follows. Discharge _{gas: Cl 2 / HBr = 40 /} 40sccm container pressure: 0.4 Pa microwave power: 900 W RF Bias: 20W (450 kHz) wafer temperature: 70 ° C. over-etching: 40%

As described above, since the ordinary anisotropic condition is used in the etching of the polycrystalline silicon layer 103, the polycrystalline silicon layer 103 is not subjected to side etching, as shown in FIG. And offset oxide film 1
It is etched vertically with almost the same width as 05.

Next, as shown in FIG. 5A, an SiO ₂ film for a side wall is
After being formed to a thickness of about 00 nm, anisotropic etch-back is performed using a normal SiO ₂ film etching apparatus, and LD
A sidewall film 106 for forming a D structure is formed. Further, an etching stopper film 11 made of a Si ₃ N ₄ film
1 is formed to a film thickness of about 50 nm,
Interlayer insulating film 1 made entirely of SiO ₂ film by VD method
07 is formed to a thickness of about 500 nm, and flattened by a reflow method. Next, the photoresist film 108
Then, a contact hole pattern having a diameter of 0.45 μm is formed in the photoresist film 108 using an i-line stepper.

Next, as shown in FIG. 5B, an ordinary magnetron type SiO ₂ etching apparatus was used.
The interlayer insulating film 107 is etched using the photoresist film 108 as an etching mask. The etching conditions at this time are set, for example, as follows. Discharge gas: C ₄ F ₈ / CO / Ar = 10/200/30
0 sccm Container pressure: 6.0 Pa RF bias: 1600 W (13.56 MHz) Wafer temperature: 20 ° C. Over etching: 50%

Next, as shown in FIG. 6A, the etching stopper film 111 (Si ₃ N ₄ film) is etched using the photoresist film 108 as an etching mask, similarly using a magnetron type SiO ₂ film etching apparatus. Remove. The etching conditions at this time are set, for example, as follows. Discharge gas: CHF ₃ / O ₂ = 20/20 sccm Container pressure: 6.0 Pa RF bias: 600 W (13.56 MHz) Wafer temperature: 20 ° C. Over etching: 30%

As described above, in this embodiment, when the two etching steps (the etching of the interlayer insulating film 107 and the etching stopper film 111) are combined, the over-etching is more sufficient than in the above-described embodiment (FIG. 2). Despite the operation, as shown in FIG.
Gate electrode 110a, the thickness of the SiO ₂ film which covers the corner portions of the WSi _X layer 104 and 110b is sufficiently ensured.

Next, as shown in FIG. 6B, after the photoresist 108 is completely removed by ashing, a wiring layer 109 made of polycrystalline silicon is formed by, for example, a low pressure CVD method, and a predetermined shape is formed. Is patterned. At this time, since a sufficient distance is secured between the gate electrodes 110a 'and 110b' and the wiring layer 109 by the sidewall film 106 having a sufficient film thickness even after etching, a sufficient withstand voltage is obtained. Characteristics (breakdown voltage of 50 V or more) can be obtained.

As described above, in the present embodiment, a good self-aligned contact can be formed even when an etching stopper is used, and the withstand voltage characteristics between the gate electrode and the wiring are sufficient.

Next, another embodiment of the present invention will be described with reference to FIGS.

In this embodiment, a self-aligned contact is formed using the same etching stopper as in the above embodiment. Here, the first few steps are the same as those in the above-described embodiment (FIG. 3A), and a description thereof will be omitted.

In this embodiment, first, the structure as shown in FIG. 3A is obtained by the same steps and conditions as those described in the above embodiment (FIG. 3A).

Next, as shown in FIG. 3B, for example, using the ICP type etching apparatus shown in FIG.
_{The X} layer 104 is etched. The etching conditions at this time are set, for example, as follows. Discharge gas: Cl ₂ / O ₂ = 100/15 sccm Container pressure: 0.4 Pa Source output: 2500 W RF bias: 90 W (13.56 MHz) Wafer temperature: 20 ° C. Over etching: 20%

As described above, at the time of etching the WSi _x layer 104, the O ₂ flow rate ratio was increased and the source output was also increased to promote the side etching of the WSi _x layer 104. as such, the undercut shape occurs immediately below the offset oxide film 105, the result offset oxide film 105 is shaped overhanging on the WSi _X layer 104 as.

Next, as shown in FIG.
The polycrystalline silicon layer 103 is etched using the ICP type etching apparatus described above. The etching conditions at this time are set, for example, as follows. Discharge gas: Cl ₂ / O ₂ = 100/2 sccm Container pressure: 0.2 Pa Microwave output: 900 W RF bias: 30 W (13.56 MHz) Wafer temperature: 20 ° C. Over etching: 40%

As described above, at the time of etching the polycrystalline silicon layer 103, the flow rate ratio of O ₂ is reduced and the WSi
And _X 104 because the same amount of side etching was controlled to occur, as shown in FIG. 3 (c), WSi _X layer 10
4 as well as the polycrystalline silicon layer 103 are vertically etched with a width smaller than the offset oxide film 105,
Gate electrodes 110a 'and 110b' having a smaller width dimension than offset oxide film 105 serving as an etching mask and having vertical side surfaces are obtained.

Next, as shown in FIG. 7A, an SiO ₂ film for a side wall is
After being formed to a thickness of about 00 nm, anisotropic etch-back is performed using a normal SiO ₂ film etching apparatus, and LD
A sidewall film 106 for forming a D structure is formed. Further, an etching stopper film 11 made of a Si ₃ N ₄ film
1 is formed to a film thickness of about 50 nm,
Interlayer insulating film 1 made entirely of SiO ₂ film by VD method
07 is formed to a thickness of about 500 nm, and flattened by a reflow method. Next, the photoresist film 108
Is applied and photoresist 1 is formed using an i-line stepper.
In 08, a contact hole pattern having a diameter of 0.45 μm is formed. And the usual magnetron type SiO ₂
Using an etching apparatus, the interlayer insulating film 107 is etched using the photoresist film 108 as an etching mask. The etching conditions at this time are set as follows, for example, as in the case of FIG. Discharge gas: C ₄ F ₈ / CO / Ar = 10/200/30
0 sccm Container pressure: 6.0 Pa RF bias: 1600 W (13.56 MHz) Wafer temperature: 20 ° C. Over etching: 50%

Next, as shown in FIG.
Using a magnetron type SiO ₂ film etching apparatus, the etching stopper film 111 (Si ₃ N ₄ film) is etched away using the photoresist film 108 as an etching mask. The etching conditions at this time are shown in FIG.
For example, the following is set as in the case of (1). Discharge gas: CHF ₃ / O ₂ = 20/20 sccm Container pressure: 6.0 Pa RF bias: 600 W (13.56 MHz) Wafer temperature: 20 ° C. Over etching: 30%

As described above, in this embodiment, when the two etching steps (the etching of the interlayer insulating film 107 and the etching stopper film 111) are combined, the over-etching is more sufficient than in the above-described embodiment (FIG. 2). Despite the operation, as shown in FIG.
The gate electrode 110a ', 110b' WSi _X layer 104
The thickness of the SiO ₂ film covering the corners of the above is sufficiently ensured.

Next, as shown in FIG. 7B, after the photoresist film 108 is completely removed by ashing, a wiring layer 109 made of polycrystalline silicon is formed by, for example, a low pressure CVD method. At that time, the gate electrode 110
a ′, 110 b ′ and the wiring layer 109, a sidewall film 10 having a sufficient thickness even after etching.
6, a sufficient distance is secured, so that sufficient withstand voltage characteristics (breakdown voltage of 50 V or more) can be obtained.

As described above, also in the present embodiment, a good self-aligned contact can be formed using the etching stopper, and the withstand voltage characteristics between the gate electrode and the wiring are also sufficient.

Although the present invention has been described with reference to various embodiments, the present invention is not limited to the above-described embodiments and can be variously modified. For example, the conditions (temperature, gas flow rate, gas flow rate ratio, etc.) of the sputtering and the like described in each of the above embodiments are merely examples, and can be set to appropriate values. Process conditions such as an etching plasma source, an apparatus configuration, a sample structure, and etching can be appropriately selected without departing from the gist of the present invention.

[0076]

As described above, according to the semiconductor device and the method of manufacturing the same according to the present invention, since the insulating layer overlying the gate electrode extends outside the gate electrode, it is formed thereafter. It is possible to prevent the insulating layer covering the shoulder (corner) of the gate electrode from being extremely thin or exposed by etching when forming a contact hole in the interlayer insulating film. For this reason, sufficient insulation between the gate electrode and the wiring can be ensured when the self-aligned contact is formed.

[Brief description of the drawings]

FIG. 1 is an element sectional view showing each step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is an element cross-sectional view illustrating each step following FIG. 1;

FIG. 3 is an element cross-sectional view illustrating each step of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 4 is an element cross-sectional view illustrating each step following FIG. 3;

FIG. 5 is a sectional view of an element showing a latter half of a method of manufacturing a semiconductor device according to still another embodiment of the present invention.

FIG. 6 is an element cross-sectional view illustrating each step following FIG. 5;

FIG. 7 is an element sectional view showing a latter half of a method of manufacturing a semiconductor device according to still another embodiment of the present invention.

FIG. 8 is a schematic sectional view showing the configuration of an RF bias application type ECR high-density plasma etching apparatus used in the method of manufacturing a semiconductor device according to the present invention.

FIG. 9 is a schematic sectional view showing a configuration of an MCR type high-density plasma etching apparatus used in the method of manufacturing a semiconductor device according to the present invention.

FIG. 10 is a schematic cross-sectional view showing a configuration of an ICP type high-density plasma etching apparatus used in the method of manufacturing a semiconductor device according to the present invention.

FIG. 11 is a cross-sectional view illustrating a structure of a conventional semiconductor device having a self-aligned contact.

FIG. 12 is a cross-sectional view illustrating a structure of another semiconductor device having a conventional self-aligned contact.

[Explanation of symbols]

11: magnetron, 12: waveguide, 13: quartz bell jar, 14: solenoid coil, 15, 25, 35: wafer, 17, 27, 37: wafer stage, 18, 21,
28, 33, 38: high frequency power supply, 29: upper electrode, 30
... side wall electrode, 31 ... induction coupling coil, 32 ... quartz plate, 1
01: silicon substrate, 102: gate oxide film, 103:
Polycrystalline silicon layer, 104 ... WSi _X layer, 105 ... offset oxide film, 106 ... sidewall film, 107 ... interlayer insulating film, 108 ... photoresist film, 109 ... wiring layer, 110a, 110a ', 110b, 110b ... Gate Electrode, 111 ... etching stopper film

Claims (9)

[Claims] A gate electrode formed on a semiconductor substrate via a gate oxide film and patterned to a predetermined size; and a gate electrode formed on the gate electrode and having high etching selectivity with respect to the gate electrode. A semiconductor device, comprising: an insulating layer, wherein the insulating layer is formed so as to protrude outside the gate electrode. 2. The gate electrode has a laminated structure of at least a polycrystalline silicon layer and a refractory metal layer formed on the polycrystalline silicon layer. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed smaller than a lateral dimension of the layer. 3. The semiconductor device according to claim 2, wherein a side surface of said high melting point metal layer is formed in a tapered shape having a narrow upper side and a wide lower side. 4. The semiconductor device according to claim 3, wherein said refractory metal layer is made of tungsten silicide. 5. A step of forming a gate electrode layer on a gate oxide film formed on a semiconductor substrate; and forming an insulating layer having high etching selectivity on the gate electrode layer on the gate electrode layer. Forming and patterning the gate electrode layer to a predetermined dimension, and using the patterned insulating layer as an etching mask, etching the gate electrode layer. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating layer protrudes outward from the gate electrode layer after the etching by etching the gate electrode layer. 6. The step of forming the gate electrode layer includes at least a step of forming a polycrystalline silicon layer and a step of laminating a high melting point metal layer on the polycrystalline silicon layer. 6. The method according to claim 5, wherein the etching is performed so that at least a side surface of the refractory metal layer is etched. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the etching step, a side surface of the high melting point metal layer is etched into a tapered shape having a narrow upper side and a wide lower side. 8. The method according to claim 1, wherein tungsten silicide is used as said refractory metal layer, and in said etching step, a flow rate of oxygen gas is increased to promote side etching of said tungsten silicide layer. Item 7. The semiconductor device according to Item 6. 9. A method in which tungsten silicide is used as the refractory metal layer, a quartz-based component is disposed in an etching chamber, and the amount of sputter of the quartz-based component is increased in the etching step. 7. The semiconductor device according to claim 6, wherein a large amount of oxygen radical having a high degree is supplied into the plasma to promote side etching of the tungsten silicide layer.