JP5058406B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device.SetThe present invention relates to a manufacturing method, and more particularly to formation of a trench.
[0002]
[Prior art]
In recent years, miniaturization and high integration of semiconductor devices are progressing, and a technique for performing sub-quarter micron processing with high accuracy and high reproducibility is required.
In particular, the formation of high-precision and fine trenches has become an extremely important issue in order to increase the number of layers and the three-dimensionality of elements, including element isolation.
[0003]
When performing element isolation using a trench, if the corner of the trench opening is steep, there is a problem that it tends to cause electric field concentration of the MOSFET formed on the surface of the semiconductor substrate. As shown in FIG. 11, it is known that the shape of the trench, that is, the taper angle θ of the trench and the radius of curvature R of the upper portion of the trench have a great influence on the Id-Vg characteristics of the MOSFET.
[0004]
That is, in the case of a trench having a taper angle θ close to vertical and a small corner R, the Id-Vg characteristic of the MOSFET may exhibit a double hump characteristic. In order to avoid such a problem, the taper angle of the trench should be made gentle. However, when the isolation width of the element becomes finer, if the taper is made gentle, the trench cannot be formed deeper than the depth determined by the taper angle as shown in FIG. 12, and sufficient isolation performance is obtained. I can't do that. Further, in order to obtain a desired depth, it is necessary to make the opening diameter of the trench extremely large, which has been a big problem that prevents miniaturization.
[0005]
Therefore, in order to achieve both good transistor characteristics and isolation performance in a fine trench, as shown in FIG. 13, a gentle taper is formed only in the opening of the trench, and a steep angle is formed in other portions. Realization of a trench shape is desired.
[0006]
Conventionally, 1-5% oxygen O in hydrogen bromide HBr₂There has been proposed a method of obtaining a Y-shaped trench as shown in FIG. However, in this method, a gentle taper is formed in the vicinity of the upper portion of the trench. However, as shown in FIG. 14, there is a problem that the opening is not easily tapered and becomes steep.
[0007]
As shown in FIG. 15 (a), this is because SiN (Si_ThreeN_FourWhen etching for trench formation is performed through the mask 101, the etching must proceed while the polymer 102 is attached to the inner wall of the trench T from the initial stage of etching.₂, Cl₂/ O₂, Cl₂/ N₂In the process using the above, as shown in FIG. 15 (b), the reaction product SiCl_xAnd SiBr_xThe reaction with the oxygen radicals in the gas phase is started only after the gas is supplied to the gas phase, and deposition of the Si halide oxide begins. Therefore, SiCl into the gas phase_xAnd SiBr_xIn the stage before the start of supply, that is, in the initial stage of etching, a taper is hardly formed, and a steep profile is formed.
[0008]
Therefore, in order to form a taper from the initial stage of etching, it is necessary to supply deposition species from the gas phase.
Therefore, using an inductively coupled plasma etching apparatus as shown in FIG._xThere has been proposed a method of etching a Si substrate with Br while supplying radicals or ions to the substrate surface and depositing a fluorocarbon polymer. This equipment is Al₂O_ThreeA plasma 205 is generated between the ceramic dome 201 made of the above and a polyimide electrostatic chuck 202 as a lower electrode, and the surface of the silicon substrate 200 placed on the polyimide electrostatic chuck 202 is etched. A coil 204 connected to a 12.56 MHz high frequency power source is disposed outside the ceramic dome 201. The polyimide electrostatic chuck 202 is connected to a 13.56 MHz bias power source 203.
[0009]
Here, as a first step, the pressure in the chamber is set to 50 mtorr, source power 1200 W, bias power 200 W, HBr / CF_FourEtching is performed for 30 seconds with = 80/80 sccm.
[0010]
Next, as a second step, the pressure in the chamber is set to 40 mtorr, the source power is 1500 W, the bias power is 180 W, and HBr / Cl.₂/ O₂Etching is performed for 58 seconds with = 160/20/5 sccm. At this time, the temperature of the coolant for cooling the electrode was 50 ° C.
[0011]
When such a method is used, in order to form a sufficient forward taper, it is necessary to perform etching at a relatively high pressure. However, as a result of etching using the inductively coupled plasma etching apparatus, it was found that a residue was generated at a pressure of about 50 mtorr. If the etching pressure is lowered, the generation of the residue can be prevented, but there is a problem that the taper angle becomes large.
[0012]
Si_ThreeN_FourOr SiO₂HBr / CF using an etching mask made of_FourOr HBr / CHF_ThreeWhen performing the first etching step by the process, Si_ThreeN_FourOr SiO₂The etching selectivity with respect to is low, and the film thickness of the etching mask becomes severe. This is due to the F radical_ThreeN₄Or SiO₂This is because of etching. When etching is performed under the above conditions, Si_ThreeN_FourThe amount of film reduction of the etching mask made of was 20-32 m.
[0013]
Thus, Si_ThreeN_FourOr SiO₂The film thickness of the etching mask made of becomes severe. That is, in this method, there is a trade-off relationship between taper formation and residue generation prevention, residue generation prevention and mask film thickness reduction, and it was extremely difficult to obtain good results.
[0014]
[Problems to be solved by the invention]
As described above, in the conventional method, when trench etching is performed, there is a trade-off relationship between taper formation and residue generation prevention, residue generation prevention and mask film reduction reduction. There is a problem that it is extremely difficult to form a trench having a high degree of dimensional accuracy so as to be steep inside.
[0015]
The present invention has been made in view of the above circumstances, and an object thereof is to obtain a highly accurate and highly reliable trench having a gently tapered surface in the vicinity of an opening.
[0025]
[Means for Solving the Problems]
  First of the present invention1ThenA method of manufacturing a semiconductor device, wherein a trench sidewall of a trench formed on a surface of a semiconductor substrate has a first tapered surface having a gentle taper angle of 48.2 degrees to 59.0 degrees at a trench opening, and a predetermined taper surface A trench including a second tapered surface having a taper angle of 72.6 degrees or more that is steeper than the taper angle in a region deeper than the depth of the semiconductor substrate, and forming the trench on the semiconductor substrate surface, A first etching step for selectively etching the surface of a semiconductor substrate exposed from a mask using a mixed gas of hydrogen halide and fluorocarbon, wherein at least one of HCl, HBr, and HI and a general formula C _x H _y X _z (X ≧ 1, z ≧ 1, y ≧ 0, both are positive numbers, X is F or Br. C _x Br _y F _z (2x + 2 = y + z) may be used. ) Using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen after the first etching step, and a second etching step of etching the semiconductor substrate surface after the first etching step, After the second etching step, a third etching step for etching the surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas and oxygen is included.
[0026]
  According to such a configuration, the active species for forming the sidewall protective film is supplied from the plasma to the semiconductor substrate surface using a mixed gas of hydrogen halide and fluorocarbon to form a gently tapered surface,The mixed gas is one or more of HCl, HBr, and HI and a general formula C _x H _y X _z (X ≧ 1, z ≧ 1, y ≧ 0, both are positive numbers, X is F or Br. C _x Br _y F _z (2x + 2 = y + z) may be used. ) Is used.Thereafter, in the second etching step, a steep tapered surface is formed using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen. Then, in the third etching step, a hydrogen halide such as HBr is added to improve the etching selectivity with the mask, thereby preventing the occurrence of an abnormal shape of the side wall due to the reduction of the mask film. Also Cl₂By adding, etch stop can be prevented from occurring even in a narrow trench. Therefore, Cl₂/ HBr / O₂By executing the third etching step using the above, it is possible to obtain a desired depth even in a fine trench.
[0027]
  BookInventionSecondThenAccording to the first inventionIn the method for manufacturing a semiconductor device, the second etching step includes Cl.₂/ N₂Or Cl₂/ HBr / N₂It is a process using this.
  First of the present invention3ThenAccording to the first or second inventionIn the method of manufacturing a semiconductor device, the third etching step includes HBr, Cl₂And O₂It is an etching process using a mixed gas with.
[0028]
According to such a configuration, Cl₂As a result of this addition, the taper angle is increased, and even when a trench having a narrow opening diameter is formed, an etch stop can be prevented and a trench having a desired depth can be formed. In addition, the addition of HBr improves the etching selectivity with a mask such as a resist, and can prevent the mask from being reduced.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
First, as shown in FIG. 1, a silicon nitride film Si having a thickness of 170 nm is formed on the surface of the silicon substrate 1._ThreeN_FourAnd patterning to form a mask 2 made of a silicon nitride film.
[0038]
Then, a trench for element isolation is formed through this mask 2. As the apparatus, the inductively coupled plasma etching apparatus shown in FIG. 16 is used, the silicon substrate 1 is placed on a polyimide electrostatic chuck, and three-step etching is performed under the following conditions.
[0039]
Step 1: Etching is performed for 5 seconds using a mixed gas of pressure = 15 mTorr, source power: 1200 W, bias power: 100 W, HBr / CF 4 = 80/80 sccm.
[0040]
Step 2: Pressure = 15 mTorr, Source power: 1000 W, Bias power: 150 W, Cl₂/ N₂Etching for 15 seconds is performed using a mixed gas of = 125/50 sccm.
[0041]
Step 3: Pressure = 40 mTorr, Source power: 1500 W, Bias power: 180 W, HBr / Cl₂/ O₂Etching is performed for 50 seconds using a mixed gas of = 160/20/5 sccm.
[0042]
Here, the temperature of the coolant for electrode cooling is set to 50 ° C.
The etched shape thus obtained is shown in FIG. In this way, it is possible to obtain a gentle trench having a steep tapered surface in a region where the opening is gentle and deep.
[0043]
FIG. 3A is an enlarged photograph of the bottom surface of the trench thus formed. It can be seen that a smooth surface state can be obtained. Incidentally, an SEM photograph of the bottom surface of the trench formed by the conventional two-step etching (Japanese Patent Laid-Open No. 1-1118628) is shown in FIG. An SEM photograph of the silicon surface is shown in FIG. As apparent from the comparison between FIGS. 3B and 3C and FIG. 3A, the bottom surface of the trench formed by the conventional method is as shown in FIGS. 3B and 3C. The surface was uneven.
[0044]
First, the etching in step 1 is performed under the above conditions. In this step, it is desirable to set the pressure to 30 mTorr or less in order to prevent residue from being generated.
Further, in order to suppress the film loss of the mask, it is desirable that the source power is 1500 W or less and the bias power is 300 W or less.
[0045]
Furthermore, HBr / CF_FourThe flow rate ratio is considered to be usable in the range of 120: 40 to 40: 120 sccm. However, CF_FourWhen the ratio is high, the amount of film reduction of the mask increases.
[0046]
Note that the etching gas and the flow rate ratio may be selected so that a desired taper angle can be obtained.
[0047]
Next, for the second etching step, Cl₂And N₂It is desirable to select a gas composition capable of producing a reaction product that reacts with the halide of silicon and deposits on the substrate surface, without being limited to the mixed gas.
[0048]
As this gas combination, HBr + N₂, HBr + Cl₂+ O₂, HBr + Br₂+ O₂, Cl₂+ O₂+ N₂, HCl + N₂, HCl₂+ Cl₂+ N₂Etc. can be selected.
[0049]
In the third etching step, the gas is Cl.₂, HCl, Br₂, HBr, HI, etc. can be selected.
[0050]
The taper angle of the trench thus obtained was 48.2 degrees to 59.0 degrees, and the same as the designed value was obtained without variation. The variation was 11.8 degrees at most, and the taper angle of the trench formed by the conventional method was 45.7 degrees to 68.0 degrees, and the variation was 22.3 degrees.
[0051]
Next, in the third etching step, the taper angle was measured by changing the flow rate of chlorine. The result is shown in FIG. This is the taper angle of Cl when forming a 0.25 micron wide trench.₂The result of having measured flow rate ratio dependence is shown. Cl₂It can be seen that the taper angle is increased by increasing the addition amount of.
[0052]
Here, taper angle θ and maximum trench depth d at frontage W_maxIs expressed by the following equation.
d_max= (W / 2) tan θ
[0053]
FIG. 5 shows the trench taper angle dependence of the maximum trench depth.
From this equation, when the opening diameter of the trench is 200 nm, it is necessary to determine the etching process so that the taper angle is 72.6 degrees or more in order to make the trench depth 320 nm or more.
[0054]
Further, when the taper is gradually reduced to 100 nm in the vicinity of the opening and then trench etching is performed at a depth of 320 nm, the taper angle of the trench must be 81.1 degrees or more. To form a trench having a taper angle of 72.6 degrees or more with a trench having an opening diameter of 200 nm, Cl₂It can be seen that about 5% should be added. In order to form a trench having a taper angle of 72.6 degrees or more with a trench having an opening diameter of 100 nm, Cl is used.₂The addition ratio may be about 20%.
[0055]
As the trench becomes finer in this way, it is necessary to increase the taper angle of the second taper surface of the trench.₂It can be seen that a desired trench depth can be obtained with respect to a fine trench by controlling the addition amount of.
[0056]
Also, Cl₂/ O₂When etching with plasma, since the selectivity to the side wall polymer is low, the side wall polymer formed in the first etching step may be etched to expose the substrate, as shown in FIG. 6B. When the etching further proceeds, as shown in FIG. 6C, the portion where the side wall polymer 6 is removed is etched, and the silicon substrate is shaved. The trench sidewall formed by newly etching the silicon substrate has SiO₂Since the deposits of the system are deposited as the protective film 7, the portion of the silicon substrate protected by these films is not etched. For this reason, SiO₂The part protected by the reaction product 7 of the system forms a protruding side wall.
[0057]
Further, when the etching proceeds, a remarkable abnormal shape as shown in FIG.
On the other hand, in the first embodiment, since HBr is added in the third etching step, SiO₂, Si_ThreeN_Four, SiO₂Alternatively, the selectivity with respect to the resist is improved, and the occurrence of an abnormal shape can be prevented.
[0058]
Note that the mask film thickness D needs to be set in such a range that the trench width W and the aspect ratio (D / W) do not exceed 1. This is because when the aspect ratio exceeds 1, the coverage of the sidewall protective film begins to deteriorate rapidly when the opening is made gentle in the first etching step. If the aspect ratio can be 1 or less, Si_ThreeN_FourWithout being limited to photoresist and Si_ThreeN_FourIt can be modified as appropriate, such as a two-layer film.
[0059]
Further, the first etching step is preferably a mixed gas (X ≧ 1, Z ≧ 1, Y ≧) of any one or more of HCl, HBr, and HI and a gas represented by the general formula CxHyXz. 0 is a positive number, X is F or Br. CxBryFz (2x + 2 = y + z may be used) is used. And the gas ratio is HBr: CF_FourIs preferably 5: 3 to 3: 5. The process pressure is 30 mTorr or less. The etching time may be a time during which the silicon substrate surface is etched by a monoatomic layer or more.
[0060]
The second etching step is Cl₂/ N₂Or Cl₂/ HBr / N₂As an etching gas and Cl₂: N₂Is about 24: 3 to 25:10, Cl₂: HBr: N₂Is Cl₂: HBr is in the range of 0:10 to 10: 0, and N₂It is desirable to add 5 to 15%. The process pressure is 30 mtorr or less. The etching time may be a time for etching the surface of the silicon substrate by 30 nm or more.
[0061]
Furthermore, the third etching step is HBr / Cl₂/ O₂And Cl₂10 to 50%, O for ICP₂5 to 10%, O for ECR₂5 to 30% is added, and etching is continued until the etching amount necessary for element isolation is reached.
[0062]
Note that the source power has an ion current density of 0.5-3 mA / cm on the substrate.²As the power and bias power, the power at which Vpp is 40 V or higher or Vdc is 20 eV or higher in the substrate installation electrode is selected. The reason why Vdc is set to 20 eV or more is that ion energy of 20 eV or more is necessary to break the Si—Si bond. Moreover, although ion current density was 0.5-3 mA, when too high, there exists a problem that etching selectivity falls.
[0063]
Next, a second embodiment of the present invention will be described.
Although the three-step etching is used in the embodiment, this method is characterized by using two-step etching.
[0064]
First, as shown in FIG. 1, as in the first embodiment, a silicon nitride film Si having a thickness of 170 nm is formed on the surface of the silicon substrate 1._ThreeN_FourAnd patterning to form a mask 2 made of a silicon nitride film.
[0065]
Then, a trench for element isolation is formed through this mask 2. As the apparatus, the inductively coupled plasma etching apparatus shown in FIG. 16 is used, the silicon substrate 1 is placed on a polyimide electrostatic chuck, and two-step etching is performed under the following conditions.
[0066]
Step 1: Pressure = 15 mTorr, Source power: 1200 W, Bias power: 100 W, SiCl_Four/ N₂Etching is performed for 10 seconds using a mixed gas of 80/10 sccm. The gas flow ratio in this step 1 is N₂5 to 20%, preferably about 10%. SiCl_Four, N₂Cl mixed gas₂However, in order to obtain a good forward taper shape, the etching rate increases.₂The flow rate needs to be higher.
[0067]
Step 2: Step 3: Pressure = 40 mTorr, Source power: 1500 W, Bias power: 180 W, HBr / Cl₂/ O₂Etching is performed for 50 seconds using a mixed gas of = 160/20/5 sccm. This step was set to the same conditions as the third etching step of the first embodiment.
[0068]
Here, the temperature of the coolant for electrode cooling is set to 50 ° C.
The etching shape thus obtained was the same as that shown in FIG. In this way, it is possible to obtain a gentle trench having a steep tapered surface in a region where the opening is gentle and deep.
[0069]
Here, in the first etching step, SiCl_FourOther SiBr_Four, BCl_Three, BBr_ThreeEtc. are applicable.
The second etching step is similar to the third etching step of the first embodiment, and Cl₂Besides HCl, Br₂, HBr, HI, etc. are applicable.
[0070]
In addition to the inductively coupled plasma etching apparatus shown in FIG. 16, the etching apparatus can be applied to an ECR (electron cyclotron resonance) plasma etching apparatus as shown in FIG. Absent. This apparatus performs plasma etching on the surface of a silicon substrate 300 placed on a ceramic electrostatic chuck 302 as a lower electrode. A coil 304 connected to a high frequency power source is disposed outside the chamber 301. The ceramic electrostatic chuck 302 is connected to a 13.56 MHz bias power source 303.
[0071]
Here, the etching conditions using the ECR plasma etching apparatus were as follows.
[0072]
Step 1: Pressure = 1 mTorr, Source power (2.45 GHz microwave): 1400 W, RF power: 45 W, Cl₂/ N₂Etching is performed for 60 seconds using a mixed gas of 25/3 to 9 sccm.
[0073]
Step 2: Pressure = 2 mTorr, Source power (2.45 GHz microwave): 1500 W, RF power: 56 W, HBr / O₂= Etching for 50 seconds using a mixed gas of 100/6 sccm
[0074]
The trench shape thus obtained is shown in FIGS. These figures show N in the first etching step.₂It is a figure which shows a state when changing flow volume with 3, 6, and 9 sccm, respectively.
[0075]
From these results, it can be seen that the taper angle of the trench front can be controlled by changing the nitrogen flow rate. 8 to 10, it can be seen that a good taper angle can be obtained when the nitrogen flow rate is 3 to 6 sccm under the above-described etching conditions.
[0076]
Cl required to obtain the desired taper angle₂: N₂The flow rate ratio also depends on the process pressure, source power, and bias power, and must be optimized according to the etching conditions.
[0077]
  The following modes are also useful.
  In a semiconductor device, a trench is provided, and the trench side wall has a first tapered surface having a gentle taper angle of 48.2 degrees to 59.0 degrees at a trench opening, and a region deeper than a predetermined depth. And a second tapered surface having a taper angle of 72.6 degrees or more, which is steeper than the taper angle. According to such a configuration, it is possible to provide a highly reliable semiconductor device that maintains smoothness of the element and is smooth at the opening on the surface and without step breakage of the film formed on the surface.
Further, in the semiconductor device, the semiconductor substrate is a silicon substrate, and the trench has an insulating film formed on an inner wall to constitute an element isolation region, thereby causing problems such as current concentration. Thus, a fine and highly reliable semiconductor device can be formed.
In the semiconductor device, a capacitor is constituted by a diffusion layer formed on the inner wall of the trench, a dielectric film formed on the surface of the diffusion layer, and a conductive film formed on the surface of the dielectric film. The conductive film is formed so as to reach the semiconductor substrate surface from the opening end of the trench, or a gate electrode is formed on the inner wall of the trench via a gate insulating film. One of the source / drain diffusion regions is formed so as to reach the semiconductor surface from the vicinity of the opening of the trench, and constitutes a MOSFET having a part of the inner wall of the trench as a channel. You can also.
Also,A step of forming a trench on the surface of a semiconductor substrate is exposed from a mask using a mixed gas plasma of at least one gas of silicon halide and boron halide and at least one gas of oxygen or nitrogen. A first etching step for selectively etching the surface of the semiconductor substrate; and a second etching step for etching the surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen after the first etching step. And an etching process.
  According to this configuration, since silicon halide or boron halide and at least one gas of oxygen or nitrogen are added in the first etching step, silicon oxide, nitride, oxynitride or Since a compound serving as a sidewall protective film, such as boron oxide, nitride, or oxynitride, is supplied from plasma, the trench is formed so that the trench opening has a gentle tapered surface. Then, after the opening is gently formed in this way, it is possible to form a steep trench by performing etching using a halogen-containing gas.
  In the method of manufacturing a semiconductor device, the silicon halide is SiCl.₄, SiBr₄And the boron halide is BCl.₃, BBr₃It is either of these.
  In addition, the step of forming a trench on the surface of the semiconductor substrate includes halogen and / or hydrogen halide and organosilane (Si (CH₃)_xH_4-x) And oxygen or nitrogen mixed gas to selectively etch the surface of the semiconductor substrate exposed from the mask, and after the first etching step, a halogen-containing gas and oxygen or And a second etching step of etching the surface of the semiconductor substrate using a mixed gas plasma with nitrogen.
  According to this configuration, halogen and / or hydrogen halide and organosilane (Si (CH₃)_xH_4-x), A compound serving as a sidewall protective film, such as silicon oxide, nitride, or nitride oxide, is supplied from plasma, so that the trench opening has a gently tapered surface. A trench is formed in the step. Then, after the opening is gently formed in this way, it is possible to form a steep trench by performing etching using a halogen-containing gas.
  In the method for manufacturing a semiconductor device, the halogen may be Cl.₂, Br₂, I₂And the hydrogen halide contains at least one of HCl, HBr, and HI.
  In the method for manufacturing a semiconductor device, the halogen-containing gas may be Cl.₂, HCl, Br₂, HBr, and HI.
  In the method for manufacturing a semiconductor device, the organosilane gas may be tetramethylsilane: Si (CH₃)₄, Trimethylsilane: Si (CH₃)₃H, dimethylsilane: Si (CH₃)₂H₂It is either of these.
  A step of forming a trench on the surface of the semiconductor substrate, the first etching step of selectively etching the surface of the semiconductor substrate exposed from the mask using a halogen and / or a mixed gas of hydrogen halide and hydrocarbon; After the first etching step, the method includes a second etching step of etching the surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen.
  In the method for manufacturing a semiconductor device, the halogen may be Cl.₂, Br₂, I₂And the hydrogen halide contains at least one of HCl, HBr, and HI.
  In the method for manufacturing a semiconductor device, the halogen-containing gas may be Cl.₂, HCl, Br₂, HBr, and HI.
  In the above embodiment, the silicon nitride film is used as a mask, but a photoresist other than the silicon oxide film may be used.
[0078]
In the above embodiment, only the example of using this trench for element isolation has been described. However, the present invention is not limited to element isolation, but a trench type MOSFET having a trench sidewall as a gate and a trench capacitor having a trench sidewall as a capacitor. Is also applicable.
[0079]
When applied to a trench MOSFET, according to the present invention, a steep taper surface can be obtained in the vicinity of the trench opening and in the vicinity of the trench opening, resulting in disconnection of the wiring in the vicinity of the trench opening. Therefore, since an almost vertical surface can be used as a gate, the occupied area can be reduced, and a fine and highly reliable semiconductor device can be provided.
[0080]
Furthermore, when the trench bottom and / or trench sidewall is used as a capacitor, when the capacitor electrode is formed so as to extend to the substrate surface, or when connected to a circuit device formed on the substrate surface by wiring, the trench opening is used. Since a substantially vertical plane can be used as a capacitor while preventing disconnection of wiring near the portion, the occupied area can be reduced, and a fine and highly reliable semiconductor device is provided. It becomes possible.
[0081]
【The invention's effect】
As described above, according to the present invention, a fine and highly reliable trench can be formed, the area required for element isolation is small, and the element can be miniaturized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a trench formation process according to an embodiment of the present invention.
FIG. 2 is a diagram showing a trench formation process according to an embodiment of the present invention.
FIG. 3 is a photograph of a trench surface obtained in the same process and a photograph showing a trench surface formed by a conventional method.
FIG. 4 shows taper angle of trench and Cl.₂Diagram showing the relationship with addition amount
FIG. 5 is a graph showing the taper angle dependency of the maximum trench depth.
FIG. 6 is an explanatory view showing an etching process.
FIG. 7 is a diagram showing an ECR plasma etching apparatus.
8 is a photograph showing a trench shape when the nitrogen addition amount is changed using the etching apparatus of FIG.
9 is a photograph showing a trench shape when the nitrogen addition amount is changed using the etching apparatus of FIG.
10 is a photograph showing a trench shape when the amount of nitrogen added is changed using the etching apparatus of FIG.
FIG. 11 is an explanatory view showing a conventional trench.
FIG. 12 is an explanatory view showing a conventional trench.
FIG. 13 is an explanatory diagram showing an ideal trench shape.
FIG. 14 is an explanatory view showing a trench shape formed by a conventional method.
FIG. 15 is a view showing a trench forming process by a conventional method;
FIG. 16 shows an inductively coupled plasma etching apparatus.
[Explanation of symbols]
100 silicon substrate
101 mask
102 polymer
201 ceramic dome
202 Polyimide electrostatic chuck
203 Al₂O_Three
204 coils
205 plasma

Claims (3)

The trench sidewalls of the trench formed on the surface of the semiconductor substrate have a first taper surface having a gentle taper angle of 48.2 degrees to 59.0 degrees at the trench opening and the taper in a region deeper than a predetermined depth. A method of manufacturing a semiconductor device having a trench including a second taper surface having a taper angle of 72.6 degrees or more, which is steeper than an angle,
The step of forming a trench on the surface of the semiconductor substrate is a first etching step of selectively etching the surface of the semiconductor substrate exposed from the mask using a mixed gas of hydrogen halide and fluorocarbon, and includes HCl, HBr, HI. A mixed gas of at least one of these gases and a gas represented by the general formula C _x H _y X _z (x ≧ 1, z ≧ 1, y ≧ 0, both are positive numbers, X is F or Br A first etching step using C _x Br _y F _z (2x + 2 = y + z) may be used ;
A second etching step of etching the surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen after the first etching step;
A method for manufacturing a semiconductor device, comprising: a third etching step of etching the surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas and oxygen after the second etching step. The method of manufacturing a semiconductor device according to claim 1 , wherein the second etching step is a step using Cl ₂ / N ₂ or Cl ₂ / HBr / N ₂ . The third etching step, HBr and, and Cl _2, the method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that a mixed gas of O _2.

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