JP3397693B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an STI (Shallow Trench Isolation) structure for forming an element isolation structure.

[0002]

2. Description of the Related Art Conventionally, for isolation between elements in a semiconductor device, a LOCOS structure has been used in which a Si (silicon) substrate is thickly oxidized to form an isolation structure. However, in recent years, with the high integration of semiconductor devices, it has become necessary to use an STI structure in which a trench is formed in a silicon substrate and an insulating film is embedded in the trench to form an element isolation structure.

FIG. 5 shows an example of the LOCOS structure. The LOCOS structure forms an element isolation structure by directly oxidizing the silicon substrate 11 to be thick. At this time, since the oxidation proceeds in the depth direction of the silicon substrate 11 and the oxidation proceeds in the horizontal direction at the same time, an oxidized region 42 called bird's beak is formed in the horizontal silicon substrate 11. For this reason, it is necessary to have a margin for isolation between elements by the amount of this oxidized region 42, which has been a hindrance to high integration.

On the other hand, the STI structure shown in FIG.
A trench 50 is formed by directly etching the silicon substrate 11 substantially vertically, and the insulator 50 is embedded in the trench 50. Therefore, it becomes possible to form an isolation structure having a narrow element isolation interval, and it is possible to easily achieve high integration.

While having the above advantages, the STI structure has the following problems. That is, LOC
In the OS structure, since the silicon substrate 11 is directly oxidized, the end of the element region, for example, the end of the channel of the MOS transistor has a gentle round shape. On the other hand, STI
Since the structure etches the silicon substrate 11, it has a shape with corners at the ends of the element region. Therefore, the electric field from the gate electrode 15 is concentrated at the corner portion 51, and the channel is more easily turned on than the flat portion 52, and the corner portion 51 is turned on before the gate bias and the flat portion 5 is turned on.
2 has a characteristic of turning on with a delay. This is M
It is known as the kink characteristic of the OS transistor and the reverse narrow channel effect. These phenomena are
ElectronDevices Meeting Technical Digest 1998 edition p
p.92-95 and IEEE Transaction on Electron Devices, Vol.
35, NO.7 July 1988, pp.945-950, etc.

When this phenomenon occurs, the switching characteristics of the transistor are deteriorated, and when the channel width is narrowed, the threshold voltage is lowered, which may hinder the circuit design. That is, the switching characteristic is deteriorated because the channel of the corner portion 51 having a low threshold voltage is turned on first and the channel of the flat portion 52 is turned on with a delay, so that the rising characteristic of the drain current with respect to the gate voltage (S− Factor) is deteriorated. Further, as the channel width becomes narrower, the ratio of the corner portion 51 to the entire channel region increases, so that the characteristics of the corner portion 51 which is turned on first become mainly, and the threshold voltage of the transistor lowers. When actually designing a circuit, the amount of current is often controlled by the width of the channel, but if the characteristic is changed when designing with a reduced amount of current, the design becomes complicated.

[0007]

The most important cause of the above phenomenon is the insulator 14 embedded in the trench.
That is, the surface near the corner portion 51 becomes lower than the surface of the gate electrode, and the gate electrode 15 has a structure of covering the corner portion 51 of the trench. A process-related problem that causes such a structure will be described with reference to FIG.

As shown in FIG. 7A, the silicon substrate 1
1, a thermal oxide film 61 as a buffer material, a SiN film 62 that acts as a stopper in a CMP (chemical mechanical polishing) process for flattening the filling material of the trench, RIE
Si as a mask material for (reactive ion etching)
The O ₂ film 63 is sequentially formed, and a mask corresponding to the element region is formed.

Next, as shown in FIG. 7B, the silicon substrate 11 is etched to a desired depth using the above mask to form a trench 66. Thereafter, as shown in FIG. 7C, a filling material 64 made of an insulating material having a thickness sufficient to fill the trench is deposited. As shown in FIG. 7D, the filling material 64 is flattened to the stopper of the SiN film 62 by a CMP process.

After that, as shown in FIG.
The film 62 is peeled off, and then the thermal oxide film 61 is peeled off as shown in FIG. Since wet etching is used in this step, as shown in FIG. 9, the etching spreads in the lateral direction and the corner portion 51 of the silicon substrate 11 is exposed. The wet etching process is shown in FIG.
The surface of the insulating film 64 adjacent to the corner portion 51 is further lowered because it is necessary for the pretreatment at the time of forming the gate oxide film 65 shown in (c), and the concave portion 16 called a divot is formed. After that, when the gate electrode 15 is formed on the gate oxide film 65, as shown in FIG. 10, the corner portion 51 including the recess 16 is covered with the gate electrode 15 and the electric field concentration easily occurs. To some extent, the recess 16 is always present as long as a process of etching the burying material (in this case, an oxide film) is used in the step of forming the gate oxide film 65 after forming the STI, and the kink characteristic and the reverse narrow channel are present. Cause the effect.

Further, in order to solve the above-mentioned problem of electric field concentration, attempts have been made to round the corner regions. For example, International Electron Devices Meeting Technic
As described in al Digest, 1998 edition, pp.661-664, a high temperature thermal oxidation process after trench formation can round the corner regions. However, in order to obtain a sufficient amount of rounding, a long time oxidation process at high temperature is required,
The increase in stress in the substrate due to the oxidation itself causes the generation of defects and the increase of leak current. Further, since the diffusion of impurities becomes large, it cannot be used for a high-concentration embedded substrate or a process of forming a well in the substrate and forming a specific profile on the substrate before the STI process. Also,
There is a problem that the size of the round by oxidation depends on the above-mentioned thermal process and thus the structure cannot be freely changed.

The present invention has been made to solve the above problems, and an object of the present invention is to prevent the threshold voltage at the channel corner from lowering by relaxing the electric field concentration from the gate of the MOS transistor. However, it is another object of the present invention to provide a semiconductor device capable of obtaining good switching characteristics and a manufacturing method thereof.

[0013]

The semiconductor device of the present invention comprises:
A semiconductor substrate and an element region formed in the semiconductor substrate
And a trench formed adjacent to the
And an insulator for separating the device region from each other.
First sloping slop formed on top of wrench sidewall
And the bottom of the trench from the bottom of this first slope
The second sloped part having a steep slope following the part and the element region
The element is formed up to the middle of the surface and the first inclined portion,
The cord having a gentle angle formed by the surface of the region and the first inclined portion
And a gate electrode that covers the gate portion.

The method for manufacturing a semiconductor device of the present invention is a semiconductor
A first step of forming a mask on the device region of the substrate, and
The first etching that produces a large amount of deposit using the mask
The semiconductor substrate is etched under the conditions, and the slope is gentle.
Forming a slanted part of the
The second step of depositing the deposit and the deposit
Second etching condition that is used as a mask and does not generate deposits
Etch the semiconductor substrate to a predetermined depth with
And a third step of forming a steep second inclined portion
However, the second etching condition is the first etching condition.
Depending on the conditions, the temperature during etching is set higher.

The method of manufacturing a semiconductor device of the present invention is a semiconductor
On the device area of the substrate,
First step of forming a mask and using the first mask
Etching the semiconductor substrate and the first mask
The semiconductor substrate is formed under the first etching condition with a low selectivity.
Second etching to form a first slope having a gentle slope
And the third step of forming the mask material on the entire surface,
The mask material is etched to form side surfaces of the first mask.
A fourth mask forming a second mask covering the first sloped portion;
Process, and using the first and second masks, the semiconductor substrate
A second plate having a high etching selectivity between the plate and the second mask
Under the above etching conditions, the semiconductor substrate is etched to a predetermined depth.
The second slope, which is steeper than the first slope.
A fifth step of forming an inclined portion,
The etching conditions are the same as the second etching conditions.
While increasing the power of the high frequency signal at the time of
Process pressure is set low.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 (a) and 1 (b) show a first embodiment of the present invention, and FIG. 1 (b) is shown in FIG.
1 (b) -1 (b) of FIG. A trench 11a that forms an element isolation region is formed in the silicon substrate 11, and an insulating film 14 is buried inside the trench 11a. A gate electrode 15 is formed on the element region 11b, and impurities are introduced into the silicon substrate 11 located on both sides of the gate electrode 15 as shown in FIG. Are formed. The sidewall of the trench 11a is formed as shown in FIG.
As shown in (b), the first sloped portion 12 having a gentle slope (taper) from the upper end of the trench and the first sloped portion 12
Has a second slope 13 having a steep slope from the lower end to the bottom of the trench. The surface of the insulating film 14 is set higher than the surface of the element region 11b, for example, and a recess 16 called a divot is formed in a portion of the insulating film 14 facing the first inclined portion 12. The bottom of the recess 16 reaches almost the middle of the first inclined portion 12. The gate electrode 15 enters the recess 16,
A gate electrode 15 covers a loose corner located at the boundary between the first inclined portion 12 and the surface of the element region 11b.

The first slanted portion 12 having a gentle slope is
As shown in Figure 1 (a), are formed around the element region 11b, portions necessary to achieve the object of the present invention are only partially in contact with the gate electrode 15.

FIG. 2 is an enlarged view of the main part of FIG. 1 (b). The angle α formed by the surface of the element region 11b and the first inclined portion 12 is the steep second inclined portion 13 and the trench 11a.
The angle may be larger than the angle β formed by the bottom of the above and 180 ° or less. The angle α formed by the surface of the element region 11b and the first inclined portion 12 is infinitely 18 if the depth of the recess 16 is shallow.
It can approach 0 °. The angle α is larger than the angle β to some extent, and if the first inclined portion 12 at the upper part of the trench is loose, the electric field concentration in the corner region covered by the gate electrode can be relaxed, and a phenomenon such as a kink characteristic or an inverse narrow channel effect can be achieved. Can be relaxed.

However, the first sloped portion 12 having a loose trench
In the case of using only one, the separation distance between elements becomes very large, and it becomes difficult to achieve high integration. Therefore, it is necessary to make the region of the gentle taper to a depth necessary for satisfying the above condition, and to make the depth deeper than that to make the separation distance between the elements steep.

Next, a method of manufacturing the trench having the first and second inclined portions will be described. [First Embodiment] In order to form the structure shown in FIG.
In this embodiment, the etching for forming the STI structure trench is performed in two steps. That is, in the first step, the silicon substrate is etched to a predetermined depth under the first RIE condition where the taper becomes loose, and in the second step, under the second RIE condition where the taper is steep, the silicon substrate is further etched to a depth sufficient for element isolation. The silicon substrate is being etched.

FIG. 3 shows a manufacturing process of the trench according to the first embodiment. As shown in FIG. 3A, a mask 21 corresponding to the element region is formed on the silicon substrate 11 by using a photoresist process and an RIE process.
The mask 21 may be formed of a material having an etching selection ratio with the silicon substrate 11, and is usually formed of, for example, a silicon oxide film (SiO ₂ ) having a film thickness of about 200 nm. In an actual process, a filling material is deposited after the trench is formed, and a silicon nitride film (Si) is used as a stopper material when flattening the filling material by a technique such as CMP.
N) etc. are often used. Therefore, a double structure may be used in which a silicon nitride film is formed under the silicon oxide film as the mask material. In the actual process, the above-mentioned double structure of SiN / SiO ₂ or a multilayer film structure having more than that may be taken, but since it is not important for explaining the purpose of this embodiment, it is simplified in this embodiment. Therefore, a single structure of the silicon oxide film will be described.

Next, as shown in FIG. 3B, the mask 2
1 is used, and the silicon substrate 11 is slightly etched using the first RIE condition for forming a gentle slope to form the gentle first slope 12. The inclination angle of the trench sidewall is controlled by changing the first RIE condition. That is, the etching of the silicon substrate 11 is, for example, HBr / Cl2 / O ₂ or HBr / O ₂ or the like of the gas used. The inclination angle of the trench sidewall is determined by the ratio of the rate at which a halide such as SiBrxHy generated during etching by RIE is deposited on the mask 21 or the sidewall of the etched trench and the rate at which the RIE ions are sputtered. It is possible to form a trench shape having a steep slope by using a condition that the deposition rate of the halide is larger, and vice versa. For example, under the HBr-based etching conditions, the higher the temperature of the wafer during the process, the less the amount of the deposit 22, and the lower the temperature of the deposit, the amount of the deposit 22.
Is generated a lot. In a general RIE apparatus, the process temperature can be controlled in the temperature range from about 0 ° C. to about a hundred and several tens of degrees C. Therefore, for example, the amount of the deposit 22 is controlled by changing the process temperature during RIE, and the trench sidewalls are controlled. The slope of can be changed. That is, in order to form the first inclined portion 12, the wafer temperature during the process is set to a low value within the above range, and a large amount of the deposit 22 is formed. These phenomena are, for example, CYChang,
It is described in detail in the etching section of ULSI TECHNOLOGY (McGRAWHILL) by SMSze et al.

As described above, by depositing the deposit 22 on the mask 21 and the side wall of the trench by etching, the gentle first inclined portion 12 can be provided in the trench. Next, as shown in FIG. 3C, the first RIE is performed.
The silicon substrate 11 is etched to a desired trench depth by switching to the second RIE condition in which the deposit 22 generated under the conditions is used as a mask and a side wall having a steep slope is formed. The second RIE condition is set so that the process temperature is higher than that of the first RIE condition so that deposits are not generated during etching. At this time, since the deposit 22 generated by the first RIE condition remains on the upper part of the trench, the upper part of the trench has the gentle first inclined part 12, and the lower part has the second inclined part 13 having a steep inclination. A trench structure having can be formed.

Thereafter, the mask 21 is subjected to, for example, hydrofluoric acid treatment.
To remove. At this time, since the deposit 22 made of a halide deposited on the upper portion of the trench can be removed at the same time, a trench structure as shown in FIG. 3D can be formed.

Although only the step of forming the trench having the first and second inclined portions 12 and 13 has been described in the first embodiment, for example, the step shown in FIG.
A MOS transistor is formed through the same steps as shown in FIGS. 8C, 8D, 8A, 8B, and 8C. According to the first embodiment, the gentle first sloped portion 12 and the steep second sloped portion 13 are formed by changing the etching conditions, for example, the process temperature when forming the trench by RIE. This manufacturing method is easy to manufacture because there is no need to add a new process or change the design of the mask pattern, and the first inclined portion 12 can prevent the electric field from concentrating and have good characteristics. A transistor having the same can be formed.

Further, since the side wall of the trench located at the channel corner portion covered by the gate electrode of the transistor is made gentle, the electric field concentration from the gate electrode can be relaxed, and the channel corner of the transistor peculiar to the STI structure can be relaxed. It is possible to prevent the threshold voltage of a part from lowering. Therefore, it is possible to prevent deterioration of the switching characteristics of the transistor peculiar to the STI structure, and it is possible to suppress a decrease in the threshold voltage of the transistor when the transistor is miniaturized and the channel width is narrowed.

Moreover, since the sidewalls of the trench are steeply inclined in a region deeper than the channel region, it is possible to obtain an STI structure which is sufficiently deep and has a narrow element isolation space, which enables high integration of elements. .

[Second Embodiment] In the first embodiment, the deposit 22 formed on the side wall of the sloped portion 12 having a gentle slope is used as a mask under the second RIE condition in which the next steep slope is obtained. However, as described above, the second RIE condition is nothing but the condition that the ratio of the deposit 22 generated during etching and the rate of sputter etching the same is the same. That is, the second
Under the above RIE condition, the sidewall deposit 22 formed under the first RIE condition is also likely to be etched at the same time. This time,
If the size of the initial sidewall deposit 22 is not sufficient for the depth of the trench formed by the second RIE, it becomes difficult to obtain the desired trench structure. This second embodiment takes this into account and provides a process that is able to adequately protect the first sloping region regardless of the second RIE condition.

That is, in the first embodiment, the trench having the first and second inclined portions is formed by controlling the temperature of the wafer during the process, but in the second embodiment,
By controlling the power of RF (high frequency signal) during RIE and the pressure in the chamber during the process, the trench having the first and second inclined portions is formed.

Specifically, the RIE condition is such that the etching selection ratio between the silicon substrate and the mask made of a silicon oxide film (SiO ₂ ) is low. In RIE, if the RF power during RIE is increased or the pressure during the process is decreased, the etching selectivity between the silicon substrate and the silicon oxide film decreases. That is, for example, a gentle slope can be formed by etching under conditions of high RF power and low pressure.

Under this condition, since the mask made of the silicon oxide film is also laterally etched at the same time as the etching of the silicon substrate proceeds, the mask width becomes gradually smaller. Therefore, etching is first started, and finally, the trench width is narrow in the deep part of the trench, and the trench width is wide in the part in contact with the mask, so that the trench shape having the inclined sidewall can be obtained.

FIG. 4 shows a manufacturing process of a trench according to the second embodiment. First, as shown in FIG. 4A, a first mask 31 made of, for example, a silicon oxide film is formed corresponding to the element region on the silicon substrate 11.
However, since the first mask 31 uses the conditions as described above to control the inclination, it is necessary to form a thick film thickness and a large pattern width in consideration of the amount of etching.

Next, using this first mask 31,
The silicon substrate 11 is etched under the RIE conditions. The first RIE condition is, for example, high RF power,
The pressure is low. By etching the silicon substrate 11 and the mask 31 under these conditions, as shown in FIG.
As shown in (b), the first inclined portion 12 having a gentle inclination can be formed to a predetermined depth.

Next, as shown in FIG. 4C, a film 32 to be a second mask is deposited on the entire surface. This film 32 is the first
The same silicon oxide film as the mask 31 may be used, or a substance different from the silicon oxide film, such as a silicon nitride film, which has a selection ratio with the first mask 31 in the sidewall formation process described later may be used.

Next, as shown in FIG. 4D, the film 32 is etched by RIE to form a second mask 33 on the side wall of the first mask so as to cover the first inclined portion 12. .

Thereafter, as shown in FIG. 4E, the second mask 33 is used to form a second RIE having a steep slope.
By changing the conditions, the silicon substrate 11 is etched to a desired trench depth to form the second sloped portion 13 having a steep slope. As the second RIE condition, for example, when the RF power during RIE is lowered or the pressure during the process is raised, the etching selectivity between the silicon substrate and the silicon oxide film increases. That is, for example, a steep slope can be formed by etching under conditions of low RF power and high pressure.

After that, the first mask 31 and the second mask 33 are removed by the same process as in the first embodiment, whereby a trench as shown in FIG. 3D can be formed. Further, after the step of FIG. 4 (e), an element isolation structure is formed by performing a normal STI formation process, and a gate oxide film and a gate are formed to obtain a transistor structure as shown in FIG.

According to the second embodiment, after forming the first inclined portion 12 under the first RIE condition using the mask 31 which is larger than the element region to be finally formed and has a large film thickness. A second mask 33 that protects the first inclined portion 12 is formed to form a trench having a steep second inclined portion 13. Therefore, the first inclined portion 12
The desired STI structure can be formed in a state where the STI structure is sufficiently protected.

Further, by changing the etching conditions during the formation of the trench by RIE, a new process for forming a gentle first sloped portion and a steep second sloped portion is added, and a mask pattern is designed. It does not need to be changed and is easy to manufacture.

The present invention is not limited to the above embodiment. For example, S as shown in FIG.
In the TI structure transistor, the height of the surface of the silicon substrate 11 as the element region may be higher than that of the embedded insulating film 14. Even with such a configuration, since the gate electrode covers the gently inclined corner portion, the concentration of the electric field can be prevented. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[0041]

As described above, according to the embodiments of the present invention, the concentration of the electric field from the gate of the MOS transistor is alleviated to prevent the threshold voltage of the channel corner from lowering and obtain good switching characteristics. It is possible to provide a semiconductor device and a method for manufacturing the same.

[Brief description of drawings]

FIG. 1A is a plan view of a transistor having an STI structure according to the present invention, and FIG. 1B is a plan view of FIG. 1A.
Sectional drawing which followed the (b) -1 (b) line.

FIG. 2 is an enlarged view of a main part of FIG.

FIG. 3 is a cross-sectional view showing a first embodiment of the manufacturing process of the semiconductor device according to the present invention.

FIG. 4 is a sectional view showing a second embodiment of the manufacturing process of the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view of a transistor having a conventional LOCOS structure.

FIG. 6 is a sectional view of a conventional STI structure.

FIG. 7 is a cross-sectional view showing a process of forming a conventional STI structure.

FIG. 8 is a cross-sectional view showing a process of forming a conventional STI structure.

FIG. 9 is a cross-sectional view showing how a divot is formed by wet etching.

FIG. 10 is a sectional view showing a relationship between a divot and a gate electrode.

[Explanation of symbols]

11 ... Silicon substrate, 11a ... trench, 12 ... the first inclined portion, 13 ... the second inclined portion, 14 ... Insulating film, 15 ... Gate electrode, 16 ... recess (divot), 21 ... Mask, 22 ... sediment, 31 ... the first mask, 33 ... A second mask.

Claims (4)

(57) [Claims] 1. A semiconductor substrate, a trench formed in the semiconductor substrate and adjacent to an element region, an insulator filled in the trench for separating the element region, and a trench of the trench. the slope formed on the upper portion of the side wall is loose 1
Inclined portion, and forming a lower portion of the first inclined portion to the middle of the second inclined portion bottom following the slope is steep and, with the surface of the device region of the first inclined portion of the trench
It is, wherein a and this <br/> having a gate electrode which covers the corner portions of loose angle with the surface of the device region and said first inclined portion forms. 2. The angle formed by the surface of the element region and the first inclined portion is larger than the angle formed by the second inclined portion and the bottom of the trench and is 180 ° or less. The semiconductor device according to claim 1. 3. A first step of forming a mask on an element region of a semiconductor substrate; a first slope having a gentle slope, wherein the semiconductor substrate is etched under a first etching condition in which a large amount of deposits are produced using the mask. A second step of forming the slanted portion of the first slanted portion and depositing the deposit on the first slanted portion; and a second step in which the deposit is not used as a mask.
The semiconductor substrate is etched to a predetermined depth under the above etching conditions to form a second sloped portion having a steep slope.
And the second etching condition is the first etching condition.
The etching temperature is set higher than the etching conditions of
A method of manufacturing a semiconductor device, comprising: 4. A first step of forming a first mask, which is slightly larger than the element region, on the element region of the semiconductor substrate; and using the first mask, the semiconductor substrate and the first mask are formed. A second step of etching the semiconductor substrate under a first etching condition having a low etching selection ratio to form a first inclined portion having a gentle inclination; a third step of forming a mask material on the entire surface; and the mask Etching a material to form a second mask that covers a side surface of the first mask and the first inclined portion;
And the first and second masks are used to etch the semiconductor substrate to a predetermined depth under a second etching condition in which the etching selection ratio between the semiconductor substrate and the second mask is high, A fifth step of forming a second sloped portion having a steeper slope than the first sloped portion , wherein the first etching condition is the second etching condition.
Depending on the conditions, the power of high frequency signal during etching can be increased.
At the same time, the process pressure is set low, and the method for manufacturing a semiconductor device is characterized.