JP2000022141A - Semiconductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To relieve conversion of electric field from a gate electrode and to suppress the deterioration of switching characteristics and threshold voltage of a transistor having a narrow channel. SOLUTION: A trench 11a has sidewalls comprising a first gentle inclination 12 and a steep inclination 13 which extends from the foot of the first inclination 12 toward the bottom of the trench 11a. A gate electrode 15 covers a gentle corner part formed by the first inclination 12 and the surface of a device region 11b. In this way, the conversion of electric field in the corner is relaxed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an STI (Shallow Trench Isolation) structure for forming an element isolation structure.

[0002]

2. Description of the Related Art Conventionally, a LOCOS structure in which a Si (silicon) substrate is thickly oxidized to form an isolation structure has been used for isolation between elements in a semiconductor device. However, in recent years, with the increase in the degree of integration of semiconductor devices, it has become necessary to use an STI structure in which a trench is formed in a silicon substrate and an insulating film is buried in the trench to form an element isolation structure.

FIG. 5 shows an example of a LOCOS structure. In the LOCOS structure, an element isolation structure is formed by directly oxidizing the silicon substrate 11 to a large thickness. At this time, the oxidation proceeds in the horizontal direction at the same time as the oxidation proceeds in the depth direction of the silicon substrate 11, so that an oxidized region 42 called a bird's beak is formed in the silicon substrate 11 in the horizontal direction. For this reason, it is necessary to provide a margin for isolation between elements by the amount of the oxidized region 42, which hinders high integration.

On the other hand, the STI structure shown in FIG.
The trench 50 is formed by directly etching the silicon substrate 11 substantially vertically, and the insulator 50 is embedded in the trench 50. For this reason, it is possible to form an isolation structure with a small element isolation interval, and it is possible to easily achieve high integration.

[0005] While having the above advantages, the STI structure has the following problems. That is, LOC
In the OS structure, since the silicon substrate 11 is directly oxidized, the end of the element region, for example, the end of the channel of the MOS transistor has a gentle round shape. In contrast, STI
The structure has a shape with a corner at the end of the element region for etching the silicon substrate 11. Therefore, the electric field from the gate electrode 15 is concentrated at the corner portion 51, so that the channel is more easily turned on than the flat portion 52, and the corner portion 51 is turned on before the gate bias and the flat portion 5 is turned on.
2 has a characteristic of turning on with a delay. This is M
This is known as a kink characteristic of an OS transistor or an inverse narrow channel effect. These phenomena are
ElectronDevices Meeting Technical Digest 1998 Edition p
p.92-95 and IEEE Transaction on Electron Devices, Vol.
35, NO.7 July 1988, pp.945-950.

When this phenomenon occurs, the switching characteristics of the transistor deteriorate, and when the channel width becomes narrow, the threshold voltage becomes low, which may hinder circuit design. That is, the deterioration of the switching characteristics means that the channel of the corner portion 51 having a low threshold voltage is turned on first, and the channel of the flat portion 52 is turned on with a delay. Factor) is degraded. In addition, as the channel width becomes narrower, the ratio of the corner portion 51 to the entire channel region increases, so that the characteristic of the corner portion 51 which is turned on first becomes dominant and the threshold voltage of the transistor decreases. In actual circuit design, the amount of current is often controlled by the width of the channel. However, when the design is performed with a reduced amount of current, the characteristics are changed and the design becomes complicated.

[0007]

The most important cause of the above-mentioned phenomenon is that the insulator 14 buried in the trench is not used.
In this case, the surface near the corner portion 51 is lower than the surface of the trench, and the gate electrode 15 covers the corner portion 51 of the trench. A process problem in which such a structure occurs will be described with reference to FIG.

[0008] As shown in FIG.
1, a thermal oxide film 61 as a buffer material, a SiN film 62 acting as a stopper in a CMP (chemical mechanical polishing) process for flattening a filling material of the trench, an RIE
Si as a mask material for (reactive ion etching)
An O ₂ film 63 is sequentially formed, and a mask corresponding to the element region is formed.

Next, as shown in FIG. 7 (b), the trench 66 is formed by etching the silicon substrate 11 to a desired depth using the mask. Thereafter, as shown in FIG. 7C, a burying material 64 made of an insulator having a thickness enough to bury the trench is deposited. As shown in FIG. 7D, the filling material 64 is flattened to the stopper of the SiN film 62 by a CMP process.

[0010] Thereafter, as shown in FIG.
The film 62 is peeled off, and then the thermal oxide film 61 is peeled off as shown in FIG. Since wet etching is used in this step, as shown in FIG. 9, the etching also spreads in the horizontal direction, and the corner portion 51 of the silicon substrate 11 is exposed. The wet etching process is shown in FIG.
The surface of the insulating film 64 adjacent to the corner portion 51 is further lowered because it is necessary for the pre-treatment or the like at the time of forming the gate oxide film 65 shown in (c), and the concave portion 16 called a divot is formed. Thereafter, when the gate electrode 15 is formed on the gate oxide film 65, as shown in FIG. 10, the corner portion 51 including the concave portion 16 is covered with the gate electrode 15, and a structure in which electric field concentration is likely to occur occurs. The concave portion 16 is present to a certain extent as long as a process of etching a burying material (in this case, an oxide film) is used in the step of forming the gate oxide film 65 after the STI is formed. Causes effects.

Further, in order to solve the above-mentioned problem of electric field concentration, attempts have been made to round a corner region. For example, International Electron Devices Meeting Technic
As described in al Digest, 1998 edition, pp. 661-664, corner regions can be rounded by performing a high temperature thermal oxidation process after trench formation. However, in order to obtain a sufficient rounding amount, a long-time oxidation step at a high temperature is required.
An increase in stress in the substrate due to the oxidation itself causes generation of defects and an increase in leak current. Furthermore, since the diffusion of impurities becomes large, it cannot be used for a high-concentration buried substrate or a process in which a well is formed in the substrate before the STI process and a specific profile is formed on the substrate. Also,
Since the size of the round due to oxidation depends on the heat process, there is a problem that the structure cannot be freely changed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to prevent concentration of an electric field from the gate of a MOS transistor from lowering a threshold voltage at a channel corner. It is another object of the present invention to provide a semiconductor device capable of obtaining good switching characteristics and a method for manufacturing the same.

[0013]

The present invention uses the following means to achieve the above object. The semiconductor device of the present invention includes a semiconductor substrate, a trench formed in the semiconductor substrate, formed adjacent to an element region, and an insulator filled in the trench to isolate the element region. The side wall of the trench includes a first slope portion having a gentle slope formed at an upper portion of the trench and the first slope portion.
And a second inclined portion having a steep inclination extending from a lower portion of the inclined portion to a bottom portion of the trench, and a gentle angled corner formed by the surface of the element region and the first inclined portion is formed by a gate electrode. Covered.

The angle formed by the surface of the element region and the first inclined portion is larger than the angle formed by the second inclined portion and the bottom of the trench, and is 180 ° or less. According to a semiconductor manufacturing method of the present invention, a first step of forming a mask on an element region of a semiconductor substrate, and using the mask, the semiconductor substrate is etched under a first etching condition in which a large amount of deposits are formed, A second step of forming a loose first slope and depositing the deposit on the first slope;
And a third step of using the deposit as a mask and etching the semiconductor substrate to a predetermined depth under a second etching condition in which no deposit occurs, thereby forming a second inclined portion having a steep inclination. And

The first etching condition and the second etching condition are characterized in that the temperature at the time of etching is different. A semiconductor manufacturing method according to the present invention includes a first step of forming a first mask slightly larger than an element region on an element region of a semiconductor substrate, and using the first mask to form the first substrate and the first substrate. A second step of etching the semiconductor substrate under a first etching condition having a low etching selectivity with a mask to form a first inclined portion having a gentle inclination;
A third step of forming a mask material on the entire surface; a fourth step of etching the mask material to form a second mask covering the side surface of the first mask and the first inclined portion; Using the first and second masks, the semiconductor substrate is etched to a predetermined depth under a second etching condition in which the etching selectivity between the semiconductor substrate and the second mask is high, and A fifth step of forming a second inclined portion having a steep inclination.
The first etching condition is set so that the power of the high-frequency signal is higher and the process pressure is lower than the second etching condition.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIGS. 1A and 1B show a first embodiment of the present invention, and FIG.
2 shows a cross section along line 1 (b) -1 (b). A trench 11a forming an element isolation region is formed in the silicon substrate 11, and an insulating film 14 is buried in the trench 11a. On the element region 11b, a gate electrode 15 is formed. On the silicon substrate 11 located on both sides of the gate electrode 15, as shown in FIG. Are formed. The side wall of the trench 11a is shown in FIG.
As shown in (b), a first inclined portion 12 whose inclination (taper) is gentle from the upper end of the trench, and the first inclined portion 12
And a second slope 13 having a steep slope extending from the lower end to the bottom of the trench. The surface of the insulating film 14 is set, for example, higher than the surface of the element region 11b, and a concave portion 16 called a divot is formed in a portion of the insulating film 14 facing the first inclined portion 12. The bottom of the concave portion 16 reaches almost halfway of the first inclined portion 12. The gate electrode 15 enters the recess 16,
A gentle corner located at the boundary between the first inclined portion 12 and the surface of the element region 11b is covered with the gate electrode 15.

The first inclined portion 12 having a gentle inclination is
As shown in FIG. 1A, the portion formed around the element region 11b is only necessary to achieve the object of the present invention in contact with the gate electrode 15.

FIG. 2 is an enlarged view of a main part of FIG. The angle α formed between the surface of the element region 11b and the first inclined portion 12 is steep between the second inclined portion 13 and the trench 11a.
It is sufficient that the angle is larger than the angle β formed by the bottom and 180 ° or less. The angle α formed by the surface of the element region 11b and the first inclined portion 12 is 18 if the depth of the concave portion 16 is small.
0 ° can be approached. The angle α is somewhat larger than the angle β, and if the first inclined portion 12 above the trench is loose, the electric field concentration in the corner region covered by the gate electrode can be reduced, and phenomena such as kink characteristics and an inverse narrow channel effect can be achieved. Can be alleviated.

However, the first sloping portion 12 is formed by loosening the trench.
In the case of using only the elements, the separation distance between the elements becomes extremely large, and it is difficult to achieve high integration. For this reason, the region of a gentle taper needs to be a depth necessary to satisfy the above condition, and a larger depth needs to have a steep taper in order to shorten the separation distance between elements.

Next, a method of manufacturing the trench having the first and second inclined portions will be described. [First Embodiment] In order to form the structure shown in FIG.
In this embodiment, the etching for forming the trench having the STI structure is performed in two steps. That is, in the first step, the silicon substrate is etched to a predetermined depth under the first RIE condition in which the taper is loosened, and in the second step, the silicon substrate is etched to a depth sufficient for element isolation under the second RIE condition in which the taper is sharp. The silicon substrate is being etched.

FIG. 3 shows a manufacturing process of the trench according to the first embodiment. As shown in FIG. 3A, a mask 21 corresponding to an element region is formed on a silicon substrate 11 by using a photoresist process and an RIE process.
The mask 21 may be formed of a material having an etching selectivity with respect to the silicon substrate 11, and is usually formed of, for example, a silicon oxide film (SiO ₂ ) having a thickness of about 200 nm. In an actual process, a filling material is deposited after forming a trench, and a silicon nitride film (Si) is used as a stopper material when the filling material is planarized by a technique such as CMP.
N) and the like are often used. For this reason, a double structure in which a silicon nitride film is formed under a silicon oxide film as the mask material may be used. In an actual process, a double structure of SiN / SiO ₂ or a multi-layer structure of more than that described above may be adopted. However, it is not important for explaining the purpose of the present embodiment, and therefore, it is simplified in the present embodiment. Therefore, the description will be made with a single structure of a silicon oxide film.

Next, as shown in FIG.
1 and the first RIE condition for forming a gentle slope is used to slightly etch the silicon substrate 11 to form a gentle first slope 12. By changing the first RIE condition, the inclination angle of the trench side wall is controlled. That is, a gas such as HBr / Cl2 / O ₂ or HBr / O ₂ is used for etching the silicon substrate 11. The inclination angle of the trench side wall is determined by the ratio of the rate at which a halide such as SiBrxHy generated during etching by RIE is deposited on the mask 21 or the side wall of the etched trench, and the rate at which sputtering is performed by RIE ions. When a condition where the halide deposition rate is higher is used, a slope is gentle, and when a condition where the sputter rate is higher is used, a trench shape with a steep slope can be formed. For example, under the HBr-based etching conditions, the deposit 22 decreases as the wafer temperature during the process increases, and the deposit 22 decreases as the wafer temperature during the process decreases.
Are often generated. In a general RIE apparatus, the process temperature can be controlled in a temperature range from about 0 ° C. to about one hundred and several tens of degrees Celsius. Therefore, for example, the amount of the deposit 22 is controlled by changing the process temperature during RIE, and the trench sidewall is controlled. Can be changed. That is, in order to form the first inclined portion 12, the temperature of the wafer during the process is set to be low in the above range, so that a large amount of the deposit 22 is formed. These phenomena are, for example, CYChang,
It is described in detail in the etching section of ULSI TECHNOLOGY (McGRAWHILL) by SMSze et al.

As described above, since the deposit 22 is deposited on the mask 21 and the side walls of the trench by etching, the first inclined portion 12 which is loose in the trench can be provided. Next, as shown in FIG. 3C, the first RIE
The silicon substrate 11 is etched to a desired trench depth by switching to the second RIE condition using the deposit 22 generated under the condition as a mask and forming a steep side wall. In the second RIE condition, the process temperature is set higher than that in the first RIE condition, so that no deposit is generated during etching. At this time, since the deposit 22 generated under the first RIE condition remains in the upper part of the trench, the upper part of the trench has the first inclined part 12 which is gentle, and the lower part has the second inclined part 13 whose inclination is steep. Having a trench structure.

Thereafter, the mask 21 is subjected to, for example, a hydrofluoric acid treatment or the like.
Is removed. At this time, since the deposit 22 composed of a halide deposited on the upper portion of the trench can be removed at the same time, a trench structure as shown in FIG. 3D can be formed.

In the first embodiment, only the step of forming a trench having the first and second inclined portions 12 and 13 has been described. However, for example, following the step shown in FIG.
A MOS transistor is formed through the same steps as shown in (c), (d) and FIGS. 8 (a), (b), and (c). According to the first embodiment, a gentle first inclined portion 12 and a steep second inclined portion 13 are formed by changing an etching condition, for example, a process temperature when forming a trench by RIE. This manufacturing method does not require adding a new step or changing the design of the mask pattern, so that the manufacturing is easy, and the first inclined portion 12 can prevent electric field concentration and provide good characteristics. Transistors can be formed.

Further, since the inclination of the side wall of the trench located at the channel corner portion covered by the gate electrode of the transistor is reduced, the electric field concentration from the gate electrode can be reduced, and the channel corner of the transistor unique to the STI structure can be reduced. The lowering of the threshold voltage of the portion can be prevented. Accordingly, it is possible to prevent the switching characteristics of the transistor unique to the STI structure from deteriorating, and to suppress a decrease in the threshold voltage of the transistor when the transistor is miniaturized and the channel width is reduced.

In addition, since the side walls of the trench have a steep slope in a region deeper than the channel region, it is possible to obtain an STI structure which is sufficiently deep and has a small element separation interval, and enables high integration of elements. .

[Second Embodiment] In the first embodiment, the deposit 22 formed on the side wall of the gently inclined portion 12 is used as a mask under the second RIE condition having the next steep inclination. However, as described above, the second RIE condition is nothing but a condition in which the ratio between the deposit 22 generated during etching and the rate at which the deposit 22 is sputter-etched is about the same. That is, the second
Under the RIE condition, there is a high possibility that the sidewall deposit 22 formed under the first RIE condition is also etched at the same time. At this time,
If the size of the first sidewall deposit 22 is not large enough for the depth of the trench formed by the second RIE, it becomes difficult to obtain a desired trench structure. In consideration of this point, the second embodiment provides a process capable of sufficiently protecting the initial steep slope region regardless of the second RIE condition.

That is, in the first embodiment, the trench having the first and second inclined portions is formed by controlling the temperature of the wafer during the process, but in the second embodiment,
By controlling the RF (high frequency signal) power during RIE and the pressure in the chamber during the process, a trench having first and second inclined portions is formed.

More specifically, the RIE condition is such that the etching selectivity between the silicon substrate and the mask made of a silicon oxide film (SiO ₂ ) is low. In RIE, if the RF power during RIE is increased or the pressure during the process is reduced, the selectivity of etching between the silicon substrate and the silicon oxide film decreases. That is, for example, a gentle slope can be formed by etching under the condition that the RF power is large and the pressure is low.

Under these conditions, the mask made of the silicon oxide film is also etched in the lateral direction at the same time as the etching of the silicon substrate proceeds, so that the mask width gradually decreases. Therefore, etching starts first, and finally, the trench width is narrow at a deep portion of the trench, the trench width is wide at a portion in contact with the mask, and a trench shape with an inclined side wall can be obtained.

FIG. 4 shows a process of manufacturing a trench according to the second embodiment. First, as shown in FIG. 4A, a first mask 31 made of, for example, a silicon oxide film is formed corresponding to the element region on the silicon substrate 11.
However, since the first mask 31 uses the above-described conditions for controlling the inclination, it is necessary to form the first mask 31 with a large film thickness and a large pattern width in consideration of the etching amount.

Next, using the first mask 31,
The silicon substrate 11 is etched under the RIE conditions described above. The first RIE condition is that, for example, the RF power is large,
This is a condition where the pressure is low. By etching the silicon substrate 11 and the mask 31 under these conditions, FIG.
As shown in (b), the first inclined portion 12 having a gentle inclination can be formed to a predetermined depth.

Next, as shown in FIG. 4C, a film 32 serving as a second mask is deposited on the entire surface. This film 32 is the first
The same silicon oxide film as the mask 31 may be used, or a material different from the silicon oxide film such that a selectivity can be obtained with the first mask 31 in a side wall forming step described later, for example, a silicon nitride film may be used.

Next, as shown in FIG. 4D, the film 32 is etched by RIE, and a second mask 33 is formed on the side wall of the first mask so as to cover the first inclined portion 12. .

Thereafter, as shown in FIG. 4E, the second mask 33 is used to form a second RIE having a steep inclination.
The silicon substrate 11 is etched to a desired trench depth by changing the conditions to form a second inclined portion 13 having a steep inclination. In the second RIE condition, for example, when the RF power during RIE is reduced or the pressure during the process is increased, the etching selectivity between the silicon substrate and the silicon oxide film is increased. That is, for example, a steep slope can be formed by etching under the condition that the RF power is small and the pressure is high.

Thereafter, the first mask 31 and the second mask 33 are removed by the same processing as in the first embodiment, whereby a trench as shown in FIG. 3D can be formed. Further, after the step of FIG. 4E, a normal STI forming step is performed to form an element isolation structure, and by forming a gate oxide film and a gate, a transistor structure as shown in FIG. 1 can be obtained.

According to the second embodiment, after the first inclined portion 12 is formed under the first RIE condition using the mask 31 which is larger and thicker than the finally formed element region. Then, a second mask 33 for protecting the first inclined portion 12 is formed, and a trench having a steep second inclined portion 13 is formed. Therefore, the first inclined portion 12
The desired STI structure can be formed in a state where is sufficiently protected.

Further, by changing the etching conditions at the time of trench formation by RIE, a new process for forming a gentle first inclined portion and a steep second inclined portion is added, and a mask pattern is designed. It does not need to be changed and is easy to manufacture.

The present invention is not limited to the above embodiment. For example, as shown in FIG.
In the transistor having the TI structure, the height of the surface of the silicon substrate 11 as an element region may be higher than that of the buried insulating film 14. Even with such a configuration, since the gate electrode covers the corner portion that is gently inclined, concentration of the electric field can be prevented. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0041]

As described above, according to the embodiment of the present invention, the reduction of the electric field concentration from the gate of the MOS transistor prevents the threshold voltage at the channel corner from lowering and obtains good switching characteristics. And a method of manufacturing the same can be provided.

[Brief description of the drawings]

1A is a plan view of a transistor having an STI structure according to the present invention, and FIG. 1B is a plan view of FIG.
Sectional drawing along line (b) -1 (b).

FIG. 2 is an enlarged view of a main part of FIG. 1 (b).

FIG. 3 is a cross-sectional view showing a first embodiment of the manufacturing process of the semiconductor device according to the present invention.

FIG. 4 is a sectional view showing a second embodiment of the manufacturing process of the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view of a transistor having a conventional LOCOS structure.

FIG. 6 is a sectional view of a conventional STI structure.

FIG. 7 is a sectional view showing a step of forming a conventional STI structure.

FIG. 8 is a sectional view showing a step of forming a conventional STI structure.

FIG. 9 is a cross-sectional view showing how a divot is formed by wet etching.

FIG. 10 is a sectional view showing a relationship between a divot and a gate electrode.

[Explanation of symbols]

 Reference Signs List 11: silicon substrate, 11a: trench, 12: first inclined portion, 13: second inclined portion, 14: insulating film, 15: gate electrode, 16: concave portion (divot), 21: mask, 22: deposit , 31: a first mask, 33: a second mask.

Claims (6)

[Claims] A semiconductor substrate, a trench formed in the semiconductor substrate and formed adjacent to an element region, and an insulator filled in the trench to isolate the element region; The side wall of the trench has a first inclined portion formed at an upper portion of the trench and having a gentle inclination, and a second inclined portion having a steep inclination extending from a lower portion of the first inclined portion to a bottom of the trench. A semiconductor device, wherein a gentle angled corner formed by the surface of the element region and the first inclined portion is covered by a gate electrode. 2. An angle formed between a surface of said element region and said first inclined portion is larger than an angle formed between said second inclined portion and a bottom portion of said trench, and is not more than 180 °. 2. The semiconductor device according to claim 1, wherein 3. A first step of forming a mask on an element region of a semiconductor substrate, and etching the semiconductor substrate using the mask under a first etching condition in which a large amount of deposits are generated. A second step of forming the inclined portion and depositing the deposit on the first inclined portion; and a second step of forming no deposit using the deposit as a mask.
Etching the semiconductor substrate to a predetermined depth under the etching conditions described above to form a second inclined portion having a steep inclination;
And a method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first etching condition and the second etching condition have different temperatures at the time of etching. 5. A first step of forming a first mask slightly larger than an element region on an element region of a semiconductor substrate, and forming a first mask between the semiconductor substrate and the first mask using the first mask. A second step of etching the semiconductor substrate under a first etching condition having a low etching selectivity to form a first inclined portion having a gentle inclination; a third step of forming a mask material over the entire surface; Etching a material to form a second mask covering the side surface of the first mask and the first inclined portion;
Using the first and second masks, etching the semiconductor substrate to a predetermined depth under a second etching condition in which an etching selectivity between the semiconductor substrate and the second mask is high, Forming a second inclined portion whose inclination is steeper than that of the first inclined portion. 6. The semiconductor device according to claim 5, wherein the first etching condition is set such that the power of a high-frequency signal is increased and the process pressure is set lower than that of the second etching condition. Manufacturing method.