JP2002141407A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a very precise and reliable trench having a gentle tapered face near an opening. SOLUTION: A process of forming the trench in the surface of a semiconductor substrate comprises: a first etching process of selectively etching the surface of the semiconductor substrate exposed out of a mask using a mixed gas of hydrohalogen and fluorocarbon; a second etching process of etching the surface of the semiconductor substrate using a plasma of a mixed gas of a halogen- contained gas and oxygen or nitrogen after the first etching process; and a third etching process of etching the surface of the semiconductor substrate using a plasma of a mixed gas of a halogen-contained gas and oxygen after the second etching process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to the formation of a trench.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor devices have been progressing, and a technique for performing sub-quarter micron processing with high accuracy and high reproducibility has been required. Among them, formation of high-precision and fine trenches has become an extremely important issue in multi-layer or three-dimensional devices such as device isolation.

[0003] When element isolation using a trench is performed, if the corner of the trench opening is sharp, there is a problem that the electric field is likely to be concentrated in the MOSFET formed on the surface of the semiconductor substrate. As shown in FIG. 11, the shape of the trench, that is, the taper angle θ of the trench and the radius of curvature of the upper portion of the trench
It is known that R greatly affects the Id-Vg characteristics of a MOSFET.

That is, in the case of a trench having a taper angle θ close to vertical and a small corner R, the Id-Vg characteristic of the MOSFET sometimes shows a double hump characteristic. In order to avoid such a problem, the taper angle of the trench may be reduced. However, when the isolation width of the element becomes finer, the trench cannot be formed deeper than the depth determined by the taper angle as shown in FIG. You will not be able to do it. Further, in order to obtain a desired depth, it is necessary to make the opening diameter of the trench extremely large, which has been a major problem that hinders miniaturization.

In order to achieve both good transistor characteristics and good isolation performance in a fine trench, a gentle taper is formed only in the opening of the trench as shown in FIG. It is desired to realize such a trench shape.

Hitherto, there has been proposed a method of obtaining a Y-shaped trench as shown in FIG. 13 by adding 1-5% of oxygen O ₂ to hydrogen bromide HBr (Japanese Patent Laid-Open No. 6-611).
90). However, in this method, although a gentle taper is formed near the upper part of the trench, as shown in FIG. 14, there is a problem that the opening is hardly tapered and becomes steep.

As shown in FIG. 15A, when etching for forming a trench through a SiN (Si ₃ N ₄ ) mask 101 formed on the surface of a silicon substrate 100, as shown in FIG. The etching must proceed while the polymer 102 is being adhered to the inner wall of the trench T, but HBr / O ₂ , Cl ₂ / O ₂ , Cl ₂ /
In a process using N ₂ or the like, as shown in FIG. 15B, the reaction product, SiCl _x or SiBr _x , reacts with oxygen radicals in the gas phase only after being supplied to the gas phase, and
Deposition of the halogenated oxide of i begins. Therefore, at the stage before the supply of SiCl _x or SiBr _x into the gas phase is started, that is, at the initial stage of etching, a taper is hardly formed, and a steep profile is formed.

Therefore, in order to form a taper from the initial stage of etching, it is necessary to supply deposition species from a gas phase. Therefore, a method has been proposed in which CF _x radicals or ions are supplied from the gas phase to the substrate surface using an inductively coupled plasma etching apparatus as shown in FIG. 16 and a Si substrate is etched by Br while depositing a fluorocarbon polymer. I have. This apparatus generates plasma 205 between a ceramic dome 201 made of Al ₂ O ₃ and a polyimide electrostatic chuck 202 as a lower electrode, and cleans the surface of a silicon substrate 200 placed on the polyimide electrostatic chuck 202. It is to be etched.
Outside the ceramic dome 201, a coil 204 connected to a high frequency power supply of 12.56 MHz is provided. The polyimide electrostatic chuck 202 is 13.56M.
Hz bias power supply 203.

Here, as a first step, the pressure in the chamber is set to 50 mtorr and the source power is set to 120 mtorr.
0 W, bias power 200 W, HBr / CF ₄ = 80
Etching is performed for 30 seconds at / 80 sccm.

Next, as a second step, the pressure in the chamber is set to 40 mtorr, the source power is 1500 W,
Bias power 180 W, HBr / Cl ₂ / O ₂ = 160
Etching is performed for 58 seconds at / 20/5 sccm.
At this time, the temperature of the coolant for cooling the electrodes was 50 ° C.

When such a method is used, it is necessary to perform etching at a relatively high pressure in order to form a sufficient forward taper. However, as a result of etching using the inductively coupled plasma etching apparatus, 50 mtor was obtained.
It was found that a residue was generated at a pressure of about r. If the etching pressure is lowered, the generation of residues can be prevented, but there is a problem that the taper angle increases.

Further, Si_ThreeN_FourOr SiO_TwoConsists of
HBr / CF using etching mask_FourOr HB
r / CHF_ThreeThe first etching step is performed by the process.
If_ThreeN_FourOr SiO_TwoEtching against
The selectivity is low and the film thickness of the etching mask decreases sharply.
You. This is due to the F radical_ThreeN₄Or Si
O_TwoIs etched. Under the above conditions
Si when etched _ThreeN_FourEtching machine consisting of
The amount of film reduction of the disk was 20-32 m.

As described above, the film thickness of the etching mask made of Si ₃ N ₄ or SiO ₂ is greatly reduced. In other words, in this method, there is a trade-off relationship between the formation of the taper and the prevention of residue generation, and the prevention of residue generation and the reduction in film thickness of the mask, and it has been extremely difficult to obtain good results in any case.

[0014]

As described above, in the conventional method, when trench etching is performed, there is a trade-off relationship between the formation of a taper and the prevention of the generation of a residue, the prevention of the generation of a residue, and the reduction of the film thickness of a mask. There is a problem that it is extremely difficult to form a trench having a high degree of dimensional accuracy such that the taper in the vicinity is moderate and the inside of the trench is sharp.

The present invention has been made in view of the above circumstances, and has as its object to obtain a highly accurate and highly reliable trench having a gentle tapered surface near an opening.

[0016]

Accordingly, in a first aspect of the present invention, a trench is provided, and the trench sidewall has a first tapered surface having a gentle taper angle at a trench opening and a depth greater than a predetermined depth. And a second tapered surface having a taper angle steeper than the taper angle in the region.

According to this configuration, it is possible to provide a highly reliable semiconductor device which is smooth at the opening on the surface and has no break in the film formed on the surface while maintaining the miniaturization of the element. .

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor substrate is a silicon substrate, and the trench has an insulating film formed on an inner wall to form an element isolation region. And

According to this configuration, a fine and highly reliable semiconductor device can be formed without problems such as current concentration.

According to a third aspect of the present invention, in the semiconductor device of the first aspect, a diffusion layer formed on the inner wall of the trench, a dielectric film formed on the surface of the diffusion layer, and a dielectric film formed on the surface of the dielectric film A capacitor is constituted by the conductive film thus formed, and the conductive film is formed so as to reach from the opening end of the trench to the surface of the semiconductor substrate.

According to a fourth aspect of the present invention, in the semiconductor device of the first aspect, a gate electrode is formed on the inner wall of the trench via a gate insulating film, and one of the source / drain diffusion regions is in the vicinity of the opening of the trench. To reach the semiconductor surface to form a MOSFET having a part of the trench inner wall as a channel.

According to a fifth aspect of the present invention, the step of forming a trench in the surface of the semiconductor substrate includes the step of forming a trench between at least one gas of silicon halide and boron halide and at least one gas of oxygen or nitrogen. A first etching step of selectively etching the surface of the semiconductor substrate exposed from the mask using the mixed gas plasma, and after the first etching step, a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen is used. And a second etching step of etching the surface of the semiconductor substrate.

According to this configuration, since silicon halide or boron halide and at least one gas of oxygen or nitrogen are added in the first etching step, silicon oxide, nitride, oxide, Since a compound serving as a sidewall protective film such as an oxide, nitride, or oxynitride of nitride or boron is supplied from plasma, the trench is formed such that the trench opening has a gentle tapered surface. Then, after the opening is formed gently in this manner, it is possible to form a steep trench by performing etching using a halogen-containing gas.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, the silicon halide is Si.
Cl ₄ or SiBr ₄ , and the boron halide is one of BCl ₃ and BBr ₃ .

According to a seventh aspect of the present invention, the step of forming a trench in the surface of the semiconductor substrate is a first etching step of selectively etching the surface of the semiconductor substrate exposed from the mask using a mixed gas of hydrogen halide and fluorocarbon. When,
After the first etching step, a halogen-containing gas;
A second etching step of etching the surface of the semiconductor substrate using a mixed gas plasma of oxygen or nitrogen; and after the second etching step, a surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas and oxygen. And a third etching step of etching.

According to this structure, the active species for forming the side wall protective film are supplied from the plasma to the semiconductor substrate surface by using a mixed gas of hydrogen halide and fluorocarbon to form a gentle tapered surface. In the second etching step, a steep tapered surface is formed using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen. In the third etching step, by adding hydrogen halide such as HBr, the etching selectivity with respect to the mask is improved, and the occurrence of an abnormal sidewall shape due to a decrease in the film thickness of the mask is prevented. By adding Cl ₂ , it is possible to prevent the occurrence of an etch stop even in a narrow trench. Therefore, the third using Cl ₂ / HBr / O ₂
By performing the etching step, it is possible to obtain a desired depth even in a fine trench.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, the third etching step is an etching step using a mixed gas of HBr, Cl ₂ and O _2. There is a feature. Preferably, the hydrogen halide is at least one of HCl, HBr and HI.
It is characterized by containing seeds.

According to this configuration, the addition of Cl ₂ increases the taper angle, prevents the etch stop even when forming a trench with a small opening diameter, and makes it possible to form a trench with a desired depth. Further, by adding HBr, the etching selectivity with respect to a mask such as a resist is improved, and it is possible to prevent a decrease in the thickness of the mask.

In a ninth aspect of the present invention, the step of forming a trench in the surface of the semiconductor substrate includes the step of forming a trench of a mixed gas of halogen and / or hydrogen halide, organic silane (Si (CH ₃ ) _x H _4-x ) and oxygen or nitrogen. A first etching step of selectively etching the semiconductor substrate surface exposed from the mask using a mixed gas, and after the first etching step, using a mixed gas plasma of a halogen-containing gas and oxygen or nitrogen. And a second etching step of etching the surface of the semiconductor substrate.

According to this structure, since a mixed gas of halogen and / or hydrogen halide and organic silane (Si (CH ₃ ) _x H _4-x ) is used in the first etching step, silicon oxide, Since a compound serving as a sidewall protective film, such as nitride or nitrided oxide, is supplied from plasma,
The trench is formed such that the trench opening has a gentle taper surface. Then, after the opening is formed gently in this manner, it is possible to form a steep trench by performing etching using a halogen-containing gas.

According to a tenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the ninth aspect, the halogen is C.
l _2, Br _2, comprises at least one I _2, and the hydrogen halide is characterized in that it comprises HCl, HBr, at least one of HI.

According to an eleventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the ninth or tenth aspect, the halogen-containing gas contains at least one of Cl ₂ , HCl, Br ₂ , HBr, and HI. Features.

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the ninth to eleventh aspects, the organic silane gas includes tetramethylsilane: Si (CH ₃ ) ₄ and trimethylsilane: Si (CH ₃ ) _3. H, dimethylsilane: Si
(CH ₃ ) ₂ H ₂ .

In a thirteenth aspect of the present invention, the step of forming a trench in the surface of the semiconductor substrate includes the step of selectively etching the surface of the semiconductor substrate exposed from the mask using a mixed gas of halogen and / or hydrogen halide and hydrocarbon. A first etching step, and after the first etching step, a second etching step of etching the surface of the semiconductor substrate using a mixed gas plasma of a halogen-containing gas, oxygen, or nitrogen. .

According to a fourteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the thirteenth aspect, the halogen is Cl
_2, Br _2, comprises at least one I _2, and the hydrogen halide is characterized in that it comprises HCl, HBr, at least one of HI.

According to a fifteenth aspect of the present invention, claim 13 or claim 14 is provided.
The method for manufacturing a semiconductor device according to the above aspect, wherein the halogen-containing gas contains at least one of Cl ₂ , HCl, Br ₂ , HBr, and HI.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. First, as shown in FIG. 1, a silicon nitride film Si ₃ N ₄ having a thickness of 170 nm is formed on the surface of a silicon substrate 1 and patterned to form a mask 2 made of a silicon nitride film.

Then, a trench for element isolation is formed through the mask 2. As an apparatus, an inductively coupled plasma etching apparatus shown in FIG. 16 is used, the silicon substrate 1 is placed on a polyimide electrostatic chuck, and three-step etching is performed under the following conditions.

Step 1: pressure = 15 mTorr, source power: 1200 W, bias power: 100 W, H
Etching is performed for 5 seconds using a mixed gas of Br / CF4 = 80/80 sccm.

Step 2: pressure = 15 mTorr, source power: 1000 W, bias power: 150 W, C
Using a mixed gas of l ₂ / N ₂ = 125/50 sccm,
Perform etching for 15 seconds.

Step 3: pressure = 40 mTorr, source power: 1500 W, bias power: 180 W, H
Etching is performed for 50 seconds using a mixed gas of Br / Cl ₂ / O ₂ = 160/20/5 sccm.

Here, the temperature of the coolant for cooling the electrodes is 50 ° C. FIG. 2 shows the etching shape thus obtained. Thus, in a region where the opening is gentle and deep, a gentle trench having a steep tapered surface can be obtained.

FIG. 3A is an enlarged photograph of the bottom surface of the trench thus formed. It can be seen that a smooth surface state can be obtained. Incidentally, FIG. 3B shows an SEM photograph of the bottom of the trench formed by the conventional two-step etching (Japanese Patent Laid-Open No. 1-118628). FIG. 3C shows a SEM photograph of the silicon surface of FIG. As apparent from the comparison between FIGS. 3B and 3C and FIG. 3A, the bottom surface of the trench formed by the conventional method is the same as that of FIG.
And as shown in FIG. 3 (c), the surface was uneven.

First, etching in step 1 is performed under the above conditions. In this step, the pressure is set at 3 to prevent the generation of residue.
It is desirable to set it to 0 mTorr or less. In addition, the source power is set to 1 in order to suppress the amount of film reduction of the mask.
It is desirable that the bias power be 500 W or less and the bias power be 300 W or less.

Further, the flow ratio of HBr / CF ₄ is 120: 4.
It is considered that it can be used in the range of 0 to 40: 120 sccm. However, when the CF ₄ ratio is high, the amount of film reduction of the mask increases.

The etching gas and the flow rate ratio are as follows:
What is necessary is just to select so that a desired taper angle can be obtained.

Next, regarding the second etching step, it is not limited to the mixed gas of Cl ₂ and N ₂ that reacts with the halide of silicon to form a reaction product which is deposited on the substrate surface. It is desirable to select a gas composition that allows.

As a combination of this gas, HBr +
N ₂ , HBr + Cl ₂ + O ₂ , HBr + Br ₂ + O ₂ , Cl ₂
+ O ₂ + N ₂ , HCl + N ₂ , HCl ₂ + Cl ₂ + N _{2 and the} like can be selected.

In the third etching step, Cl ₂ , HCl, Br ₂ , HBr, HI or the like can be selected as the gas.

The taper angle of the trench thus obtained was 48.2 ° to 59.0 °, and the same as the designed value was obtained without variation. Variation is at most 1
The taper angle of the trench formed by the conventional method was 45.7 to 68.0 degrees, and the variation was 22.3 degrees.

Next, in the third etching step, the taper angle was measured by changing the flow rate of chlorine.
FIG. 4 shows the results. This shows the result of measuring the dependence of the taper angle on the Cl ₂ flow rate ratio when forming a trench having a width of 0.25 μm. It can be seen that the taper angle is increased by increasing the amount of Cl ₂ added.

Here, the taper angle θ and the maximum trench depth d _max at the frontage W are represented by the following equations. d _max = (W / 2) tan θ

FIG. 5 shows the dependency of the maximum trench depth on the trench taper angle. From this equation, the opening diameter of the trench is 20
When the thickness is 0 nm, in order to make the trench depth 320 nm or more, it is necessary to determine the etching process so that the taper angle becomes 72.6 degrees or more.

When the trench is etched to a depth of 320 nm after the taper is gradually reduced to 100 nm in the vicinity of the opening, the taper angle of the trench is 81.
Must be at least once. It can be seen from FIG. 4 that Cl ₂ should be added by about 5% in order to form a trench having a taper angle of 72.6 degrees or more in a trench having an opening diameter of 200 nm. Further, in order to form a trench having an opening diameter of 100 nm and a taper angle of 72.6 degrees or more, the Cl ₂ addition ratio may be about 20%.

As described above, as the trench becomes finer,
Although it is necessary to increase the taper angle of the second tapered surface of the trench, it can be seen that a desired trench depth can be obtained for a fine trench by controlling the amount of Cl ₂ added.

When etching is performed with Cl ₂ / O ₂ plasma, the selectivity to the side wall polymer is low.
As shown in (b), the sidewall polymer formed in the first etching step may be etched, exposing the substrate. As the etching proceeds further, FIG.
As shown in (c), the portion where the sidewall polymer 6 has been removed is etched, and the silicon substrate is scraped. Since SiO ₂ -based deposits are deposited as protective films 7 on the side walls of the trench formed by newly etching the silicon substrate, the silicon substrate in the portion protected by these films is not etched. Therefore, the portion protected by the SiO ₂ -based reaction product 7 forms a projecting side wall.

FIG. 6 shows the case where the etching is further advanced.
A remarkable abnormal shape as shown in FIG. On the other hand, in the first embodiment, since HBr is added in the third etching step, SiO ₂ ,
The selectivity to Si ₃ N ₄ , SiO ₂ or resist is improved, and the occurrence of abnormal shapes can be prevented.

The mask thickness D must be set so that the aspect ratio (D / W) does not exceed 1 when the mask thickness D is set to the trench width W. Aspect ratio is 1
Is exceeded, the coverage of the sidewall protective film starts to rapidly deteriorate when the opening is made gentle in the first etching step. If the aspect ratio can be set to 1 or less, it is not limited to Si ₃ N ₄ , but can be appropriately modified such as a two-layer film of a photoresist and Si ₃ N ₄ .

Further, the first etching step includes:
Desirably, a mixed gas of at least one of HCl, HBr, and HI and a gas represented by the general formula CxHyXz (X ≧ 1, Z ≧ 1, Y ≧ 0, all positive numbers, and X is F
Or Br. CxBryFz (2x + 2 = y +
z) may be used. ). The gas ratio HBr: CF ₄ is 5: 3 to 3: 5 is desirable. The process pressure is set to 30 mTorr or less. The etching time may be any time as long as the surface of the silicon substrate is etched by a single atomic layer or more.

In the second etching step, Cl ₂ / N ₂ or Cl ₂ / HBr / N ₂ is used as an etching gas, and Cl ₂ :
N ₂ is about 24: 3 to 25:10, Cl ₂ : HBr: N
₂ is preferably Cl ₂ : HBr in the range of 0:10 to 10: 0, to which N ₂ is added in an amount of 5 to 15%. The process pressure is 30 mtorr or less. The etching time may be any time as long as the silicon substrate surface is etched by 30 nm or more.

Further, the third etching step is performed by using HBr
/ Cl ₂ / O ₂ , 10 to 50% of Cl ₂ , 5 to 10% of O ₂ for ICP, and 5 to 30% of O ₂ for ECR, etching amount required for element isolation The etching is continued until reaching.

The source power is such that the ion current density is 0.5-3 mA / cm ² on the substrate, and the bias power is such that Vpp at the substrate installation electrode is 40 V
The above or the power at which Vdc becomes 20 eV or more is selected. Here, the reason why Vdc is set to 20 eV or more is that Si-S
This is because ion energy of 20 eV or more is required to break the i-bond. In addition, the ion current density is 0.5-
Although it was set to 3 mA, there is a problem that if it is too high, the etching selectivity decreases.

Next, a second embodiment of the present invention will be described. In the above embodiment, three-step etching is used, but this method is characterized by using two-step etching.

First, as in the first embodiment, as shown in FIG. 1, a silicon nitride film Si ₃ N ₄ having a thickness of 170 nm is formed on the surface of the silicon substrate 1 and patterned, and a mask made of the silicon nitride film is formed. Form 2

Then, a trench for element isolation is formed through the mask 2. As the apparatus, an inductively coupled plasma etching apparatus shown in FIG. 16 is used, the silicon substrate 1 is placed on a polyimide electrostatic chuck, and two-step etching is performed under the following conditions.

Step 1: pressure = 15 mTorr, source power: 1200 W, bias power: 100 W, S
Etching is performed for 10 seconds using a mixed gas of iCl ₄ / N ₂ = 80/10 sccm. Flow rate ratio of the gas in step 1, the N ₂ 5% ~20% preferably 1
It must be contained at about 0%. In addition, SiC
When Cl ₂ is added to a mixed gas of l ₄ and N ₂ , the etching rate increases, but the flow rate of N ₂ needs to be increased in order to obtain a good forward taper shape.

Step 2: Step 3: pressure = 40 m
Torr, source power: 1500 W, bias power: 180 W, HBr / Cl ₂ / O ₂ = 160/20/5
Etching is performed for 50 seconds using a mixed gas of sccm. This step was set under the same conditions as the third etching step of the first embodiment.

Here, the temperature of the coolant for cooling the electrodes is 50 ° C. The etching shape obtained in this way was the same as that shown in FIG. Thus, in a region where the opening is gentle and deep, a gentle trench having a steep tapered surface can be obtained.

Here, in the first etching step, Si
In addition to Cl ₄ , SiBr ₄ , BCl ₃ , BBr _{3 and the} like can be applied. The second etching step is similar to the third etching step of the first embodiment, except that Cl ₂ and HC are used.
1, Br ₂ , HBr, HI, etc. are applicable.

As an etching apparatus, in addition to the inductively-coupled plasma type etching apparatus shown in FIG. 16, as shown in FIG.
It goes without saying that the present invention is also applicable to a (resonance) plasma etching apparatus. This apparatus performs plasma etching on the surface of a silicon substrate 300 placed on a ceramic electrostatic chuck 302 as a lower electrode. A coil 304 connected to a high-frequency power supply is provided outside the chamber 301. The ceramic electrostatic chuck 302 has a bias power supply 30 of 13.56 MHz.
3 is connected.

Here, the etching conditions using the ECR plasma etching apparatus were as follows.

Step 1: pressure = 1 mTorr, source power (2.45 GHz microwave): 1400 W, R
F power: 45 W, Cl ₂ / N ₂ = 25 / 3-9 sccm
Is performed for 60 seconds using a mixed gas of

Step 2: pressure = 2 mTorr, source power (2.45 GHz microwave): 1500 W, R
F power: 56 W, HBr / O ₂ = 100/6 sccm
Etching for 50 seconds using a mixed gas of

The trench shapes thus obtained are shown in FIGS. These figures are views showing states when the N ₂ flow rate in the first etching step is changed to 3, 6, 9 sccm, respectively.

From these results, it is understood that the taper angle of the trench opening can be controlled by changing the nitrogen flow rate. 8 to 10, it can be seen that under the above-described etching conditions, a favorable taper angle can be obtained when the nitrogen flow rate is 3 to 6 sccm.

Cl required to obtain a desired taper angle
_{The 2} : N ₂ flow ratio also depends on the process pressure, source power, and bias power and needs to be optimized according to the etching conditions.

Although the silicon nitride film is used as a mask in the above embodiment, a photoresist other than the silicon oxide film may be used.

In the above embodiment, only an example in which the trench is used for element isolation has been described. However, the present invention is not limited to the element isolation, and a trench MOSFET having a gate on the sidewall of the trench and a trench having a capacitor on the sidewall of the trench. The present invention is also applicable to a type capacitor.

When applied to a trench MOSFET,
According to the present invention, a steep inside the trench and a gentle tapered surface near the trench opening can be obtained. Since such a surface can be used as a gate, the occupied area can be reduced, and a fine and highly reliable semiconductor device can be provided.

Further, when the trench bottom and / or trench side wall is used as a capacitor, when a capacitor electrode is formed so as to extend to the substrate surface, or when a wiring is connected to a circuit device formed on the substrate surface, etc. In addition, since a substantially vertical surface can be used as a capacitor while preventing disconnection of wiring near the trench opening, the occupied area can be reduced, and a fine and highly reliable semiconductor device can be used. Can be provided.

[0081]

As described above, according to the present invention, a fine and highly reliable trench can be formed, the area required for element isolation is small, and the element can be miniaturized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a process of forming a trench according to an embodiment of the present invention.

FIG. 2 is a view showing a process of forming a trench according to an embodiment of the present invention;

FIG. 3 is a photograph of a trench surface obtained in the same step and a photograph showing a trench surface formed by a conventional method.

FIG. 4 is a diagram showing the relationship between the taper angle of a trench and the amount of Cl ₂ added.

FIG. 5 is a diagram showing the dependence of the maximum trench depth on the taper angle of the trench.

FIG. 6 is an explanatory view showing an etching process.

FIG. 7 is a diagram showing an ECR plasma etching apparatus.

FIG. 8 is a photograph showing a trench shape when the amount of nitrogen added is changed using the etching apparatus of FIG. 7;

FIG. 9 is a photograph showing a trench shape when the amount of nitrogen added is changed using the etching apparatus of FIG. 7;

10 is a photograph showing a trench shape when the amount of nitrogen added is changed using the etching apparatus of FIG.

FIG. 11 is an explanatory view showing a conventional trench.

FIG. 12 is an explanatory view showing a conventional trench.

FIG. 13 is an explanatory view showing an ideal trench shape.

FIG. 14 is an explanatory view showing a trench shape formed by a conventional method.

FIG. 15 is a diagram showing a process of forming a trench by a conventional method.

FIG. 16 shows an inductively coupled plasma etching apparatus.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 silicon substrate 101 mask 102 polymer 201 ceramic dome 202 polyimide electrostatic chuck 203 Al ₂ O ₃ 204 coil 205 plasma

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 653 H01L 29/78 658G 21/336 F term (Reference) 5F004 AA11 BA16 BA20 BB14 BB18 CA01 DA00 DA01 DA04 DA11 DA25 DA26 DA29 DB01 EA28 EB04 EB05 5F032 AA36 AA67 CA17 DA23 DA28 DA30 5F038 AC10 EZ15 EZ20 5F040 DC01 EC24 EK05 FC21

Claims (15)

[Claims] 1. A semiconductor device comprising: a trench formed on a surface of a semiconductor substrate; wherein a side wall of the trench has a first tapered surface having a gentle taper angle at a trench opening; A second tapered surface having a steeper taper angle than the second tapered surface. 2. The semiconductor substrate is a silicon substrate,
2. The semiconductor device according to claim 1, wherein an insulating film is formed on an inner wall of the trench to form an element isolation region. 3. A capacitor comprising a diffusion layer formed on the inner wall of the trench, a dielectric film formed on the surface of the diffusion layer, and a conductive film formed on the surface of the dielectric film. 2. The semiconductor device according to claim 1, wherein the conductive film is formed so as to reach from the opening end of the trench to the surface of the semiconductor substrate. 4. A gate electrode is formed on an inner wall of the trench via a gate insulating film, and one of source / drain diffusion regions is formed so as to reach from the vicinity of the opening of the trench to the semiconductor surface, 2. The semiconductor device according to claim 1, wherein a MOSFET having a part of the inner wall of the trench as a channel is configured. 5. A step of forming a trench in a surface of a semiconductor substrate, using a mixed gas plasma of at least one kind of gas of silicon halide and boron halide and at least one kind of gas of oxygen or nitrogen. A first etching step of selectively etching the semiconductor substrate surface exposed from the mask, and after the first etching step, a halogen-containing gas;
A second etching step of etching the semiconductor substrate surface using a mixed gas plasma of oxygen or nitrogen. 6. The silicon halide is SiCl ₄ , Si
Br ₄ , wherein the boron halide is B 4
Cl _3, a method of manufacturing a semiconductor device according to claim 5, characterized in that any one of BBr _3. 7. A step of forming a trench in the surface of the semiconductor substrate, the first etching step of selectively etching the surface of the semiconductor substrate exposed from the mask using a mixed gas of hydrogen halide and fluorocarbon; After the etching step, halogen-containing gas and
A second etching step of etching the surface of the semiconductor substrate using a mixed gas plasma of oxygen or nitrogen, and after the second etching step, a halogen-containing gas;
A third etching step of etching the surface of the semiconductor substrate using a mixed gas plasma with oxygen. 8. The method according to claim 7, wherein the third etching step is performed using HBr.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the mixed gas is a mixed gas of Cl ₂ , Cl ₂ , and O ₂ . 9. The step of forming a trench in the surface of a semiconductor substrate comprises the steps of:
a first etching step of selectively etching the semiconductor substrate surface exposed from the mask using a mixed gas of i (CH ₃ ) _x H _4-x ) and oxygen or nitrogen; and after the first etching step, A halogen-containing gas,
A second etching step of etching the semiconductor substrate surface using a mixed gas plasma of oxygen or nitrogen. 10. The halogen is Cl ₂ , Br ₂ , I ₂
And the hydrogen halide is H
The method according to claim 9, wherein the method includes at least one of Cl, HBr, and HI. 11. The halogen-containing gas may be Cl ₂ , H
The method of manufacturing a semiconductor device according to claim 9, further comprising at least one of Cl, Br ₂ , HBr, and HI. 12. The organic silane gas is tetramethyl
Silane: Si (CH _Three)_Four, Trimethylsilane: Si (C
H_Three)_ThreeH, dimethylsilane: Si (CH_Three)_TwoH_TwoNozomi
The method according to claim 9, wherein:
13. A method for manufacturing a semiconductor device according to 13. A step of forming a trench in a surface of a semiconductor substrate, comprising: a first etching step of selectively etching a surface of the semiconductor substrate exposed from a mask using a mixed gas of halogen and / or hydrogen halide and hydrocarbon. After the first etching step, a halogen-containing gas;
A second etching step of etching the semiconductor substrate surface using a mixed gas plasma of oxygen or nitrogen. 14. The method according to claim 14, wherein the halogen is Cl ₂ , Br ₂ , I ₂
And the hydrogen halide is H
14. The method for manufacturing a semiconductor device according to claim 13, comprising at least one of Cl, HBr, and HI. 15. The halogen-containing gas may be Cl ₂ , H
The method according to claim 13, wherein the method includes at least one of Cl, Br ₂ , HBr, and HI.