JP2000277488A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is prevented from deteriorating in gate breakdown voltage and enhanced in reliability by a method wherein the edge of a trench opening is rounded so as to be large in curvature radius, and an electric field is prevented from concentrating on it. SOLUTION: An Si substrate is subjected to isotropic etching by the use of a dry etcher of down flow-type using an oxide film 2 as a mask, and an etching groove 3 is formed so as to round a point where the flat surface of the Si substrate intersects a trench opening that is formed in a following process or a part which becomes the edge of a trench opening. Thereafter, a trench groove is formed. The depth X of etching of the etching groove 3 is set at a prescribed range of 100 to 170 nm, by which the edge of a trench opening can be roounded large in a curvature radius.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a trench gate structure used in a power switching element.

[0002]

2. Description of the Related Art In recent years, a trench gate structure has been adopted in order to improve the ON characteristics and ON resistance of IGBTs (insulated gate bipolar transistors), MOSFETs (MOS gate field effect transistors) and MOS thyristors (MOS gate thyristors). More and more. In this trench gate structure, a trench is dug, and the surface in the trench is covered with a gate oxide film.
It is formed by filling polysilicon serving as a gate electrode into a trench groove covered with the gate oxide film.

FIG. 13 shows a conventional manufacturing method for forming a trench. FIGS. 13A to 13C are cross-sectional views showing the manufacturing steps in the order of the manufacturing steps. In FIG. 1A, a trench 24 is formed in a silicon substrate 21. At this time, the damage layer 26 is formed on the surface layer of the trench 24.
After that, the oxide film 22 is etched to expose the edge of the trench opening 25 (opening of the trench groove).
In FIG. 2B, when forming the trench 24, the damaged layer 26 introduced into the silicon substrate 21 is removed by etching. At this time, the trench opening 25 becomes wider. Thereafter, a sacrificial oxide film 27 is formed, and the edge of the trench opening (an obtuse but sharp portion) is rounded.
In FIG. 3C, the sacrificial oxide film 27 is removed, and then a gate oxide film 28 is formed.

In the above, if the gate oxide film 28 is formed without forming the sacrificial oxide film 27 by etching the damage layer 26 after forming the trench 24, the shape of the edge of the trench opening 25 is obtuse. Becomes sharp, and when a gate voltage is applied, electric field concentration occurs at a sharp portion D in FIG. 3C, which causes a problem that the gate breakdown voltage is reduced. In order to round the edge of the sharp trench opening 25, sacrificial oxidation is performed at a high temperature. This sacrificial oxidation is to form the sacrificial oxide film 27 on the silicon substrate 21 and remove the sacrificial oxide film. By forming a thick sacrificial oxide film 27 at the sharp portion D, the silicon surface at the sharp portion D is rounded, and thereafter, by removing the sacrificial oxide film 27, the silicon surface at the sharp portion D is rounded. The sacrificial oxidation step also has the function of removing residual damage.

[0005]

However, even with this sacrificial oxidation, the silicon surface at the sharp portion D is not rounded with a sufficiently large radius of curvature, and electric field concentration occurs at the sharp portion D, resulting in a decrease in gate breakdown voltage. . SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to round the edge of a trench opening with a large radius of curvature, and to prevent electric field concentration, thereby preventing a decrease in gate withstand voltage and providing a highly reliable semiconductor device. It is to provide a manufacturing method.

[0006]

In order to achieve the above object, in a method of manufacturing a semiconductor device having a trench gate structure, a surface layer of a region to be a trench opening is preliminarily isotropic before trench etching. To be removed by etching. The depth to be removed by the isotropic etching is preferably 70 nm to 170 nm from the surface of the region to be the trench opening.

[0007]

FIG. 1 to FIG. 10 are cross-sectional views showing a manufacturing method according to an embodiment of the present invention in the order of steps. In FIG. 1, an oxide film 2 having a thickness of about 400 nm is formed on a silicon substrate 1 by pyro-oxidation at a processing temperature of about 1100 ° C. Pyro-oxidation is a method in which hydrogen and oxygen are reacted at a high temperature to form steam, and an oxide film is formed on the silicon surface using the steam. The oxide film can be formed in a cleaner state than steam oxidation.

In FIG. 2, following FIG. 1, after patterning by photolithography, dry etching by reactive ion etching (RIE) is performed to use the patterned oxide film 2 as a mask for trench etching.

In FIG. 3, following FIG. 2, using this oxide film 2 as a mask, isotropic Si etching is performed by a down-flow type dry etcher to form a silicon flat surface and the next step. An etching groove 3 is formed in order to previously etch and round a portion where the opening portion of the trench intersects, that is, a portion which becomes an edge of the trench opening portion. The etching amount X at this time is changed from 70 nm to 17
It is set to a predetermined value in the range of 0 nm.

In FIG. 4, following FIG. 3, trench etching is performed to form a trench 4. In FIG. 5, following FIG. 4, the mask oxide film 2 is retracted by about 300 nm by wet etching with hydrofluoric acid, and the recessed oxide film 2a is formed into the trench opening 5.
Expose the edge of

In FIG. 6, following FIG. 5, the Si etching by the down-flow type dry etcher is performed for 10 minutes.
The process is performed to about 0 nm, and the damaged layer 6 caused by the trench etching shown in FIG. 5 is removed. At this time, the portion B of the trench opening has a tapered shape. In FIG.
As shown in FIG. 6, the mask oxide film 2a is removed using hydrofluoric acid.

In FIG. 8, following FIG. 7, a sacrifice oxide film 7 having a thickness of about 100 nm is formed by oxidizing at a high processing temperature of about 1100 ° C., for example, by dry oxidation. The silicon surface at the sharp point C is smoothed. Dry oxidation is a method in which oxygen is supplied and reacted with silicon at a high temperature to form a dense oxide film. 9, following FIG. 8, the sacrificial oxide film 7 is removed with hydrofluoric acid. In FIG. 10, a gate oxide film 8 is formed following FIG.

In FIG. 3 described above, an etching amount is set to 70 nm by rounding to round a portion to be an edge of the opening.
A predetermined value in the range from 170 nm to 170 nm, the radius of curvature of the trench opening becomes large, and when a gate voltage is applied, the electric field concentration at this location can be prevented, the gate breakdown voltage can be improved, and the reliability of the semiconductor device can be improved. Can be enhanced.

FIG. 11 is a graph showing the result of an experiment to determine the relationship between the amount of etching and the rate of good gate breakdown voltage in the step of FIG. The specifications of the trench used in the experiment were as follows: the width of the trench 4 was fixed at 0.8 μm, the depth was 3.0 μm, the removal amount of the damaged layer 6 was fixed at 100 nm, and the etching amount X was 0, 10
It was made variable to 0, 150, and 200 nm. In addition, the electric field intensity applied to the gate oxide film covering the trench groove 4 is set to 9.
6 MV / cm, the ratio of the element that withstands the electric field strength was expressed as the non-defective gate rate.

As the etching amount X increases, the gate non-defective rate increases, but the etching amount X reaches a maximum at 150 nm, and decreases again at 200 nm. this is,
This is because, when the etching amount X is increased to 200 nm, the edge of the trench opening has an inverted tapered shape (shape that becomes acute), so that electric field concentration is likely to occur.

According to this experiment, the etching amount is preferably in the range of 70 nm to 170 nm,
The optimum is around 0 nm. The trench width, the depth, and the removal amount of the damaged layer are each increased from about 0.5 times to 2 times.
Even if it is changed about twice, the same result as above is expected.

FIG. 12 shows the gate breakdown electric field intensity distribution of the device having the trench manufactured by the manufacturing method of the present invention and the conventional manufacturing method. FIG. 12 (a) is a distribution diagram in the case of the manufacturing method of the present invention. FIG. 2B is a distribution diagram in the case of the conventional manufacturing method.

Compared with the conventional manufacturing method, the device manufactured by the manufacturing method of the present invention has a smaller variation in gate breakdown electric field strength (smaller standard deviation) and a higher breakdown electric field strength (average value). Is bigger). As a result, the gate breakdown voltage is improved, and the reliability of the semiconductor device can be improved.

[0019]

According to the present invention, the edge of the trench opening is etched and rounded in advance, whereby the edge of the trench opening can be rounded with a large radius of curvature. Electric field concentration at this location can be prevented. Therefore, the gate withstand voltage can be improved, and the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 1;

FIG. 3 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 3;

FIG. 5 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 3;

FIG. 6 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 4;

FIG. 7 is a sectional view of a manufacturing step of the embodiment of the present invention, following FIG. 6;

FIG. 8 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 7;

FIG. 9 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 8;

FIG. 10 is a sectional view showing a manufacturing step of the embodiment of the present invention, following FIG. 9;

FIG. 11 is a view showing a result obtained by an experiment on a relationship between an etching amount and a good ratio of gate withstand voltage in the process of FIG. 3;

FIG. 12 shows a gate breakdown electric field intensity distribution of a device having a trench manufactured by the manufacturing method of the present invention and a conventional manufacturing method, and (a) a distribution diagram according to the manufacturing method of the present invention;
(B) is a distribution diagram according to the conventional manufacturing method.

FIG. 13 shows a conventional method for forming a trench,
(A) to (c) are manufacturing process sectional views shown in a manufacturing process order.

[Explanation of symbols]

 Reference Signs List 1 silicon substrate 2 oxide film 2a recessed oxide film 3 etching groove 4 trench groove 5 trench opening 6 damage layer 7 sacrificial oxide film 8 gate oxide film 21 silicon substrate 22 oxide film 24 trench groove 25 trench opening 26 damage layer 27 sacrifice Oxide film 28 Gate oxide film A A portion to be an edge B A portion to be tapered C, D Sharp portion X Etching amount

Claims (2)

[Claims] In a method of manufacturing a semiconductor device having a trench gate structure, a surface layer in a region to be a trench opening is removed in advance by isotropic etching before trench etching. Production method. 2. The method according to claim 1, wherein the depth of the region to be removed by the isotropic etching is 70 nm to 1 nm from the surface of the region to be the trench opening.
2. The method according to claim 1, wherein the thickness is 70 nm.