WO2016031252A1 - Semiconductor device with trench gate - Google Patents

Semiconductor device with trench gate Download PDF

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Publication number
WO2016031252A1
WO2016031252A1 PCT/JP2015/004321 JP2015004321W WO2016031252A1 WO 2016031252 A1 WO2016031252 A1 WO 2016031252A1 JP 2015004321 W JP2015004321 W JP 2015004321W WO 2016031252 A1 WO2016031252 A1 WO 2016031252A1
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Prior art keywords
trench
semiconductor substrate
inclined flat
flat surface
top surface
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PCT/JP2015/004321
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French (fr)
Inventor
Katsuhiro Kutsuki
Sachiko Aoi
Yukihiko Watanabe
Akitaka Soeno
Atsushi Onogi
Tomohiro Mimura
Original Assignee
Kabushiki Kaisha Toyota Chuo Kenkyusho
Toyota Jidosha Kabushiki Kaisha
Denso Corporation
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Application filed by Kabushiki Kaisha Toyota Chuo Kenkyusho, Toyota Jidosha Kabushiki Kaisha, Denso Corporation filed Critical Kabushiki Kaisha Toyota Chuo Kenkyusho
Publication of WO2016031252A1 publication Critical patent/WO2016031252A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

Definitions

  • This specification discloses a semiconductor device of which resistance changes based on a potential of a trench gate provided in a semiconductor substrate of SiC and the like.
  • Patent Literature 1 discloses a manufacturing method of a semiconductor device (MOSFET or IGBT) that turns ON/OFF based on a potential of a gate electrode which is filled within a trench formed in a semiconductor substrate of SiC.
  • MOSFET or IGBT semiconductor device
  • a rounding process is performed at the corner portion of the trench after forming the trench in the semiconductor substrate by an anisotropic etching (especially see paragraph 0039).
  • a concentration of electric field is relaxed by rounding the corner portion of the trench so that the breakdown of the gate insulation film is prevented. This technique is practical and effective, and can increase a voltage that can be applied to a semiconductor device.
  • Patent Literature 1 Japanese Patent Application Publication No.2012-054347
  • An improvement of a breakdown voltage that is achieved by rounding the corner portion of the trench is limited.
  • the gate insulation film at the rounded corner portion of the trench may break down and the breakdown may accordingly determine an upper limit of the voltage that can be applied to the semiconductor device.
  • the gate insulation film and the gate electrode or the gate insulation film and the gate wire extends along a shoulder portion (a corner portion arranged at a boundary between the upper surface of the semiconductor substrate and a side surface of the trench) so that the gate insulation film covering the shoulder portion of the trench easily breaks down.
  • the rounding process for the shoulder portion of the trench may be not sufficient to prevent the breakdown of the gate insulation film covering the rounded shoulder portion of the trench.
  • New technique to prevent the breakdown of the gate insulation covering the shoulder portion of the trench is needed for improving the voltage that can be applied to a semiconductor device.
  • a semiconductor device disclosed in this specification comprises a semiconductor substrate in which a trench for a trench gate extends from a top surface of the semiconductor substrate in a depth direction of the semiconductor substrate.
  • An inclined flat surface is arranged in at least a portion between the top surface of the semiconductor substrate and a side surface of the trench. The inclined flat surface is inclined with respect to the top surface and the side surface.
  • the shoulder portion of the trench is not rounded, but instead, the inclined flat surface is provided.
  • the flat surface mentioned here is not a curved surface (rounded surface), but refers to a flat surface as defined in terms of geometry. Further, the inclined surface mentioned here inclines with respect to both the top surface of the semiconductor substrate and the side surface of the trench.
  • the concentration of electric field is more relaxed near the shoulder portion of the trench than the case of the rounded shoulder portion of the trench, and the upper limit of the voltage that can be applied to the semiconductor device can be further increased.
  • FIG. 1 is a figure showing a configuration of a trench in an embodiment.
  • FIG. 2 is a figure added with a gate insulation film, a gate electrode and an interlayer insulating film.
  • FIG. 3 is an enlarged figure showing a vicinity of a shoulder portion of FIG.2
  • FIG. 4 is a figure showing an edge portion of the trench in a longitudinal direction of the trench.
  • FIG. 5 is a figure showing a relation 1 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench.
  • FIG. 6 is a figure showing a relation 2 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench.
  • FIG. 1 is a figure showing a configuration of a trench in an embodiment.
  • FIG. 2 is a figure added with a gate insulation film, a gate electrode and an interlayer insulating film.
  • FIG. 3 is an enlarged figure showing a vicinity of a shoulder portion of
  • FIG. 7 is a figure showing a relation 3 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench.
  • FIG. 8 is a figure showing a relation 4 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench.
  • FIG. 9 is a figure showing a configuration of a semiconductor structure in a second embodiment.
  • FIG. 10 is a figure showing a configuration of a semiconductor structure in a third embodiment.
  • FIG. 11A is a figure showing a manufacturing method in a first embodiment.
  • FIG. 11B is a figure showing the manufacturing method in the first embodiment.
  • FIG. 12 is a figure showing a manufacturing method in a second embodiment.
  • FIG. 12B is a figure showing the manufacturing method in the second embodiment.
  • FIG. 12C is a figure showing the manufacturing method in the second embodiment.
  • a term "inclination angle” as used below means an angle formed with a top surface of a semiconductor substrate, and in particular, refers to an angle that is acute.
  • Aspect 1 An inclination angle ⁇ of a side surface of each trench in a range where a trench penetrates a base layer may be constant.
  • Aspect 2 The inclination angle ⁇ of Aspect 1 may be in a range of 85 to 90 degrees.
  • Aspect 3 An inclination angle ⁇ of an inclined flat surface may satisfy a relation ⁇ ⁇ ⁇ .
  • Aspect 4 Among adjacent trenches including a right-side trench and a left-side trench, a top surface of a semiconductor substrate may remain present between an inclined flat surface continuing into a right-side surface of the left-side trench and an inclined flat surface continuing into a left-side surface of the right-side trench.
  • a base contact region may be arranged in a range facing the top surface remaining between the inclined flat surfaces.
  • the inclined flat surface may be within a range of thickness of a source layer (or emitter layer) and does not reach a base (or body) layer.
  • a transitional range may be present between the top surface of the semiconductor substrate and the inclined flat surface.
  • a transitional range may be present between the inclined flat surface and the side surface of the trench.
  • Aspect 10 A 45-degree imaginary inclined line passing through a point of contact between the top surface of the semiconductor substrate in which an inclined flat surface has not been formed and the side surface of the trench may pass through the inclined flat surface.
  • the semiconductor substrate may be configured of SiC.
  • Aspect 12 The inclined flat surface may be configured of a particular crystal plane of a SiC single crystal.
  • Aspect 13 The inclined flat surface may be formed by crystal anisotropic etching of the SiC single crystal in which a trench has been formed.
  • Aspect 14 Etching may be performed without processing a mask that was utilized for forming the trench.
  • Aspect 15 Etching may be performed after enlarging a width of an opening in the mask utilized for forming the trench.
  • Aspect 16 The base layer may extend in a middle range of a drift layer located between adjacent trenches.
  • Aspect 17 A range facing the bottom surface of the trench may contain implanted impurities of a conductivity type opposite to that of the drift layer.
  • FIG. 1 shows a cross-section of a semiconductor substrate 20 in which a plurality of trenches 22 extending from a top surface 24 of the semiconductor substrate 20 in a depth direction of the semiconductor substrate 20 are disposed and an inclined flat surface 26 is arranged in a shoulder portion of each of the trenches 22.
  • FIG. 1 omits hatching that indicates the cross-section.
  • the plurality of trenches 22 extends so as to have their longer sides along a direction perpendicular to a sheet surface.
  • FIG. 1 shows adjacent trenches 22, one of which is a left-side trench 22a and the other of which is a right-side trench 22b.
  • the left-side and right-side trenches 22a and 22b are identical in shape to each other.
  • a source layer 32, a base layer (sometimes referred to as a body layer) 34, a drift layer 36, and a drain layer 38 are arranged in this order from an upper side.
  • the trenches 22 penetrate the source layer 32 and the base layer 34, and reach the drift layer 36, from the top surface 24 of the semiconductor substrate 20.
  • the semiconductor substrate 20 includes a top surface 24, which refers to both a top surface of the semiconductor substrate 20 in which the trenches 22 have not been formed and a top surface of the semiconductor substrate 20 that remains between the adjacent trenches 22a and 22b after the trenches 22 have been formed.
  • Each of the trenches 22 includes an inclined flat surface 26, a side surface 28 and a bottom surface 30.
  • the inclined flat surface 26 includes an inclined flat surface 26a located on a right side of the left-side trench 22a and an inclined flat surface 26b located on a left side of the right-side trench 22b.
  • the inclined flat surfaces 26a and 26b have shapes that are bilaterally symmetrical with each other. In case of explaining of matters that the inclined flat surfaces 26a and 26b share in common, alphabetical subscripts a and b may be omitted.
  • the bottom surface 30 of the trench 22 is parallel to the top surface 24 of the semiconductor substrate 20.
  • the side surface 28 of the trench 22 has an inclination angle ⁇ set in a range of 85 degrees or larger and 90 degrees or smaller (hereinafter referred to as 85 to 90 degrees).
  • the term "inclination angle" as used herein means an angle or, in principle, an acute angle formed with the top surface 24 of the semiconductor substrate 20.
  • the inclined flat surface 26 has an inclination angle ⁇ of 58.5 degrees. Since ⁇ ⁇ ⁇ , the trench 22 becomes wider toward the upper side.
  • the inclined flat surface 26 can be said to be a portion of the side surface of the trench 22. Therefore, the side surface of the trench 22 can be said to be configured by two-step tapered surfaces 26 and 28 that are different in inclination angle from each other.
  • the inclined flat surface 26 is arranged within the source layer 32 in a depth direction.
  • FIG. 1 illustrates a case where the inclination angle ⁇ of the side surface 28 is constant. Further, FIG. 1 also illustrates a case where L is a pitch between the adjacent trenches 22 and W1 is a width of the bottom surface 30 of the trench 22.
  • d3 is a depth of a boundary between the base layer 34 and the drain layer 36
  • d4 is a depth of the bottom surface 30 of the trench 22.
  • d3 ⁇ d4.
  • FIG. 2 shows a cross-section of a semiconductor device including a gate insulating film 42 disposed on the inclined flat surface 26, on the side surface 28, and on the bottom surface 30, a trench gate electrode 44 filling an inner side of the gate insulating film 42, an interlayer insulating film 46 covering a top surface of the trench gate electrode 44, and a source electrode 48 disposed on a top surface of the interlayer insulating film 46.
  • the gate insulating film 42 and the trench gate electrode 44 configure a trench gate 43.
  • the source electrode 48 is in contact with the source layer 32.
  • a drain electrode 40 Arranged on a back surface of the semiconductor substrate 20 is a drain electrode 40 that is in contact with the drain layer 38.
  • the trench gate electrode 44 is insulated from the source electrode 48 by the interlayer insulating film 46, and is connected to a gate wire 50 (described below with reference to FIG. 4) in a portion of the cross-section of the semiconductor device (not shown).
  • the source layer 32 is of an n + type.
  • the base layer 34 is of a p - type.
  • the drift layer 36 is of an n - type.
  • the drain layer 38 is of an n + type.
  • An npn structure is disposed between the source electrode 48 and the drain electrode 40, and in an absence of a potential being applied to the trench gate electrode 44, a resistance between the source electrode 48 and the drain electrode 40 is high.
  • Application of a positive voltage to the trench gate electrode 44 causes the base layer 34, which is located in a position facing the trench gate electrode 44 via the gate insulating film 42, to be inverted into an n type, thus decreasing the resistance between the source electrode 48 and the drain electrode 40.
  • the semiconductor device thus configured operates as a MOSFET.
  • FIG. 3 is an enlarged figure showing a vicinity of the shoulder portion of the trench 22.
  • the top surface 24 of the semiconductor substrate 20 is a (000-1) plane, and the trench 22 extends along a [1-100] direction.
  • the inclined flat surface 26 is a (03-38) plane.
  • the (03-38) plane is inclined at 58.5 degrees with respect to the (000-1) plane. That is, the inclination angle ⁇ of the inclined flat surface 26 is 58.5 degrees.
  • FIG. 4 is a figure showing an edge portion of the trench 22 in a longitudinal direction whose longer sides extend along the [1-100] direction.
  • the inclined flat surface 26 is arranged in the shoulder portion of the trench 22. That is, the inclined flat surface 26 is provided between the top surface 24 and the side surface 28.
  • the gate insulating film 42 is arranged in a range extending from the top surface 24 to the side surface 28 through the inclined flat surface 26.
  • the gate wire 50 is provided on a top surface of the semiconductor substrate.
  • the gate wire 50 is connected to the trench gate electrode 44. At a connection between the gate wire 50 and the trench gate electrode 44, a relation holds in which the trench gate electrode 44 or the gate wire 50 faces the inclined flat surface 26 via the gate insulating film 42.
  • Patent Literature 1 shows a comparison result obtained by changing only shapes of the shoulder portion of the trench, with other conditions being equal. It is confirmed that with the shoulder portion as the inclined flat surface, the upper limit of the possible voltage applied between the source electrode 48 and the drain electrode 40 can be raised to 60 volts.
  • the top surface 24 of the semiconductor substrate 20 and the inclined flat surface 26 are in contact with each other, and the inclined flat surface 26 and the side surface 28 of the trench 22 are in contact with each other.
  • the inclined flat surface 26 is present in the shoulder portion of the trench 22, and a curved surface may be present in at least a portion between the top surface 24 and the inclined flat surface 26.
  • a curved surface may be present in at least a portion between the inclined flat surface 26 and the side surface 28.
  • assumed is an imaginary inclined line passing through a point of contact between the top surface 24 of the semiconductor substrate 20 in which the inclined flat surface 26 has not been formed and the side surface 28 of the trench 22, and being inclined at 45 degrees with respect to the top surface 24 of the semiconductor substrate 20.
  • a point of intersection between the semiconductor substrate 20 in which the inclined flat surface 26 has been formed and the imaginary inclined line is included in a range of the inclined flat surface 26, a presence of the inclined flat surface 26 brings about an effect of improving a breakdown voltage.
  • the inclination angle ⁇ of the side surface 28 of the trench 22 be in the range of 85 to 90 degrees.
  • the inclination angle ⁇ is set in this range, channel resistance of when the MOSFET is turned on is low. This makes it possible to fill the trench 22 with the trench gate electrode 44 without leaving a gap.
  • An inclination angle necessary for bringing about the aforementioned effect is the inclination angle ⁇ of the side surface 28 in a range where the trench 22 penetrates the base layer 34.
  • An inclination angle ⁇ of the side surface 28 of the trench 22 at a depth where the trench 22 is into the drift layer 36 does not need to be in the aforementioned numerical range.
  • FIG. 5 illustrates a case where an inclination angle ⁇ of a side surface 28c of a trench 22 in a range where the trench 22 penetrates a base layer 34 is equal to an inclination angle ⁇ of a side surface 28d of the trench 22 in a range where the trench 22 is into the drift layer 36.
  • ⁇ ⁇ holds.
  • ⁇ > ⁇ may hold as shown in FIG. 6, and ⁇ ⁇ ⁇ may also hold as shown in FIG. 7.
  • the inclination angle ⁇ is equal to an inclination angle of a segment connecting y1 with y2 in FIG. 1, that the inclination angle ⁇ is equal to an inclination angle of a segment connecting y2 with y3 in FIG.
  • the inclination angle ⁇ is equal to an inclination angle of a segment connecting y3 with y4 in FIG. 1.
  • the inclination angle ⁇ is 90 degrees or larger, as the side surface 28d is inclined in such a direction that the trench 22 becomes wider toward a lower side.
  • the inclination angle in this case refers to an angle that is obtuse.
  • ⁇ ⁇ ⁇ may hold under a condition where the side surface is inclined in such a direction that the trench becomes wider toward the upper side. That is, it is possible that ⁇ ⁇ ⁇ ⁇ 90 degrees may hold.
  • the trench 22 may have a rounded side surface and a rounded bottom surface in a range where the trench 22 is into the drift layer 36.
  • the p-type base layer 34 may have a p-type region 34e extending upward from a center of the p-type base layer 34 between right and left halves of the p-type base layer 34. It is preferable that the region 34e be exposed on the top surface 24 of the semiconductor substrate 20 that remains between the adjacent trenches 22 and contain such an impurity concentration as to make ohmic contact with the source electrode 48.
  • the region 34e operates as a base contact region to make a potential of the base layer 34 equal to a potential of the source electrode 48 or the source layer 32. Stabilization of the potential of the base layer 34 allows the MOSFET to stably operate.
  • a p-type base layer 34 may have a p-type region 34f extending downward from the center of the p-type base layer 34 between right and left halves of the p-type base layer 34.
  • the region 34f enters a drift region 36 between adjacent trenches 22.
  • the region 34f relaxes a concentration of electric field near a corner portion of a bottom surface side of each of the trenches 22 and prevents the breakdown of a gate insulating film near a corner portion of the bottom surface side.
  • a p-type region 54 may be provided in a range of the drift layer 36 that faces a bottom surface 30 of each of the trenches 22.
  • the p-type region 54 relaxes the concentration of electric field near the corner portion of the bottom surface side of each of the trenches 22 and prevents the breakdown of the gate insulating film near the corner portion of the bottom surface side. It is preferable that the p-type region 54 be electrically connected to the source electrode 48 via a portion of the cross-section (not shown), although the p-type region 54 may alternatively be floated.
  • FIGS. 11A and 11B show an example of a method for forming the inclined flat surface 26.
  • a mask 52 is used for forming a trench 22.
  • the mask 52 is configured of SiO 2 , and has an opening formed in a range where the trench 22 is to be formed.
  • the trench 22 is formed by performing RIE (Reactive Ion Etching) from above the mask 52. By changing conditions of the RIE, an inclination angle ⁇ of a side surface 28 of the trench 22 can be adjusted to the range of 85 to 90 degrees.
  • FIG. 11B shows a result of CDE (Chemical Dry Etching) performed with use of CF 4 + H 2 , following the formation of the trench 22. Performing the CDE with use of CF 4 + H 2 forms an inclined flat surface 26.
  • CDE Chemical Dry Etching
  • the CDE is isotropic etching, which presumably makes it difficult for a particular crystal plane to be exposed, the flat surface is formed.
  • etching damage is applied near a top surface 24 of a semiconductor substrate 20 even outside of the range where the trench is to be formed.
  • a particular crystal plane is exposed by covering, with the mask 52, the top surface of the semiconductor substrate 20 near which the etching damage has been applied, and then performing the CDE on the top surface. This makes it possible to form the inclined flat surface 26.
  • FIG. 12A is equivalent to FIG. 11A.
  • FIG. 12B shows a state, following the state shown in FIG. 12A, in which wet etching has been performed with use of BHF (Buffered Hydrogen Fluoride). A portion of the mask 52 is etched, so that a width of the opening is made greater. Note that the width of the opening, which is denoted by L1 in FIG. 12A, is denoted by L2 in FIG. 12B, and that L1 has been widened to L2.
  • FIG. 12C shows a state in which RIE has been performed with use of SF 6 . Changing conditions of RIE can bring about a result that a particular crystal plane has been exposed. This makes it possible to obtain the inclined flat surface 26.
  • Table 2 shows methods for forming an inclined flat surface in a shoulder portion of a trench.
  • What is important in the present technique is not a method for forming an inclined flat surface. What is important is a finding that the upper limit of the voltage that can be applied between the source and the drain can be raised by forming a shoulder portion of a trench as an inclined flat surface instead of rounding the shoulder portion of the trench.
  • the methods for forming an inclined flat surface are not limited to those shown in Table 2.
  • An inclined flat surface whose inclination angle ⁇ has been adjusted as required can be formed by utilizing a known technique of crystal anisotropic etching that differs in etching rate depending on crystal planes. Alternatively, a physical anisotropic etching may be implemented to expose a particular crystal plane so as to form an inclined flat surface whose inclination angle ⁇ has been adjusted as required.
  • the rounding process for the shoulder portion of the trench does not allow rounded shoulder portions to have a constant curvature radius, resulting in a greater variation from one semiconductor device to another.
  • the technique of forming an inclined flat surface eliminates such a variation, enabling mass production of semiconductor devices having a constant quality.
  • the present technique may be applied to an IGBT, although the embodiments described above are embodiments in which the present technique is applied to MOSFETs.
  • the inclination angles of an inclined flat surface and a side surface that are arranged on the right side of a trench are bilaterally symmetrical to the inclination angles of an inclined flat surface and a side surface that are formed on the left side of the trench.
  • the top surface of the semiconductor substrate may include an off angle. In this case, due to an effect of the off angle, the bilateral symmetry is lost.

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Abstract

A semiconductor device is provided with a semiconductor substrate in which a trench for a trench gate extends from a top surface of the semiconductor substrate in a depth direction of the semiconductor substrate. An inclined flat surface is arranged in at least a portion between the top surface of the semiconductor substrate and a side surface of the trench, and the inclined flat surface is inclined with respect to the top surface and the side surface.

Description

SEMICONDUCTOR DEVICE WITH TRENCH GATE
This specification discloses a semiconductor device of which resistance changes based on a potential of a trench gate provided in a semiconductor substrate of SiC and the like.
Patent Literature 1 discloses a manufacturing method of a semiconductor device (MOSFET or IGBT) that turns ON/OFF based on a potential of a gate electrode which is filled within a trench formed in a semiconductor substrate of SiC. In a technique of Patent Literature 1, to prevent a breakdown of a gate insulation film at a corner portion of the trench, a rounding process is performed at the corner portion of the trench after forming the trench in the semiconductor substrate by an anisotropic etching (especially see paragraph 0039). In a technique of Patent Literature 1, a concentration of electric field is relaxed by rounding the corner portion of the trench so that the breakdown of the gate insulation film is prevented. This technique is practical and effective, and can increase a voltage that can be applied to a semiconductor device.
[Patent Literature 1] Japanese Patent Application Publication No.2012-054347
An improvement of a breakdown voltage that is achieved by rounding the corner portion of the trench is limited. When the voltage applied to the semiconductor device is further increased, the gate insulation film at the rounded corner portion of the trench may break down and the breakdown may accordingly determine an upper limit of the voltage that can be applied to the semiconductor device. Especially, at a connection portion between a gate wire formed above a upper surface of the semiconductor substrate and a trench gate electrode filled within the trench, the gate insulation film and the gate electrode or the gate insulation film and the gate wire extends along a shoulder portion (a corner portion arranged at a boundary between the upper surface of the semiconductor substrate and a side surface of the trench) so that the gate insulation film covering the shoulder portion of the trench easily breaks down. The rounding process for the shoulder portion of the trench may be not sufficient to prevent the breakdown of the gate insulation film covering the rounded shoulder portion of the trench. New technique to prevent the breakdown of the gate insulation covering the shoulder portion of the trench is needed for improving the voltage that can be applied to a semiconductor device.
A semiconductor device disclosed in this specification comprises a semiconductor substrate in which a trench for a trench gate extends from a top surface of the semiconductor substrate in a depth direction of the semiconductor substrate. An inclined flat surface is arranged in at least a portion between the top surface of the semiconductor substrate and a side surface of the trench. The inclined flat surface is inclined with respect to the top surface and the side surface.
In the above semiconductor device, the shoulder portion of the trench is not rounded, but instead, the inclined flat surface is provided. The flat surface mentioned here is not a curved surface (rounded surface), but refers to a flat surface as defined in terms of geometry. Further, the inclined surface mentioned here inclines with respect to both the top surface of the semiconductor substrate and the side surface of the trench.
According to the above semiconductor device, the concentration of electric field is more relaxed near the shoulder portion of the trench than the case of the rounded shoulder portion of the trench, and the upper limit of the voltage that can be applied to the semiconductor device can be further increased.
FIG. 1 is a figure showing a configuration of a trench in an embodiment. FIG. 2 is a figure added with a gate insulation film, a gate electrode and an interlayer insulating film. FIG. 3 is an enlarged figure showing a vicinity of a shoulder portion of FIG.2 FIG. 4 is a figure showing an edge portion of the trench in a longitudinal direction of the trench. FIG. 5 is a figure showing a relation 1 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench. FIG. 6 is a figure showing a relation 2 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench. FIG. 7 is a figure showing a relation 3 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench. FIG. 8 is a figure showing a relation 4 between an inclination angle of an intermediate depth of a trench and an inclination angle of a deeper depth of the trench. FIG. 9 is a figure showing a configuration of a semiconductor structure in a second embodiment. FIG. 10 is a figure showing a configuration of a semiconductor structure in a third embodiment. FIG. 11A is a figure showing a manufacturing method in a first embodiment. FIG. 11B is a figure showing the manufacturing method in the first embodiment. FIG. 12 is a figure showing a manufacturing method in a second embodiment. FIG. 12B is a figure showing the manufacturing method in the second embodiment. FIG. 12C is a figure showing the manufacturing method in the second embodiment.
Preferred aspects of below embodiments will be listed. Each of the following aspects is encompassed in the technical scope of the claims. A term "inclination angle" as used below means an angle formed with a top surface of a semiconductor substrate, and in particular, refers to an angle that is acute.
Aspect 1: An inclination angle α of a side surface of each trench in a range where a trench penetrates a base layer may be constant.
Aspect 2: The inclination angle α of Aspect 1 may be in a range of 85 to 90 degrees.
Aspect 3: An inclination angle β of an inclined flat surface may satisfy a relation β < α.
Aspect 4: Among adjacent trenches including a right-side trench and a left-side trench, a top surface of a semiconductor substrate may remain present between an inclined flat surface continuing into a right-side surface of the left-side trench and an inclined flat surface continuing into a left-side surface of the right-side trench.
Aspect 5: A base contact region may be arranged in a range facing the top surface remaining between the inclined flat surfaces.
Aspect 6: An inclination angle θ of the side surface of the trench near a bottom surface of the trench may satisfy any one of the following relations: θ < α; θ ＝ α; and θ >α.
Aspect 7: The inclined flat surface may be within a range of thickness of a source layer (or emitter layer) and does not reach a base (or body) layer.
Aspect 8: A transitional range may be present between the top surface of the semiconductor substrate and the inclined flat surface.
Aspect 9: A transitional range may be present between the inclined flat surface and the side surface of the trench.
Aspect 10: A 45-degree imaginary inclined line passing through a point of contact between the top surface of the semiconductor substrate in which an inclined flat surface has not been formed and the side surface of the trench may pass through the inclined flat surface.
Aspect 11: The semiconductor substrate may be configured of SiC.
Aspect 12: The inclined flat surface may be configured of a particular crystal plane of a SiC single crystal.
Aspect 13: The inclined flat surface may be formed by crystal anisotropic etching of the SiC single crystal in which a trench has been formed.
Aspect 14: Etching may be performed without processing a mask that was utilized for forming the trench.
Aspect 15: Etching may be performed after enlarging a width of an opening in the mask utilized for forming the trench.
Aspect 16: The base layer may extend in a middle range of a drift layer located between adjacent trenches.
Aspect 17: A range facing the bottom surface of the trench may contain implanted impurities of a conductivity type opposite to that of the drift layer.
Embodiments
FIG. 1 shows a cross-section of a semiconductor substrate 20 in which a plurality of trenches 22 extending from a top surface 24 of the semiconductor substrate 20 in a depth direction of the semiconductor substrate 20 are disposed and an inclined flat surface 26 is arranged in a shoulder portion of each of the trenches 22. For the sake of clear illustration, FIG. 1 omits hatching that indicates the cross-section. The plurality of trenches 22 extends so as to have their longer sides along a direction perpendicular to a sheet surface. FIG. 1 shows adjacent trenches 22, one of which is a left-side trench 22a and the other of which is a right-side trench 22b. The left-side and right- side trenches 22a and 22b are identical in shape to each other. In a case of explaining matters that the left-side and right- side trenches 22a and 22b share in common, alphabetical subscripts a and b may be omitted. In the semiconductor substrate 20, a source layer 32, a base layer (sometimes referred to as a body layer) 34, a drift layer 36, and a drain layer 38 (shown in FIG. 2) are arranged in this order from an upper side. The trenches 22 penetrate the source layer 32 and the base layer 34, and reach the drift layer 36, from the top surface 24 of the semiconductor substrate 20.
The semiconductor substrate 20 includes a top surface 24, which refers to both a top surface of the semiconductor substrate 20 in which the trenches 22 have not been formed and a top surface of the semiconductor substrate 20 that remains between the adjacent trenches 22a and 22b after the trenches 22 have been formed. Each of the trenches 22 includes an inclined flat surface 26, a side surface 28 and a bottom surface 30. In FIG. 1, the inclined flat surface 26 includes an inclined flat surface 26a located on a right side of the left-side trench 22a and an inclined flat surface 26b located on a left side of the right-side trench 22b. The inclined flat surfaces 26a and 26b have shapes that are bilaterally symmetrical with each other. In case of explaining of matters that the inclined flat surfaces 26a and 26b share in common, alphabetical subscripts a and b may be omitted.
The bottom surface 30 of the trench 22 is parallel to the top surface 24 of the semiconductor substrate 20. The side surface 28 of the trench 22 has an inclination angle α set in a range of 85 degrees or larger and 90 degrees or smaller (hereinafter referred to as 85 to 90 degrees). The term "inclination angle" as used herein means an angle or, in principle, an acute angle formed with the top surface 24 of the semiconductor substrate 20. The inclined flat surface 26 has an inclination angle β of 58.5 degrees. Since β < α, the trench 22 becomes wider toward the upper side. The inclined flat surface 26 can be said to be a portion of the side surface of the trench 22. Therefore, the side surface of the trench 22 can be said to be configured by two-step tapered surfaces 26 and 28 that are different in inclination angle from each other.
A depth (a depth is expressed herein by a distance from the top surface 24) d1 to a position y3 where the inclined flat surface 26 and the side surface 28 make contact with each other is equal to or shallower than a depth d2 of the source layer 32. That is, d1 = d2, or d1 < d2. The inclined flat surface 26 is arranged within the source layer 32 in a depth direction. FIG. 1 illustrates a case where the inclination angle α of the side surface 28 is constant. Further, FIG. 1 also illustrates a case where L is a pitch between the adjacent trenches 22 and W1 is a width of the bottom surface 30 of the trench 22. d3 is a depth of a boundary between the base layer 34 and the drain layer 36, and d4 is a depth of the bottom surface 30 of the trench 22. Note that d3 < d4. In this case, a half width W3 of the top surface 24 of the semiconductor substrate 20 that remains between the adjacent trenches 22 is expressed by the following equation:

W3 = L/2 - W1/2 - (d4 - d1)/tanα - (d1)/tanβ.

In the embodiment shown in FIG. 1, adjustments have been made so that a relation W3 > 0 holds. That is, adjustments have been made so that a relation holds in which the top surface 24 of the semiconductor substrate 20 remains between the adjacent trenches 22. When the adjustments have been made so that the relation holds in which the top surface 24 of the semiconductor substrate 20 remains between the adjacent trenches 22, an area of contact required between an after-mentioned source electrode 48 and the source layer 32 can be ensured, and an after-mentioned base contact region 34e can be formed in a position facing the top surface 24.
FIG. 2 shows a cross-section of a semiconductor device including a gate insulating film 42 disposed on the inclined flat surface 26, on the side surface 28, and on the bottom surface 30, a trench gate electrode 44 filling an inner side of the gate insulating film 42, an interlayer insulating film 46 covering a top surface of the trench gate electrode 44, and a source electrode 48 disposed on a top surface of the interlayer insulating film 46. The gate insulating film 42 and the trench gate electrode 44 configure a trench gate 43. The source electrode 48 is in contact with the source layer 32. Arranged on a back surface of the semiconductor substrate 20 is a drain electrode 40 that is in contact with the drain layer 38. The trench gate electrode 44 is insulated from the source electrode 48 by the interlayer insulating film 46, and is connected to a gate wire 50 (described below with reference to FIG. 4) in a portion of the cross-section of the semiconductor device (not shown).
The source layer 32 is of an n+ type. The base layer 34 is of a p- type. The drift layer 36 is of an n- type. The drain layer 38 is of an n+ type. An npn structure is disposed between the source electrode 48 and the drain electrode 40, and in an absence of a potential being applied to the trench gate electrode 44, a resistance between the source electrode 48 and the drain electrode 40 is high. Application of a positive voltage to the trench gate electrode 44 causes the base layer 34, which is located in a position facing the trench gate electrode 44 via the gate insulating film 42, to be inverted into an n type, thus decreasing the resistance between the source electrode 48 and the drain electrode 40. The semiconductor device thus configured operates as a MOSFET.
FIG. 3 is an enlarged figure showing a vicinity of the shoulder portion of the trench 22. The top surface 24 of the semiconductor substrate 20 is a (000-1) plane, and the trench 22 extends along a [1-100] direction. The inclined flat surface 26 is a (03-38) plane. The (03-38) plane is inclined at 58.5 degrees with respect to the (000-1) plane. That is, the inclination angle β of the inclined flat surface 26 is 58.5 degrees.
FIG. 4 is a figure showing an edge portion of the trench 22 in a longitudinal direction whose longer sides extend along the [1-100] direction. At the edge portion of the trench 22 in the longitudinal direction, too, the inclined flat surface 26 is arranged in the shoulder portion of the trench 22. That is, the inclined flat surface 26 is provided between the top surface 24 and the side surface 28. At the edge portion of the trench 22 in the longitudinal direction, the gate insulating film 42 is arranged in a range extending from the top surface 24 to the side surface 28 through the inclined flat surface 26. The gate wire 50 is provided on a top surface of the semiconductor substrate. The gate wire 50 is connected to the trench gate electrode 44. At a connection between the gate wire 50 and the trench gate electrode 44, a relation holds in which the trench gate electrode 44 or the gate wire 50 faces the inclined flat surface 26 via the gate insulating film 42.
When, in an absence of a positive voltage being applied to the trench gate electrode 44, the voltage that is applied between the source electrode 48 and the drain electrode 40 is gradually increased, the gate insulating film 42 covering the shoulder portion of the trench 22 breaks down at a certain point in time. This phenomenon determines an upper limit of the possible voltage that can be applied between the source electrode 48 and the drain electrode 40. If the shoulder portion of the trench 22 forms an acute angle, electric field is concentrated significantly near the shoulder portion, thus making it easy for the gate insulating film covering the shoulder portion to be broken down. In order to prevent such breakdown, the technique of Patent Literature 1 has been developed in which the shoulder portion of the trench is rounded. Rounding the shoulder portion relaxes the concentration of electric field, thus making it difficult for the gate insulating film covering the shoulder portion to be broken down. However, the technique of Patent Literature 1 can only bring about a limited effect. The present embodiment provides the inclined flat surface in the shoulder portion instead of rounding the shoulder portion. The provision of the inclined flat surface in the shoulder portion further relaxes the concentration of electric field, thus making it significantly difficult for the gate insulating film to be broken down. Table 1 shows a comparison result obtained by changing only shapes of the shoulder portion of the trench, with other conditions being equal. It is confirmed that with the shoulder portion as the inclined flat surface, the upper limit of the possible voltage applied between the source electrode 48 and the drain electrode 40 can be raised to 60 volts.
[Corrected under Rule 26, 30.09.2015]
Figure WO-DOC-TABLE-1
In FIG. 1, the top surface 24 of the semiconductor substrate 20 and the inclined flat surface 26 are in contact with each other, and the inclined flat surface 26 and the side surface 28 of the trench 22 are in contact with each other. What is important is that the inclined flat surface 26 is present in the shoulder portion of the trench 22, and a curved surface may be present in at least a portion between the top surface 24 and the inclined flat surface 26. Alternatively, a curved surface may be present in at least a portion between the inclined flat surface 26 and the side surface 28. Herein assumed is an imaginary inclined line passing through a point of contact between the top surface 24 of the semiconductor substrate 20 in which the inclined flat surface 26 has not been formed and the side surface 28 of the trench 22, and being inclined at 45 degrees with respect to the top surface 24 of the semiconductor substrate 20. Provided that a point of intersection between the semiconductor substrate 20 in which the inclined flat surface 26 has been formed and the imaginary inclined line is included in a range of the inclined flat surface 26, a presence of the inclined flat surface 26 brings about an effect of improving a breakdown voltage.
It is preferable that the inclination angle α of the side surface 28 of the trench 22 be in the range of 85 to 90 degrees. When the inclination angle α is set in this range, channel resistance of when the MOSFET is turned on is low. This makes it possible to fill the trench 22 with the trench gate electrode 44 without leaving a gap. An inclination angle necessary for bringing about the aforementioned effect is the inclination angle α of the side surface 28 in a range where the trench 22 penetrates the base layer 34. An inclination angle θ of the side surface 28 of the trench 22 at a depth where the trench 22 is into the drift layer 36 does not need to be in the aforementioned numerical range.
FIG. 5 illustrates a case where an inclination angle α of a side surface 28c of a trench 22 in a range where the trench 22 penetrates a base layer 34 is equal to an inclination angle θ of a side surface 28d of the trench 22 in a range where the trench 22 is into the drift layer 36. However, it is not necessary that α ＝ θ holds. Alternatively, α > θ may hold as shown in FIG. 6, and α < θ may also hold as shown in FIG. 7. It should be noted that the inclination angle θ is equal to an inclination angle of a segment connecting y1 with y2 in FIG. 1, that the inclination angle α is equal to an inclination angle of a segment connecting y2 with y3 in FIG. 1, and that the inclination angle β is equal to an inclination angle of a segment connecting y3 with y4 in FIG. 1. In a case of FIG. 7, the inclination angle θ is 90 degrees or larger, as the side surface 28d is inclined in such a direction that the trench 22 becomes wider toward a lower side. In a case where the side surface of the trench is inclined in such a direction that the trench becomes wider toward the lower side, the inclination angle in this case refers to an angle that is obtuse. It should be noted that under a condition where the side surface is inclined in such a direction that the trench becomes wider toward the upper side, α < θ may hold. That is, it is possible that α < θ < 90 degrees may hold. As shown in FIG. 8, the trench 22 may have a rounded side surface and a rounded bottom surface in a range where the trench 22 is into the drift layer 36.
As shown in FIG. 9, the p-type base layer 34 may have a p-type region 34e extending upward from a center of the p-type base layer 34 between right and left halves of the p-type base layer 34. It is preferable that the region 34e be exposed on the top surface 24 of the semiconductor substrate 20 that remains between the adjacent trenches 22 and contain such an impurity concentration as to make ohmic contact with the source electrode 48. The region 34e operates as a base contact region to make a potential of the base layer 34 equal to a potential of the source electrode 48 or the source layer 32. Stabilization of the potential of the base layer 34 allows the MOSFET to stably operate.
As shown in FIG. 9, a p-type base layer 34 may have a p-type region 34f extending downward from the center of the p-type base layer 34 between right and left halves of the p-type base layer 34. The region 34f enters a drift region 36 between adjacent trenches 22. The region 34f relaxes a concentration of electric field near a corner portion of a bottom surface side of each of the trenches 22 and prevents the breakdown of a gate insulating film near a corner portion of the bottom surface side. Alternatively, as shown in FIG. 10, a p-type region 54 may be provided in a range of the drift layer 36 that faces a bottom surface 30 of each of the trenches 22. The p-type region 54, too, relaxes the concentration of electric field near the corner portion of the bottom surface side of each of the trenches 22 and prevents the breakdown of the gate insulating film near the corner portion of the bottom surface side. It is preferable that the p-type region 54 be electrically connected to the source electrode 48 via a portion of the cross-section (not shown), although the p-type region 54 may alternatively be floated.
FIGS. 11A and 11B show an example of a method for forming the inclined flat surface 26. A mask 52 is used for forming a trench 22. The mask 52 is configured of SiO2, and has an opening formed in a range where the trench 22 is to be formed. The trench 22 is formed by performing RIE (Reactive Ion Etching) from above the mask 52. By changing conditions of the RIE, an inclination angle α of a side surface 28 of the trench 22 can be adjusted to the range of 85 to 90 degrees. FIG. 11B shows a result of CDE (Chemical Dry Etching) performed with use of CF4 + H2, following the formation of the trench 22. Performing the CDE with use of CF4 + H2 forms an inclined flat surface 26. Although the CDE is isotropic etching, which presumably makes it difficult for a particular crystal plane to be exposed, the flat surface is formed. During the RIE during which the trench is being formed, etching damage is applied near a top surface 24 of a semiconductor substrate 20 even outside of the range where the trench is to be formed. A particular crystal plane is exposed by covering, with the mask 52, the top surface of the semiconductor substrate 20 near which the etching damage has been applied, and then performing the CDE on the top surface. This makes it possible to form the inclined flat surface 26. Alternatively, it is possible to perform RIE instead of performing the CDE with use of CF4 + H2.
FIG. 12A is equivalent to FIG. 11A. FIG. 12B shows a state, following the state shown in FIG. 12A, in which wet etching has been performed with use of BHF (Buffered Hydrogen Fluoride). A portion of the mask 52 is etched, so that a width of the opening is made greater. Note that the width of the opening, which is denoted by L1 in FIG. 12A, is denoted by L2 in FIG. 12B, and that L1 has been widened to L2. FIG. 12C shows a state in which RIE has been performed with use of SF6. Changing conditions of RIE can bring about a result that a particular crystal plane has been exposed. This makes it possible to obtain the inclined flat surface 26.
[Corrected under Rule 26, 30.09.2015]
Table 2 shows methods for forming an inclined flat surface in a shoulder portion of a trench.
Figure WO-DOC-TABLE-2
What is important in the present technique is not a method for forming an inclined flat surface. What is important is a finding that the upper limit of the voltage that can be applied between the source and the drain can be raised by forming a shoulder portion of a trench as an inclined flat surface instead of rounding the shoulder portion of the trench. The methods for forming an inclined flat surface are not limited to those shown in Table 2. An inclined flat surface whose inclination angle β has been adjusted as required can be formed by utilizing a known technique of crystal anisotropic etching that differs in etching rate depending on crystal planes. Alternatively, a physical anisotropic etching may be implemented to expose a particular crystal plane so as to form an inclined flat surface whose inclination angle β has been adjusted as required.
The rounding process for the shoulder portion of the trench does not allow rounded shoulder portions to have a constant curvature radius, resulting in a greater variation from one semiconductor device to another. The technique of forming an inclined flat surface eliminates such a variation, enabling mass production of semiconductor devices having a constant quality.
Specific examples of the present invention has been described in detail, however, these are mere exemplary indications and thus do not limit the scope of the claims. The art described in the claims include modifications and variations of the specific examples presented above. For example, the present technique may be applied to an IGBT, although the embodiments described above are embodiments in which the present technique is applied to MOSFETs. According to the embodiments described above, the inclination angles of an inclined flat surface and a side surface that are arranged on the right side of a trench are bilaterally symmetrical to the inclination angles of an inclined flat surface and a side surface that are formed on the left side of the trench. However, the top surface of the semiconductor substrate may include an off angle. In this case, due to an effect of the off angle, the bilateral symmetry is lost. Even if bilateral asymmetry is caused by the effect of the off angle, advantages of forming the inclined flat surfaces will not be lost. Technical features described in the description and the drawings may technically be useful alone or in various combinations, and are not limited to the combinations as originally claimed. Further, the art described in the description and the drawings may concurrently achieve a plurality of aims, and technical significance thereof resides in achieving any one of such aims.

Claims (7)

  1. A semiconductor device comprising:
    a semiconductor substrate in which a trench for a trench gate extends from a top surface of the semiconductor substrate in a depth direction of the semiconductor substrate,
    wherein an inclined flat surface is arranged in at least a portion between the top surface of the semiconductor substrate and a side surface of the trench, and
    the inclined flat surface is inclined with respect to the top surface and the side surface.
  2. The semiconductor device according to claim 1, further comprising:
    an insulation film formed in at least a range extending from the inclined flat surface to the side surface; and
    a gate electrode facing the inclined surface and the side surface via the insulation film.
  3. The semiconductor device according to claim 1 or 2, wherein
    an angle formed by the top surface and the inclined flat surface is smaller than an angle formed by the top surface and the side surface.
  4. The semiconductor device according to any one of claims 1 to 3, wherein
    the semiconductor substrate is configured of a single crystal, and
    the inclined flat surface is configured of a crystal plane of the single crystal.
  5. The semiconductor device according to claim 4, wherein
    the semiconductor substrate is configured of SiC, and
    the inclined flat surface is configured of a (03-38) plane or a (1-102) plane.
  6. The semiconductor device according to any one of claims 1 to 5, wherein
    the semiconductor substrate includes a source layer, a base layer, and a drift layer, which are laminated in this order from the top surface of the semiconductor layer in the depth direction,
    the trench penetrates the source layer and the base layer, and reaches the drift layer, and
    the inclined flat surface is arranged within the source layer in the depth direction.
  7. The semiconductor device according to any one of claims 1 to 6, wherein
    at least two trenches are provided in the semiconductor substrate, and
    the top surface of the semiconductor substrate is present between adjacent inclined flat surfaces.
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