JP2012160601A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly-reliable, low-resistance semiconductor device.SOLUTION: A manufacturing method of a semiconductor device of an embodiment comprises: a step of forming a polysilicon on a first surface 5 on the opposite side of a first conductivity-type semiconductor layer 1, of a first conductivity-type first semiconductor layer 2 formed on the semiconductor layer 1; a step of etching the polysilicon; a step of forming an interlayer insulating film 11; a step of forming a mask 12; a step of wet-etching the interlayer insulating film 11; a step of dry-etching the interlayer insulating film 11; a step of forming a first electrode 23; and a step of forming a second electrode 22. The step of wet-etching forms a recess 13 on a surface of the interlayer insulating film 11 on a gate electrode 8. The step of dry-etching dry-etches the entire surface of the interlayer insulating film 11 having the recess 13 after the mask 12 is removed.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  In MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the miniaturization of the manufacturing process leads to an increase in channel density in the chip and a reduction in resistance. Since a MOSFET having a trench gate electrode can form a channel at a higher density than a MOSFET having a planar gate electrode, a trench gate structure is advantageous for a low resistance MOSFET. In addition, the trench type gate structure MOSFET can have a larger contact area between the source electrode and the source layer than the planar type gate structure MOSFET, so that the resistance can be further reduced.

JP 2009-38208 A

  A highly reliable low-resistance semiconductor device is provided.

  In the method of manufacturing a semiconductor device according to the embodiment, the semiconductor of the first conductivity type first semiconductor layer has a lower impurity concentration of the first conductivity type than the semiconductor layer formed on the first conductivity type semiconductor layer. A step of forming polysilicon on the first surface opposite to the layer, a step of etching the polysilicon, a step of forming an interlayer insulating film, a step of forming a mask, and wet the interlayer insulating film An etching step, a step of dry etching the interlayer insulating film, a step of forming a first electrode, and a step of forming a second electrode.

  In the step of forming the polysilicon, the first semiconductor layer extends from the first surface of the first semiconductor layer opposite to the semiconductor layer into the first semiconductor layer and is parallel to the first surface. A trench extending in the first direction is formed in advance. A gate insulating film is formed in advance to cover the bottom and side walls of the trench. An insulating film connected to the gate insulating film at the upper end of the sidewall of the trench and covering the first surface of the first semiconductor layer is formed in advance. The polysilicon is formed on the first surface of the first semiconductor layer through the insulating film so as to fill the trench through the gate insulating film.

  In the step of etching the polysilicon, the gate electrode made of the polysilicon is arranged such that an upper surface thereof is located inside the trench with respect to the first surface of the first semiconductor layer. An insulating film is formed in the trench along the first direction. At the same time, a gate wiring layer made of polysilicon is formed on the first surface of the first semiconductor layer via the insulating film, and the gate wiring layer has a first portion. In the first direction, one end of the gate electrode and one end of the first portion of the gate wiring layer are connected in a direction perpendicular to the first surface. The first portion of the gate wiring layer is formed by extending in a second direction orthogonal to the first direction.

  In the step of forming the interlayer insulating film, the interlayer insulating film is formed to cover the upper surface of the gate electrode, the first surface of the first semiconductor layer, and the gate wiring layer. Is done.

  In the step of forming the mask, the mask is formed directly above the gate wiring layer via the interlayer insulating film and has a first portion. The first portion of the mask covers the first portion of the gate wiring layer in the first direction so as not to be exposed in a plan view, and extends along the first portion of the gate wiring layer. And extending in the second direction.

  In the step of wet etching the interlayer insulating film, a region of the interlayer insulating film that is not covered with the mask is etched by wet etching to form a recess on the surface of the interlayer insulating film on the gate electrode. Is done. The recess has a first side wall extending in the second direction along the first portion of the gate wiring layer and intersecting the gate electrode. The interlayer insulating film is etched so that the first surface of the first semiconductor layer is not exposed to the bottom surface of the recess.

  In the step of dry etching the interlayer insulating film, the entire surface of the interlayer insulating film having the recess is etched by dry etching after the mask is removed. A portion of the first surface of the semiconductor substrate adjacent to the trench in the second direction and an upper end of a sidewall of the trench are exposed at the bottom surface of the recess.

  In the step of forming the first electrode, the first electrode is electrically connected to the semiconductor layer on the surface of the semiconductor layer opposite to the first surface.

  In the step of forming the second electrode, a current controlled by the gate electrode flows between the first electrode and the gate electrode, insulated by the gate electrode and the interlayer insulating film. The second electrode is formed.

1 is a plan view of a semiconductor device according to a first embodiment. 1A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. 1 of the semiconductor device according to the first embodiment. 2A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. 2A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. 2A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. 2A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. 2A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. 2A is a cross-sectional view taken along line AA of the plan view of FIG. 1 and FIG. 1B is a cross-sectional view taken along line BB of the plan view of FIG. (A) A cross-sectional view at a position corresponding to the AA line in the plan view of FIG. 1 in a part of the manufacturing process of the semiconductor device according to the comparative example, and (b) a BB line in the plan view of FIG. Sectional drawing in the position equivalent to. (A) A cross-sectional view at a position corresponding to the AA line in the plan view of FIG. 1 in a part of the manufacturing process of the semiconductor device according to the comparative example, and (b) a BB line in the plan view of FIG. Sectional drawing in the position equivalent to. (A) A cross-sectional view at a position corresponding to the AA line in the plan view of FIG. 1 in a part of the manufacturing process of the semiconductor device according to the comparative example, and (b) a BB line in the plan view of FIG. Sectional drawing in the position equivalent to. In the semiconductor device according to the comparative example, (a) a cross-sectional view at a position corresponding to the line AA in the plan view of FIG. 1, (b) at a position corresponding to the line BB in the plan view of FIG. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description of the embodiment are schematic for ease of description, and the shape, size, size relationship, etc. of each element in the drawing are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained.

(First embodiment)
A first embodiment will be described with reference to FIGS. FIG. 1 is a plan view of a chip of a semiconductor device according to the first embodiment of the present invention. 2A and 2B are a cross-sectional view taken along the line AA in the plan view of FIG. 1 and a plan view taken along the line BB. 3 to 8 are diagrams showing a part of the manufacturing process for explaining the method of manufacturing the semiconductor device shown in FIGS. In each figure, (a) is a cross-sectional view taken along line AA of the plan view of FIG. 1, and (b) is a cross-sectional view taken along line BB of the plan view of FIG. The semiconductor device according to the embodiment is an n-channel MOSFET using silicon as a semiconductor material as an example, but can be applied to other semiconductor devices such as a p-channel MOSFET and an IGBT.

The semiconductor device 100 according to the first embodiment is configured as follows, as shown in FIGS. 1 and 2. Made of silicon the n ^- type drift layer 2 (first semiconductor layer) is formed over the n ⁺ -type drain layer 1 made of silicon (semiconductor layer), a first on a side opposite to the n ⁺ -type drain layer 1 Surface 5. The X-direction (second direction) extending in the Y direction (first direction) in the drawing parallel to the first surface 5 of the n ⁻ -type drift layer 2 and perpendicular to the Y direction and parallel to the first surface 5 ) Are formed. These trenches 4, n ^- toward the n ⁺ -type drain layer 1 side n from the first surface 5 forms the drift layer 2 ^- extends in the interior of the shape drift layer 2.

A gate insulating film 6 is formed on the bottom and side walls of the trench. As the gate insulating film, a thermal oxide film is used as an example, but a silicon oxide film by CVD, a nitride film such as SiN or SiNO, or another dielectric film such as Al ₂ O ₃ can also be used. A gate electrode 8 made of polysilicon is embedded in the trench 4 via a gate insulating film 6. The gate electrode 8 extends in a stripe shape along the Y direction. The upper surface of the gate electrode 8 is formed so as to be located below the first surface 5 of the n ⁻ -type drift layer 2 (on the n ⁺ -type drain layer 1 side). An insulating film 7 is connected to the gate insulating film 6 at the upper ends of the side walls at both ends of the trench 4 in the Y direction, and is formed on the first surface 5 of the n ⁻ -type drift layer 2. The insulating film 7 can be made of the same material as the gate insulating film 6, but it is also possible to provide another insulator or dielectric film below it.

A gate wiring layer 9 made of the same polysilicon as the gate electrode is formed on the first surface 5 of the n ⁻ -type drift layer 2 via the insulating film 7 and insulated from the n ⁻ -type drift layer 2. The gate wiring layer 9 has a first portion 9a and a second portion 9b. One end of the first portion 9a of the gate wiring layer 9 overlaps one end of the gate electrode 8 in the Y direction, and the overlapped portion is joined to one end of the gate electrode 8 by the connecting portion 10 made of polysilicon. That is, one end of the first portion 9a of the gate wiring layer 9 is connected to one end of the gate electrode 8 in the Y direction in a direction perpendicular to the first surface 5 of the n ⁻ -type drift layer 2 (Z direction in the figure). The Further, the first portion 9a of the gate wiring layer 9 extends in the X direction orthogonal to the Y direction. The second portion 9 b of the gate wiring layer 9 extends in the Y direction perpendicular to the first portion 9 a of the gate wiring layer 9. The first portion and the second portion of the gate wiring layer are formed so as to surround the gate electrode 8 formed in the plurality of trenches 4. A region where the gate electrode 8 is formed in the plan view is referred to as an element region. In the element region, a source layer is formed as will be described later, and current flows from the drain electrode 23 to the source electrode 22 via the n ⁺ -type drain layer 1, the n ⁻ -type drift layer 2, the channel layer, and the source layer 15. .

A termination region is formed so as to surround the outside of the element region. Since no source layer is formed in the termination region, no current flows from the drain electrode 23 toward the source electrode 22. The first portion 9 a and the second portion 9 b of the gate wiring layer 9 are formed on the first surface 5 of the n ⁻ -type drift layer 2 in the termination region via the insulating film 7.

An interlayer insulating film 11 is formed so as to cover the upper surface of the gate electrode 8 and the upper surface of the first portion 9 a and the upper surface of the second portion 9 b of the gate wiring layer 9. The gate electrode 8 is insulated from the outside by the gate insulating film 6 and the interlayer insulating film 11, and the gate wiring layer 9 is insulated from the outside by the insulating film 7 and the interlayer insulating film 11. The portion of the first surface 5 of the n ⁻ -type drift layer 2 between the adjacent trenches 4, the upper end of the sidewall of the trench 4, and the gate wiring layer of the first surface 5 of the n ⁻ -type drift layer 2 The portion between the second portion 9b 9 and the outermost gate electrode 8 is exposed without an interlayer insulating film formed thereon. That is, the recess 13 is formed on the surface of the interlayer insulating film 11 in the region surrounded by the first portion 9a and the second portion 9b of the gate wiring layer 9. The recess 13 includes a first side wall 13a extending in the X direction along the first portion 9a of the gate wiring layer 9, and a second side wall 13b extending along the second portion 9b of the gate wiring layer 9. Have The recess 13 formed in the interlayer insulating film 11 passes through the insulating film 7 formed under the interlayer insulating film 11, and the adjacent trench 4 in the first surface 5 of the n ⁻ -type drift layer 2. A portion between the second portion 9b of the gate wiring layer 9 and the outermost gate electrode 8 in the first surface 5 of the n ⁻ -type drift layer 2. Is exposed at the bottom of the recess 13. The first side wall 13 a and the second side wall 13 b of the recess 13 are constituted by the interlayer insulating film 11 and the insulating film 7. The first side wall 13a and the second side wall 13b is, n ^- is not formed perpendicular to the first surface 5 forms the drift layer 2, n ^- increases toward the form drift layer 2 side, the gate wiring layer 9 is formed so as to be away from the first portion 9a or the second portion 9b. In the present embodiment, the first side wall 13a and the second side wall 13b have a shape recessed toward the n ⁻ -type drift layer 2 side, but a tapered shape or the like is also possible. The interlayer insulating film 11 may be made of the same material as the gate insulating film 6 and the insulating film 7, and is a thermal oxide film, a silicon oxide film by CVD, a nitride film such as SiN or SiNO, and a dielectric such as Al ₂ O _3. A body membrane can be used.

A p-type base layer 14 a is formed on the surface of the n ⁺ -type drain layer 1 between the adjacent trenches 4. The bottom of the p-type base layer 14 a is closer to the first surface of the first semiconductor layer than the bottom of the trench 4 and is shallower than the bottom of the trench 4. A p-type base layer termination 14 b is formed between the second portion 9 b of the gate wiring layer 9 and the outermost trench 4, and is adjacent to the gate insulating film 6 of the outermost trench 4. The p-type base layer termination portion 14b is a layer formed integrally with the p-type base layer 14a formed between the adjacent trenches 4, and is formed to the same depth with the same impurity concentration. A p-type guard ring layer is formed on the surface of the n ⁻ -type drift layer 2 immediately below the first portion 9a and the second portion 9b of the gate wiring layer 9, and is more p-type impurity than the p-type base layer termination portion 14b. The concentration is low, the bottom is deep, and it is connected to the p-type base layer termination 14b.

An n ^{+ -type} source layer 15 is formed on the first surface 5 of the n ⁻ -type drift layer 2 between the adjacent trenches 4 and selectively formed on the surface of the p-type base layer 14 a. The n ^{+ type} source layer 15 has an n type impurity concentration higher than that of the n ^{− type} drift layer 2. An n ^{+ -type} channel stopper layer 16 is formed at a chip end portion (diced portion) of the MOSFET 100 at a portion where the interlayer insulating film 11 and the insulating film 7 on the first surface 5 of the n ⁻ -type drift layer 2 are removed. Is done. The n ^{+ -type} channel stopper layer 16 has the same n-type impurity concentration and the same depth as the n ^{+ -type} source layer 15.

A p ^{+ -type} carrier discharge layer 18 is formed on the surface of the p-type base layer termination 14 b between the second side wall 13 b of the recess 13 formed in the interlayer insulating film 11 and the outermost trench 4. The impurity concentration is higher than that of the p-type base layer termination portion 14b, and the bottom thereof is located deeper than the bottom of the n ^{+ -type} source layer 15 and located on the n ⁺ -type drain layer 1 side. A p ^{+ -type} contact layer (not shown) is formed on the first surface 5 of the n ⁻ -type drift layer 2 between the adjacent trenches 4 so as to be electrically connected to the p-type base layer 14a. The n ^{+ -type} source layers 15 are alternately arranged along the Y direction on the surface of 14a. position of the bottom of the p-type impurity concentration and the p ⁺ -type contact layer of p ⁺ -type contact layer is the same as the position of the bottom of the p-type impurity concentration and the p ⁺ -type carrier discharging layer 18 of p ⁺ -type carrier discharging layer 18 . The arrangement of the n ^{+ -type} source layer 15 and the p ^{+ -type} contact layer along the Y direction on the surface of the p-type base layer 14a is an example when the gate electrode is formed in a stripe shape. When the electrode is formed in a mesh shape, an offset mesh shape, or a honeycomb shape, the n ^{+ -type} source layer 15 and the p ^{+ -type} contact layer may be arranged corresponding to each existing one.

The interlayer insulating film 11 is formed with a first opening 20a and a second opening 20b that respectively reach the first portion 9a and the second portion 9b of the gate wiring layer 9 from the surface thereof. A gate metal wiring 21 electrically connected to the gate wiring layer 9 is formed through the first opening 20a and the second opening 20b. As shown in FIG. 1, the gate metal wiring is electrically connected to an external gate terminal (not shown) by wire bonding or the like from the gate pad formed at the chip corner portion. Thereby, the gate electrode 8 is electrically connected to the external gate terminal via the gate wiring layer 9 and the gate metal wiring 21. In the internal element region surrounded by the gate wiring layer 9, the source electrode 22 is formed on the gate electrode 8 via the interlayer insulating film 11, on the n ^{+ -type} source layer 15, and on the p ^{+ -type} contact layer. And the p ^{+ -type} carrier discharge layer 18 and is electrically connected to the n ^{+ -type} source layer 15, the p ^{+ -type} contact layer and the p ^{+ -type} carrier discharge layer 18. The source electrode 22 is electrically connected to a source terminal (not shown) by wire bonding or the like. The drain electrode 23 is formed so as to be electrically connected to the surface of the n ⁺ -type drain layer 1 opposite to the n ⁻ -type drift layer 2. Similarly to the other electrodes, the drain electrode 23 is also electrically connected to a drain terminal (not shown).

Next, the operation and characteristics of the MOSFET 100 according to this embodiment will be described below. When a positive voltage exceeding the threshold is applied to the gate electrode 8 in a state where a positive voltage is applied to the drain electrode 23 with respect to the source electrode 23, the channel layer of electrons generated by the inversion distribution becomes the p-type base layer 14a. Is formed in a region adjacent to the gate insulating film 6. As a result, the electron source electrode 22, ^{n +} -type source layer 15, the channel layer, n ^- form drift layer, and via the ^{n +} -type drain layer flows to the drain electrode 23, MOSFET 100 is turned on.

Here, the upper surface of the interlayer insulating film 11 formed on the upper surface of the gate electrode 8 is directed toward the inside of the trench 4 from the first surface 5 of the n ⁻ -type drift layer 2 (to the n ⁺ -type drain layer side). ), The n ^{+ -type} source layer 15 is not only electrically connected to the source electrode 22 through the first surface 5 of the n ⁻ -type drift layer 2, but also the upper end of the sidewall of the trench 4. It is electrically connected to the source electrode 22 through the electrode. For this reason, since the contact resistance between the n ^{+ -type} source layer 15 and the source electrode 22 is lowered, the on-resistance of the MOSFET 100 is lowered. The thinner the interlayer insulating film 11 formed on the upper surface of the gate electrode 8, the larger the contact area between the n ^{+ -type} source layer 15 and the source electrode 22 at the upper end of the trench 4. Further reduction can be achieved.

Further, as will be described later with reference to the manufacturing method, the first side wall 13a and the second side wall 13b of the recess 13 formed in the interlayer insulating film 11 have the first side wall of the n ^{− type} drift layer 2 as described above. Since the surface is not perpendicular to the surface, the curvature of the end of the gate wiring layer 9 on the second portion 9b side of the p ^{+ -type} carrier discharge layer 18 formed below the surface is relaxed compared to the case of being perpendicular. The As a result, MOSFET 100 is n in the off state ^- distance equipotential lines of the depletion layer spread from the shape drift layer 2 to the p-type base layer terminating unit 14b is, the gate wiring layer 9 of ^{p +} -type carrier discharging layer 18 Since it spreads at the end on the second portion 9b side, the electric field concentration is alleviated and the breakdown voltage of the MOSFET 100 is improved.

Next, a method for manufacturing the MOSFET 100 according to the present embodiment will be described with reference to FIGS. 3 to 8 are cross-sectional views that are the same as the cross-section in FIG. 2, showing a part of the manufacturing process of the MOSFET 100 according to this embodiment. As shown in FIG. 3, an n ^{− type} drift layer 2 is formed on the n ^{+ type} drain layer 1. This is because the epitaxially grown on the n ⁺ -type silicon substrate n ^- well that can be obtained by forming the shape epitaxial layer, n ^- a n-type impurity on the back of the form board by diffusion by ion implantation to a heat treatment It can also be obtained by forming an n ⁺ -type epitaxial layer, and can be formed by a normal MOSFET manufacturing process.

The p-type guard ring layer 3 is formed on the first surface 5 of the n ⁻ -type drift layer 2 at a position where the first portion 9a and the second portion 9b of the gate wiring layer 9 are to be formed. . For example, the p-type guard ring layer 3 can be formed by ion implantation of p-type impurities and diffusion by heat treatment. A plurality of trenches 4, by RIE (Reactive Ion Etching) as an example, n ^- on the first surface of the form the drift layer 2, is formed in a region surrounded by the above p-type guard ring layer 3, n ^- form The film extends from the first surface 5 of the drift layer 2 toward the inside of the n ⁻ -type drift layer 2 and extends in a stripe shape in the Y direction. Both ends in the Y direction of the trench 4 are respectively formed inside the opposing portions of the p-type guard ring layer 3. A gate insulating film 6 is formed so as to cover the bottom and side walls of the trench 4. The gate insulating film 6 can be formed of a silicon oxide film by thermal oxidation or CVD, but may be SiN, SiNO, or other dielectric film such as Al ₂ O ₃ . An insulating film 7 is formed in the same manner as the gate insulating film so as to cover the first surface 5 of the n ⁻ -type drift layer 2 and is connected to the gate insulating film 6 at the upper end of the sidewall of the trench 4. The The insulating film 7 may be formed integrally with the gate insulating film 6 or may be formed on another insulating film previously formed on the first surface 5 of the n ⁻ -type drift layer 2. It is. Polysilicon is formed on the entire surface of the first surface 5 of the n ⁻ -type drift layer 2 via the insulating film 7 so as to be buried in the trench 4 via the gate insulating film 6.

Next, the polysilicon is etched using a resist mask (not shown) having a desired pattern formed by using an existing silicon process lithography technique, whereby the gate electrode 8 and the gate wiring layer made of this polysilicon are etched. 9 are formed. The gate electrode 8 is embedded in the trench 4 via the gate insulating film 6 and extends in the Y direction. The upper surface of the gate electrode 8 recedes into the trench 4 from the first surface 5 of the n ⁻ -type drift layer 2. It is formed. The gate wiring layer 9 is formed on the first surface of the n ^{− type} drift layer 2 via the insulating film 7 and has a first portion 9 a and a second portion 9 b. One end of the first portion 9a of the gate wiring layer 9 overlaps with one end of the gate electrode 8 in the Y direction, and the overlapped portion is joined to one end of the gate electrode 8 by the connecting portion 10 made of polysilicon. That is, one end of the first portion 9a of the gate wiring layer 9 is connected to one end of the gate electrode 8 in the Y direction in a direction perpendicular to the first surface 5 of the n ⁻ -type drift layer 2 (Z direction in the figure). The Further, the first portion 9a of the gate wiring layer 9 extends in the X direction orthogonal to the Y direction. The second portion 9 b of the gate wiring layer 9 extends in the Y direction perpendicular to the first portion 9 a of the gate wiring layer 9. The first portion 9 a and the second portion 9 b of the gate wiring layer 9 are formed so as to surround the gate electrode 8 formed in the plurality of trenches 4. The outermost gate electrode 8 is formed in a region surrounded by the first portion 9 a and the second portion 9 b of the gate wiring layer 9. The first portion 9 a and the second portion 9 b of the gate wiring layer 9 are respectively formed immediately above the p-type guard ring layer 3 formed on the first surface 5 of the n ⁻ -type drift layer 2.

Next, as shown in FIG. 4, the interlayer insulating film 11 is formed on the entire upper surface of the gate electrode 8 in the trench 4 and on the first surface 5 of the n ⁻ -type drift layer 2. The interlayer insulating film 11 may be made of the same material as the gate insulating film 6 and the insulating film 7, and is a thermal oxide film, a silicon oxide film by CVD, a nitride film such as SiN or SiNO, and a dielectric film such as Al ₂ O _3. Can be used.

  Next, a resist mask 12 is formed on the interlayer insulating film 11 so as to cover the gate wiring layer 9 by using an existing silicon process lithography technique. The resist mask 12 has a first portion 12a and a second portion 12b. The first portion 12a of the resist mask 12 covers the first portion 9a of the gate wiring layer 9 in the Y direction so as not to be exposed in a plan view (when viewed from the Z direction). It extends in the X direction along the portion 9a. The second portion 12b of the resist mask 12 covers the second portion 9b of the gate wiring layer 9 in the X direction so as not to be exposed in a plan view, and the Y portion along the second portion 9b of the gate wiring layer 9 And is orthogonal to the first portion 12a of the resist mask 12. Similar to the gate wiring layer, the resist mask 12 has an annular structure surrounding the element region in the termination region of the MOSFET 100.

Next, as shown in FIG. 5, a portion of the surface of the interlayer insulating film 11 exposed from the resist mask 12 is etched by wet etching, and a recess 13 is formed along the resist mask 12 inside. . The recess 13 has a first side wall 13a and a second side wall 13b, and the wet etching is stopped in a state where the first surface 5 of the n ⁻ -type drift layer 2 is not exposed at the bottom. As an etchant for wet etching, one used in an existing silicon process can be used. The first side wall 13 a of the recess 13 extends in the X direction along the first portion 9 a of the gate wiring layer 9, intersects the gate electrode 8, and is on the first surface 5 of the n ⁻ -type drift layer 2. It is not formed vertically. Since the interlayer insulating film 11 is isotropically etched at the end of the first portion 12a of the resist mask 12 by wet etching, the first side wall 13a of the recess 13 faces the n ⁻ -type drift layer 2 side. The gate wiring layer 9 is formed so as to move away from the first portion 9a. In other words, the first side wall 13a of the recess 13 is formed to be recessed toward the n ⁻ -type drift layer 2 side.
Note that the first side wall 13a of the recess 13 can be tapered by changing the etching conditions. The second side wall 13b of the recess 13 extends in the Y direction along the second portion 9b of the gate wiring layer 9, is parallel to the gate electrode 8, and is the outermost side with the second portion 9b of the gate wiring layer 9. Between the gate electrode 8 and the gate electrode 8. Similarly to the first side wall 13a, the second side wall 13b of the recess 13 is not formed perpendicular to the first surface 5 of the n ⁻ -type drift layer 2. Since the interlayer insulating film 11 is isotropically etched at the end of the second portion 12b of the resist mask 12 by wet etching, the second side wall 13b of the recess 13 is similarly formed on the n ⁻ -type drift layer 2 side. It is formed so as to move away from the second portion 9b of the gate wiring layer 9 as it goes. In other words, the second side wall 13b of the recess 13 is also formed to be recessed toward the n ⁻ -type drift layer 2 side. By performing wet etching on the interlayer insulating film 11 as described above, the recess 13 having the first side wall 13a facing each other and the second side wall 13b facing perpendicularly to the first side wall 13a is formed on the gate wiring layer 9. It is formed on the surface of the interlayer insulating film 11 in a region surrounded by the first portion 9a and the second portion 9b.

Next, as shown in FIG. 6, after removing the resist mask 12, the entire surface of the interlayer insulating film 11 is etched by dry etching. As an example, dry etching can be performed by RIE, but CDE (Chemical Dry Etching) or the like can also be performed. Any etching method other than dry etching may be used as long as the surface of the interlayer insulating film 11 can be etched uniformly and with good control. By uniformly etching the entire surface of the interlayer insulating film 11 by RIE, the recess 13 formed on the surface of the interlayer insulating film 11 by the above-described wet etching is etched while maintaining the shape of the recess 13. To go. Of the first surface 5 of the n ⁻ -type drift layer 2, the portion between the adjacent trenches 4 (the portion adjacent to the trenches in the X direction) and the second side wall 13 b of the recess 13 and the gate electrode 8 are the most. Dry etching is finished when the portion between the outer gate electrode 8 and the upper end portion of the sidewall of the trench 4 of the n ⁻ -type drift layer 2 are exposed at the bottom surface of the recess 13. As a result, a portion of the interlayer insulating film 11 formed on the upper surface of the gate electrode 8 in the trench 4 is located closer to the n ⁺ -type drain layer 1 side than the first surface 5 of the n ⁻ -type drift layer 2. To be formed. The first side wall 13a and the second side wall 13b of the recess 13 maintain the shape formed by the wet etching, and the first portion 9a of the gate wiring layer 9 becomes closer to the n ⁻ -type drift layer 2 side. And the second portion 9b. In other words, the first side wall 13a and the second side wall 13b of the recess 13 have a shape recessed toward the n ⁻ -type drift layer 2 side. By this dry etching, the opening 24 of the interlayer insulating film 11 is formed by etching at the same time in a portion that becomes a dicing line from which the chip of the MOSFET 100 is separated, but it may be etched in another process for convenience of the process. Is possible.

Next, as shown in FIG. 7, the p-type base layer 14 a is formed in a portion sandwiched between adjacent trenches on the first surface 5 of the n ⁻ -type drift layer 2, and gate insulation is performed on the sidewall of the trench 4. It is formed adjacent to the film 6. The p-type impurity concentration of the p-type base layer 14a is set higher than that of the p-type guard ring layer. The bottom of the p-type base layer 14 a is shallower than the bottom of the gate electrode 8 in the trench 4 and is formed on the first surface 5 side of the n ⁻ -type drift layer 2. The p-type base layer termination portion 14b is formed between the p-type guard ring layer 3 and the outermost gate electrode 8 in the first surface 5 of the n ⁻ -type drift layer 2 simultaneously with the p-type base layer 14a. One end is adjacent to the gate insulating film 6 and the other end on the opposite side is connected to the p-type guard ring layer 3. The p-type base layer 14a and the p-type base termination portion 14b are formed by using the interlayer insulating film 11 and the gate electrode 8 formed on the gate wiring layer 9 as a mask and using the p-type impurity as the first of the n ⁻ -type drift layer 2. It can be formed integrally by injecting into the surface 5 of. As an example, the impurity can be implanted by thermal diffusion after ion implantation. At this time, if necessary, the opening 24 of the interlayer insulating film 11 to be a dicing line of the MOSFET 100 may be covered with a mask (not shown). In the method for manufacturing the MOSFET 100 of this embodiment, as described above, the p-type base layer 14a and the p-type base layer termination 14b are formed after the trench 4 is formed on the first surface 5 of the n ⁻ -type drift layer 2. Although formed, this is merely an example. p-type base layer 14a and the p-type base layer terminating unit 14b, like the p-type guard ring layer 3, n ^- before the trench 4 is formed on the first surface 5 forms the drift layer 2, n ^- form It may be formed in advance at a predetermined position on the first surface 5 of the drift layer 2. Thereafter, the trenches 4, n ^- through the p-type base layer 14a and the p-type base layer 14b from the first surface 5 forms the drift layer 2 (a portion p-type base layer 14a is formed) n ^- form It can be formed so as to reach the inside of the drift layer 2.

Next, the n ^{+ -type} source layer 15 is formed on the surface of the p-type base layer 14 a formed on the first surface 5 of the n ⁻ -type drift layer 2 between the adjacent trenches 4, and the n ^{+ -type} source layer is formed. The n-type impurity concentration of 15 is higher than the n-type impurity concentration of the n ⁻ -type drift layer 2. The n ^{+ -type} source layer 15 is formed so as to face the upper end of the gate electrode 8 through the gate insulating film 6 at the lower end portion. The n ^{+ -type} source layer 15 uses the interlayer insulating film 11 formed on the gate electrode 8 and the gate wiring layer 9 as a mask, and converts n-type impurities into the first surface 5 (that is, adjacent to the n ⁻ -type drift layer 2). By injecting into the surface of the p-type base layer 14a formed between the trenches, the surface of the p-type base layer 14a is formed. The n-type impurity implantation can be performed by ion implantation and subsequent thermal diffusion as an example, similarly to the p-type base layer 14a. At the same time, the n ^{+ -type} channel stopper layer 16 is formed on the first surface 5 of the n ⁻ -type drift layer 2 in the portion serving as the dicing line of the chip of the MOSFET 100 through the opening 24 of the interlayer insulating film 11. The In FIG. 7, on the surface of the p-type base layer terminating unit 14b not n ⁺ -type source layer is formed, at the time of implantation of the n-type impurity, the n ⁺ -type source layer is formed on the surface It may be. This is because when the p ^{+ -type} carrier discharge layer described later is formed, the surface of the p-type base layer termination portion 14b is compensated by the p-type impurity and becomes p-type.

Next, as shown in FIG. 8, in order to protect the n ^{+ -type} source layer 15 sandwiched between adjacent trenches 4 from the implantation of p-type impurities described later, a resist mask 17 is formed on the n ^{+ -type} source layer 15. Formed. In order to protect the n ^{+ -type} channel stopper layer 16 as necessary, it is covered with a resist mask 17. The resist mask 17 has a plurality of openings not shown along the Y direction. The openings may be, for example, striped openings that extend in the X direction and are spaced apart in the Y direction. A p-type impurity is formed on the first surface 5 of the n ⁻ -type drift layer 2 using the resist mask 17, the gate electrode 8, and the interlayer insulating film 11 formed on the gate wiring layer 9 as a mask. Implanted into the respective surfaces of the p-type base layer 14a and the p-type base layer termination 14b. As a result, a p ^{+ -type} contact layer (not shown) is selectively formed on a portion of the surface of the p-type base layer 14a between the adjacent trenches 4 corresponding to the opening of the resist mask 17 described above. It is electrically connected to the base layer 14a and is alternately arranged with the n ^{+ -type} source layers 15 along the Y direction. p ⁺ even in the form originally n ⁺ -type source layer 15 in the portion where the contact layer is formed has been formed, impurity is compensated p ⁺ -type contact layer can be formed by p-type impurity is sufficiently injected It is. At the same time that the p ^{+ -type} contact is selectively formed on the p-type base layer 14a, the p ^{+ -type} carrier discharge layer 18 has the outermost gate electrode on the surface of the p-type base termination 14b. 8 and the second side wall 13 b of the recess 13.
Here, the shape of the second side wall 13b of the recess 13 maintains the shape formed by the above-described wet etching, and is separated from the second portion 9b of the gate wiring layer 9 toward the n ⁻ -type drift layer 2 side. It is formed to go. In other words, the second side wall 13b of the recess 13 has a shape recessed toward the n ⁻ -type drift layer 2 side. For this reason, when the p-type impurity is implanted into the p-type base layer termination portion 14b, the second sidewall 13b of the recess 13 becomes the end of the interlayer insulating film 11 serving as a mask. The amount of p-type impurity implanted onto the surface of the p-type base layer 14b gradually decreases from the side wall 13b toward the second portion 9b of the gate wiring layer 9. As a result, compared with the case where the shape of the second sidewall 13b of the recess 13 is formed perpendicular to the first surface of the n ⁻ -type drift layer 2, the p ^{+ -type} carrier discharge layer 18 has the gate wiring The end of the layer 9 on the second portion 9b side has a gentle curvature.
Although the n ^{+ -type} source layer 15 is not formed on the surface of the p-type base layer termination portion 14b when the n ^{+ -type} source layer 15 in FIG. 7 is formed, the p-type may be formed even if it is formed at the same time. If the impurity is sufficiently implanted, the p ^{+ -type} carrier discharge layer 18 can be formed on the p-type base layer termination portion 14b with the impurity compensated in the same manner as the p ^{+ -type} contact layer. The implantation of the p-type impurity can also be performed by, for example, ion implantation of the p-type impurity and subsequent diffusion by heat treatment.

Next, as shown in FIG. 2, after removing the resist mask 17, the first opening 20 a and the second opening 20 b reaching the first portion 9 a and the second portion 9 b of the gate wiring layer 9. Are formed by existing silicon process technology. These openings 20a and 20b are formed simultaneously when the interlayer insulating film 11 is etched by the above-described dry etching and the first surface 5 of the n ⁻ -type drift layer 2 is exposed at the bottom of the recess 13. It is also possible. The openings 20a and 20b may be formed at an appropriate time according to the convenience of the process. The gate metal wiring 21 is formed so as to be electrically connected to the first portion 9a and the second portion 9b of the gate wiring layer 9 through the first openings 20a and 20b of the interlayer insulating film 11. . A source electrode 22 is formed on the n ^{+ -type} source layer 15, the p ^{+ -type} carrier discharge layer 18, and the gate electrode 8 through the interlayer insulating film 11 in the recess 13, and the n ^{+ -type} source layer 15, The p-type base layer 14 a and the p ^{+ -type} carrier discharge layer 18 are electrically connected.
Here, the gate metal wiring layer 21 and the source electrode 22 can be formed by forming a metal on the entire chip surface of the MOSFET 100 and then patterning the metal by the existing lithography technique and etching technique. The gate metal wiring layer 21 and the source electrode 21 may be an existing metal material used as a semiconductor electrode, such as aluminum, copper, or gold. The drain electrode is formed so as to be electrically connected to the surface of the n ⁺ -type drain layer 1 opposite to the n ⁻ -type drift layer 2. Similarly to the source electrode 22 and the gate electrode 21, the drain electrode 23 may be an existing metal material.

  The MOSFET 100 according to this embodiment can be manufactured by the manufacturing method according to this embodiment described above.

  Next, in order to explain the effect of the method of manufacturing the MOSFET 100 according to this embodiment, a method of manufacturing the MOSFET of the comparative example will be described. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in this embodiment, and description thereof is omitted. Differences from the present embodiment will be mainly described. 9A is a cross-sectional view of a part of the manufacturing process of the MOSFET manufacturing method according to the comparative example, and FIG. 9B is a cross-sectional view taken along the line AA in the plan view of FIG. It is sectional drawing in the position corresponded to the BB line of the top view. The manufacturing process in FIG. 9 corresponds to the manufacturing process in FIGS. 5 and 6 in the MOSFET manufacturing method according to the present embodiment. The manufacturing method of the MOSFET of the comparative example is the manufacturing method of this embodiment up to FIG. 4 of the manufacturing method of this embodiment, that is, until the mask is formed on the interlayer insulating film so as to cover the gate wiring layer 9. The same manufacturing process as the method is provided.

In the MOSFET manufacturing method of the present embodiment, as shown in FIG. 5, a portion of the surface of the interlayer insulating film 11 exposed from the resist mask 12 covering the gate wiring layer 9 is first etched by wet etching. The recess 13 having the first side wall 13a and the second side wall 13b is formed. Thereafter, the resist mask 12 is removed, and the entire surface of the interlayer insulating film 11 having the recess 13 on the surface is etched by dry etching, so that the adjacent trenches in the first surface 5 of the n ⁻ -type drift layer 2 are etched. 4 and a portion between the second sidewall 13b of the recess 13 and the outermost gate electrode 8 of the gate electrode 8, and a portion at the upper end of the sidewall of the trench 4 of the n ^{− type} drift layer 2 Are exposed on the bottom surface of the recess 13 to finish the etching.

  In contrast, in the MOSFET manufacturing method of the comparative example, as shown in FIG. 9, the portion of the surface of the interlayer insulating film 11 exposed from the resist mask 12 covering the gate wiring layer 9 is directly etched by dry etching. As a result, the recess 113 having the first side wall 113a and the second side wall 113b is formed. This is different from the MOSFET manufacturing method of the present embodiment. Subsequent processes include the same manufacturing steps as the manufacturing method of the present embodiment as will be described later.

The first sidewall 113a and the second sidewall 113b of the recess 113 formed on the surface of the interlayer insulating film 11 by the manufacturing method of the comparative example are the first sidewall 13a and the second sidewall of the recess 13 according to this embodiment. Similarly to 13b, the gate wiring layer 9 is formed along the first portion 9a and the second portion 9b, respectively, but the shape is different from the recess 13 according to the present embodiment. Since the first side wall 113a and the second side wall 113b of the comparative example are anisotropic etching by dry etching, the first side wall of the n ^{− type} drift layer 2 is formed from the end of the resist mask 12 as shown in FIG. It is formed substantially perpendicular to the surface 5. Further, at the portion where the bottom surface of the recess 113 of the comparative example intersects with the first side wall 113a and the second side wall 113b, it is not formed at a right angle, and is further n ⁻ than the bottom surface of the recess 113 along each side wall. A convex portion T is formed toward the drift layer 2 side. Hereinafter, the phenomenon in which the convex portion is formed is referred to as trenching. The dry etching is characterized in that the boundary between the resist mask 12 and the interlayer insulating film 11 has a higher etching rate than the etching rate of the surface of the interlayer insulating film 11. Therefore, when dry etching is performed with the resist mask 12 and the interlayer insulating film 11 both exposed on the surface, the etching of the interlayer insulating film 11 is performed along the edge of the resist mask 12 as shown in FIG. And locally fast, so that trenching occurs.

Similar to the MOSFET manufacturing method of the present embodiment, as shown in FIG. 10, when the first surface 5 of the n ⁻ -type drift layer 2 is exposed, dry etching is stopped and the resist mask 12 is removed. As shown in FIG. 10A, since the trenching occurs in the MOSFET manufacturing method of the comparative example, the thickness of the interlayer insulating film 11 on the gate electrode 8 is changed to the MOSFET manufacturing method of this embodiment. It cannot be made thinner than. In the MOSFET manufacturing method of the comparative example, if the thickness of the interlayer insulating film 11 on the gate electrode 8 is too thin, the first sidewall 113a of the recess 113 formed on the surface of the interlayer insulating film 11 and the gate electrode 8 intersect. This is because an opening is formed in the interlayer insulating film 11 by the convex portion T generated by trenching. When the opening of the interlayer insulating film 11 is formed, the source electrode 22 and the gate electrode 8 formed after that cannot be insulated. Therefore, the interlayer insulating film 11 needs to have a thickness sufficient to provide insulation between the sort electrode and the gate electrode at the projecting portion T formed by the trenching.

After that, as shown in FIG. 11, through the same process as the MOSFET manufacturing method according to the present embodiment, the p-type base layer 14a, the p-type base layer termination 14b, the n ^{+ -type} source layer 15, the channel stopper layer 16, a p ^{+ -type} contact layer and a p ^{+ -type} carrier discharge layer 118 are formed. Here, the p ^{+ -type} carrier discharge layer 118 is formed on the outermost side with the second side wall 113b of the recess 113 formed on the surface of the interlayer insulating film 11 in the same process as the MOSFET manufacturing method according to the present embodiment. Using the formed gate electrode 8 as a mask, p-type impurities are implanted into the surface of the p-type base layer termination 14b. However, in the MOSFET manufacturing method of the comparative example, since the surface of the interlayer insulating film 11 exposed from the resist mask 12 is etched by dry etching without first performing wet etching as described above, the interlayer insulating film 11, the first side wall 113 a and the second side wall 113 b of the recess 113 formed substantially perpendicular to the first surface 5 of the n ⁻ -type drift layer 2. This is different from the MOSFET manufacturing method according to FIG. For this reason, when the p-type impurity is implanted, the second side wall 113b of the recess 113 becomes the end of the interlayer insulating film 11 serving as a mask, and therefore, p implanted into the surface of the p-type base layer termination 14b. Since the amount of the type impurity decreases rapidly from the second side wall 113b of the recess 113 toward the second portion 9b of the gate wiring layer 9, the end of the p ^{+ type} carrier discharge layer 118 on the gate wiring layer 9b side is The p ^{+ -type} carrier discharge layer 18 of the MOSFET 100 according to this embodiment has a larger curvature than the end of the gate wiring layer 9b side. Thereafter, as shown in FIG. 12, the gate metal wiring 21, the source electrode 22, and the drain electrode 23 are formed through the same process as the MOSFET manufacturing method according to the present embodiment.

As described above, the MOSFET 101 manufactured by the MOSFET manufacturing method of the comparative example has an interlayer insulating film 11 formed on the gate electrode 8 embedded in the trench 4 rather than the MOSFET 100 manufactured by the manufacturing method of the present embodiment. Therefore, it is difficult to form the upper surface of the interlayer insulating film 11 closer to the n ⁺ -type drain layer than the first surface 5 of the n ⁻ -type drift layer 2. Further, the end of the p ^{+ -type} carrier discharge layer 118 of the MOSFET 101 manufactured by the MOSFET manufacturing method of the comparative example on the gate wiring layer 9b side is the gate wiring of the p ^{+ -type} carrier discharge layer 18 of the MOSFET 100 according to the present embodiment. It has a larger curvature than the end on the layer 9b side. As shown in FIG. 9, these features are obtained by directly etching the surface of the interlayer insulating film 11 to be an element region exposed by the resist mask 8 by dry etching without first performing wet etching. This is because the recess 113 is formed on the surface of the interlayer insulating film 11.

On the other hand, in the method for manufacturing the MOSFET 100 according to the present embodiment, the portion exposed from the resist mask 12 covering the gate wiring layer 9 in the surface of the interlayer insulating film 11 is first etched by wet etching, thereby A recess 13 having a first side wall 13a and a second side wall 13b is formed. Thereafter, the resist mask 12 is removed, and the entire surface of the interlayer insulating film 11 having the recess 13 on the surface is etched by dry etching, so that the adjacent trenches 4 in the first surface 5 of the n ⁻ -type drift layer 2 are etched. And a portion between the second sidewall 13b of the recess 13 and the outermost gate electrode 8 of the gate electrode 8, and a portion of the n ^{− type} drift layer 2 at the upper end of the sidewall of the trench 4 Are exposed on the bottom surface of the recess 13.

By including such steps, in the method for manufacturing MOSFET 100 according to the present embodiment, the bottom surface of the recess 13 formed on the surface of the interlayer insulating film 11 intersects the first side wall 13a and the second side wall 13b. Unlike the method of manufacturing the MOSFET 101 of the comparative example, no trenching occurs in the portion. Therefore, the thickness of the interlayer insulating film 8 formed on the upper surface of the gate electrode 8 embedded in the trench 4 can be reduced, and the n ^{+ -type} source layer 15 exposed at the upper end of the side wall of the trench 4. Therefore, the MOSFET 100 manufactured by the manufacturing method according to this embodiment has a contact resistance between the n ^{+ -type} source layer 15 and the source electrode as compared with the MOSFET 101 manufactured by the manufacturing method of the comparative example. Lowers the on-resistance.

In addition, the second portion 9b of the gate wiring layer 9 is formed such that the shape of the first sidewall 13a and the second sidewall 13b of the recess 13 formed on the surface of the interlayer insulating film 11 is closer to the n ⁻ -type drift layer 2 side. It is formed to go away from. In other words, the second side wall 13b of the recess 13 has a shape recessed toward the n ⁻ -type drift layer 2 side. When the p-type impurity is implanted into the p-type base layer termination portion 14b, the second side wall 13b of the recess 13 becomes the end of the interlayer insulating film 11 serving as a mask, so that the second side wall 13b of the recess 13 The amount of p-type impurity implanted onto the surface of the p-type base layer 14b gradually decreases toward the second portion 9b of the gate wiring layer 9. Therefore, compared to the case where the shape of the second sidewall 13b of the recess 13 is formed perpendicular to the first surface of the n ⁻ -type drift layer 2, the p ^{+ -type} carrier discharge layer 18 has a gate wiring The end of the layer 9 on the second portion 9b side has a gentle curvature. As a result, the MOSFET 100 manufactured by the manufacturing method according to the present embodiment is more concentrated in the electric field at the end of the p ^{+ -type} carrier discharge layer 18 on the gate wiring layer 9b side than the MOSFET 101 manufactured by the manufacturing method of the comparative example. Is relaxed, and the breakdown voltage at the terminal end is improved.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 n ^{+ type} drain layer 2 n ^{− type} drift layer 3 p type guard ring layer 4 trench 5 first surface 6 gate insulating film 7 insulating film 8 gate electrode 9a First portion of gate wiring layer, 9b of gate wiring layer Second portion 10 Connection portion 11 Interlayer insulating film 12a First portion of resist mask, 12b Second portion of resist mask 13 Recess, 13a First sidewall of recess, 13b Second sidewall 14a of recess p-type base Layer, 14b p-type base layer termination 15 n ^{+ -type} source layer 16 channel stopper layer 17 resist mask 18 p ^{+ -type} carrier discharge layer 20a, 20b, 24 opening 21 gate metal wiring 22 source electrode 23 drain electrode 100 MOSFET
Projection by T-trenching

Claims (15)

A first conductivity type first semiconductor layer having an impurity concentration of the first conductivity type lower than that of the semiconductor layer formed on the first conductivity type semiconductor layer is opposite to the first semiconductor layer. A trench that extends from the surface into the first semiconductor layer and extends in a first direction parallel to the first surface is formed in advance, and covers a bottom surface and a sidewall of the trench. Is formed in advance, and an insulating film that is connected to the gate insulating film at the upper end of the sidewall of the trench and covers the first surface of the first semiconductor layer is formed in advance, and the gate insulating film is interposed therebetween. Forming polysilicon on the first surface of the first semiconductor layer through the insulating film so as to fill the trench.
The gate electrode made of polysilicon is arranged in the first direction through the gate insulating film so that the upper surface thereof is located inside the trench with respect to the first surface of the first semiconductor layer. And a gate wiring layer made of polysilicon is formed on the first surface of the first semiconductor layer via the insulating film, and the gate wiring layer is formed in the trench. Has a first portion, and in the first direction, one end of the gate electrode and one end of the first portion of the gate wiring layer are connected in a direction perpendicular to the first surface, and the gate Etching the polysilicon so that the first portion of the wiring layer is formed to extend in a second direction orthogonal to the first direction;
Forming an interlayer insulating film so as to cover the upper surface of the gate electrode, the first surface of the first semiconductor layer, and the gate wiring layer;
A mask formed directly over the gate wiring layer via the interlayer insulating film has a first portion, and the first portion of the mask is the first portion of the gate wiring layer in the first direction. Forming the mask so as to cover the first portion so as not to be exposed in a plan view and to extend in the second direction along the first portion of the gate wiring layer; ,
A recess having a first sidewall extending in the second direction along the first portion of the gate wiring layer and intersecting the gate electrode is formed on the surface of the interlayer insulating film on the gate electrode. Etching a region of the interlayer insulating film that is not covered with the mask by wet etching so that the first surface of the first semiconductor layer is not exposed on the bottom surface of the recess;
A portion of the first surface of the first semiconductor layer adjacent to the trench in the second direction and an upper end of a sidewall of the trench are exposed to the bottom surface of the recess, and the upper surface of the gate electrode is exposed. Then, after removing the mask so that the interlayer insulating film remains inside the trench from the first surface of the first semiconductor layer, the entire surface of the interlayer insulating film having the recess is dry etched. Etching with
Forming a first electrode electrically connected to the semiconductor layer on a surface of the semiconductor layer opposite to the first surface;
Forming a second electrode on the gate electrode that is insulated by the gate electrode and the interlayer insulating film and through which a current controlled by the gate electrode flows between the first electrode;
A method for manufacturing a semiconductor device, comprising: A first conductivity type first semiconductor layer having an impurity concentration of the first conductivity type lower than that of the semiconductor layer formed on the first conductivity type semiconductor layer is opposite to the first semiconductor layer. A trench that extends from the surface into the first semiconductor layer and extends in a first direction parallel to the first surface is formed in advance, and covers a bottom surface and a sidewall of the trench. Is formed in advance, and an insulating film that is connected to the gate insulating film at the upper end of the sidewall of the trench and covers the first surface of the first semiconductor layer is formed in advance, and the gate insulating film is interposed therebetween. Forming polysilicon on the first surface of the first semiconductor layer through the insulating film so as to fill the trench.
The gate electrode made of polysilicon is arranged in the first direction through the gate insulating film so that the upper surface thereof is located inside the trench with respect to the first surface of the first semiconductor layer. And a gate wiring layer made of polysilicon is formed on the first surface of the first semiconductor layer via the insulating film, and the gate wiring layer is formed in the trench. Has a first portion, and in the first direction, one end of the gate electrode and one end of the first portion of the gate wiring layer are connected in a direction perpendicular to the first surface, and the gate Etching the polysilicon so that the first portion of the wiring layer is formed to extend in a second direction orthogonal to the first direction;
Forming an interlayer insulating film so as to cover the upper surface of the gate electrode, the first surface of the first semiconductor layer, and the gate wiring layer;
A mask formed directly over the gate wiring layer via the interlayer insulating film has a first portion, and the first portion of the mask is the first portion of the gate wiring layer in the first direction. Forming the mask so as to cover the first portion so as not to be exposed in a plan view and to extend in the second direction along the first portion of the gate wiring layer; ,
A recess having a first sidewall extending in the second direction along the first portion of the gate wiring layer and intersecting the gate electrode is formed on the surface of the interlayer insulating film on the gate electrode. Etching a region of the interlayer insulating film that is not covered with the mask by wet etching so that the first surface of the first semiconductor layer is not exposed on the bottom surface of the recess;
A portion of the first surface of the first semiconductor layer adjacent to the trench in the second direction and an upper end of a sidewall of the trench are exposed to the bottom surface of the recess, and the upper surface of the gate electrode is exposed. Then, after removing the mask so that the interlayer insulating film remains inside the trench from the first surface of the first semiconductor layer, the entire surface of the interlayer insulating film having the recess is dry etched. Etching with
Forming a second semiconductor layer of a second conductivity type on the first surface of the first semiconductor layer so as to be adjacent to the gate insulating film on the sidewall of the trench;
The third semiconductor layer of the first conductivity type having a first conductivity type impurity concentration higher than that of the first semiconductor layer so as to be adjacent to the gate insulating film above the sidewall of the trench. Selectively forming on the surface of
Forming a first electrode electrically connected to the semiconductor layer on a surface of the semiconductor layer opposite to the first surface;
Forming a second electrode electrically connected to the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer on the third semiconductor layer and the gate electrode; When,
A method for manufacturing a semiconductor device, comprising: In the step of etching the polysilicon,
A second portion extending in the first direction perpendicular to the first portion of the gate wiring layer is formed on the first surface of the first semiconductor layer with the insulating film. Via to form further,
In the step of forming the mask,
The mask covers the second portion of the gate wiring layer so as not to be exposed in a plan view in the second direction, and extends in the first direction along the second portion of the gate wiring layer. Forming a second portion to stretch,
In the wet etching step,
The recess extends in the first direction along the second portion of the gate wiring layer, and the first semiconductor layer between the second portion of the gate wiring layer and the gate electrode 3. The method of manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed to have a second side wall formed on the first surface. In the dry etching step,
4. The portion of the first surface of the first semiconductor layer between the second sidewall of the recess and the gate electrode is further exposed to the bottom surface of the recess. Semiconductor device manufacturing method.   In the step of forming the second semiconductor layer, the second conductivity type second so as to be adjacent to the gate insulating film at the side wall of the trench on the first surface of the first semiconductor layer. At the same time as forming the semiconductor layer, the portion of the first surface of the first semiconductor layer exposed to the bottom surface of the recess between the second sidewall of the recess and the gate electrode, 5. The method of manufacturing a semiconductor device according to claim 4, further comprising forming a fourth semiconductor layer of the second conductivity type.   In the step of forming the second semiconductor layer, after the step of etching the interlayer insulating film by dry etching, the first semiconductor layer is formed by using the gate electrode and the interlayer insulating film as a mask. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the second semiconductor layer and the fourth semiconductor layer are simultaneously formed by implanting an impurity of a second conductivity type on the surface of the semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the impurity implantation of the second conductivity type is performed by ion implantation.   After the step of etching the interlayer insulating film by dry etching, the second conductivity type fifth semiconductor layer having a second conductivity type impurity concentration higher than that of the second semiconductor layer using the interlayer insulating film as a mask. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of selectively forming a surface of the fourth semiconductor layer on the surface of the fourth semiconductor layer.   9. The method according to claim 3, wherein the first sidewall or the second sidewall of the recess is not perpendicular to the first surface of the first semiconductor layer. The manufacturing method of the semiconductor device of description.   The first side wall or the second side wall of the recess is separated from the first part of the gate wiring layer or the second part of the gate wiring layer as it goes toward the first semiconductor layer. The method for manufacturing a semiconductor device according to claim 3, wherein the method is performed.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the first side wall or the second side wall of the recess is recessed toward the first semiconductor layer. A second portion extending in a first direction perpendicular to the first portion of the gate wiring layer is further formed on the first surface of the first semiconductor layer via the insulating film. ,
On the first surface of the first semiconductor layer, a second semiconductor layer of a second conductivity type adjacent to the gate insulating film on the side wall of the trench is further formed, and the gate electrode and the gate wiring Forming a fourth semiconductor layer of the second conductivity type between the second portion of the layer and
2. The method according to claim 1, further comprising the step of selectively forming a third semiconductor layer of the first conductivity type adjacent to the gate insulating film on the sidewall of the trench, on the surface of the second semiconductor layer. The manufacturing method of the semiconductor device of description.   13. The semiconductor according to claim 12, wherein the second semiconductor layer and the fourth semiconductor layer are formed on the first surface of the first semiconductor layer before the trench is formed. Device manufacturing method.   After the step of etching the interlayer insulating film by dry etching, the second conductivity type fifth semiconductor layer having a second conductivity type impurity concentration higher than that of the second semiconductor layer using the interlayer insulating film as a mask. 14. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of selectively forming on the surface of the fourth semiconductor layer.   15. The method for manufacturing a semiconductor device according to claim 1, wherein the dry etching is RIE.

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