CN111244167A - Gate groove filling method - Google Patents
Gate groove filling method Download PDFInfo
- Publication number
- CN111244167A CN111244167A CN202010060925.0A CN202010060925A CN111244167A CN 111244167 A CN111244167 A CN 111244167A CN 202010060925 A CN202010060925 A CN 202010060925A CN 111244167 A CN111244167 A CN 111244167A
- Authority
- CN
- China
- Prior art keywords
- hard mask
- substrate
- mask layer
- layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The application discloses a gate trench filling method, which comprises the following steps: providing a substrate, wherein a groove is formed on the substrate, and a hard mask layer is formed on the substrate except the groove; etching the hard mask layer and the substrate, removing the hard mask layer and forming an arc chamfer at the opening of the groove; forming a gate oxide layer on the surface of the substrate and the groove; and forming a polycrystalline silicon layer on the surface of the gate oxide layer, and filling the groove with the polycrystalline silicon layer to form a gate. This application is through forming the hard mask layer on the substrate at ditch groove gate device, after the slot that the grid corresponds formed, through carrying out the sculpture to hard mask layer and substrate, just make the slot opening part form arc chamfer when getting rid of the hard mask layer to behind the gate oxide layer of formation on slot and the substrate, gate oxide layer is difficult for causing of slot opening part and is piled up, thereby the opening width of slot has been improved, hollow formation probability when having reduced later stage polycrystalline silicon and having filled, the yield that the device was made has been improved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a gate trench filling method.
Background
Power devices typically include planar gate devices and trench gate devices. The trench gate of the trench gate device is formed by etching a deep trench in a substrate or an epitaxial layer, and the deep trench is filled with polysilicon to form a gate, so that the gate is located inside the substrate. The trench gate device has higher integration level, lower on-resistance, lower gate-drain charge density and higher current capacity, so that the trench gate device has lower switching loss and higher switching speed and is widely applied to the field of low-voltage power.
Referring to fig. 1, a cross-sectional view of a trench-gate device manufactured by a method provided by the related art is shown. As shown in fig. 1, in the trench gate device provided in the related art, since the gate oxide layer on the top of the trench 101 is thick (as shown by the dotted line in fig. 1), and the opening of the trench 101 is small, after the polysilicon filling is performed in the trench, a Void (Void)102 may occur in the formed gate 110, thereby reducing the yield of device manufacturing.
Disclosure of Invention
The application provides a gate trench filling method which can solve the problem of low yield caused by a manufacturing method of a trench gate device in the related art.
In one aspect, an embodiment of the present application provides a gate trench filling method, where the method is applied in a manufacturing process of a trench gate device, and the method includes:
providing a substrate, wherein a groove is formed on the substrate, and a hard mask layer is formed on the substrate except the groove;
etching the hard mask layer and the substrate, removing the hard mask layer and forming an arc-shaped chamfer at the opening of the groove;
forming a gate oxide layer on the surface of the substrate and the surface of the groove;
and forming a polycrystalline silicon layer on the surface of the gate oxide layer, wherein the polycrystalline silicon layer fills the groove to form a gate.
Optionally, the etching the hard mask layer and the substrate to remove the hard mask layer and form an arc-shaped chamfer at the trench opening includes:
in the first stage, carrying out first etching on the hard mask layer, thinning the hard mask layer and exposing the substrate within a preset width range at the opening of the groove;
in the second stage, performing second etching on the substrate to form a C-shaped recess at the opening of the trench;
and in the third stage, carrying out third etching on the hard mask layer, removing the residual hard mask layer and forming the arc-shaped chamfer at the opening of the groove.
Optionally, the performing the first etching on the hard mask layer includes:
and carrying out the first etching on the hard mask layer by a wet etching process.
Optionally, the third etching of the hard mask layer includes:
and carrying out the third etching on the hard mask layer by a wet etching process.
Optionally, the hard mask layer includes silicon oxide.
Optionally, the reaction solution in the wet etching process includes Hydrogen Fluoride (HF).
Optionally, the performing the second etching on the substrate includes:
and performing the second etching on the substrate by a dry etching process.
Optionally, in the process of forming the gate oxide layer on the surface of the substrate and the trench, the gate oxide layer is baked by hydrogen to form an arc-shaped chamfer at the opening of the trench.
Optionally, forming a polysilicon layer on the surface of the gate oxide layer includes:
and depositing the polycrystalline silicon layer on the surface of the gate oxide layer by a PVD (physical vapor deposition) process.
Optionally, after the depositing the polysilicon layer on the surface of the gate oxide layer by a Physical Vapor Deposition (PVD) process, the method further includes:
and removing the polysilicon layer outside the groove through a planarization process to expose the gate oxide layer outside the groove.
The technical scheme at least comprises the following advantages:
by forming the hard mask layer on the substrate of the trench gate device, after the trench corresponding to the grid is formed, the hard mask layer and the substrate are etched, the hard mask layer is removed, and an arc-shaped chamfer is formed at the opening of the trench, so that after the gate oxide layer is formed on the trench and the substrate, the gate oxide layer is not easy to cause accumulation at the opening of the trench, the opening width of the trench is increased, the formation probability of cavities during later-stage polysilicon filling is reduced, and the yield of device manufacturing is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a cross-sectional view of a trench-gate device manufactured by a method provided in the related art;
fig. 2 is a flow chart of a gate trench filling method provided by an exemplary embodiment of the present application;
fig. 3 to 7 are schematic views illustrating a gate trench filling method according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flow chart of a gate trench filling method provided by an exemplary embodiment of the present application is shown, the method being applicable to a manufacturing process of a trench gate device, and the method includes:
in step S1, a substrate having a trench formed thereon is provided, and a hard mask layer is formed on the substrate except for the trench.
Referring to fig. 3, a schematic cross-sectional view of a hard mask layer 320 formed on a substrate 310 is shown. As shown in fig. 3, a trench 301 is formed in a substrate 310, and a hard mask layer 320 is formed on the surface of the substrate 310 except for the trench 301. Optionally, hard mask layer 320 comprises silicon oxide (e.g., silicon dioxide, SiO)2). Illustratively, before the step S1, the method further includes: a hard mask layer 320 is deposited on the substrate 310 by a tetraethyl orthosilicate (TEOS) technique; covering photoresist on the surface of the hard mask layer 320 except the region corresponding to the trench 301 by a photolithography process; the hard mask layer 320 and the substrate 310 are etched to form a trench 301, and the photoresist is removed. Optionally, substrate 310 comprises silicon; optionally, the hard mask layer 320 has a thickness of
To 3000 angstroms.
And step S2, etching the hard mask layer and the substrate, removing the hard mask layer and forming an arc chamfer at the opening of the groove.
Referring to fig. 6, there is shown a cross-sectional view of etching the hard mask layer 320 and the substrate 310 to form an arcuate chamfer (shown in dashed lines in fig. 6) at the opening of the trench 301. As shown in fig. 6, the opening of the groove 301 is enlarged due to the formation of the arc-shaped chamfer.
And step S3, forming a gate oxide layer on the substrate and the surface of the groove.
And step S4, forming a polysilicon layer on the surface of the gate oxide layer, and filling the polysilicon layer into the groove to form a gate.
Referring to fig. 7, there is shown a schematic cross-sectional view of forming a gate oxide layer 330 on the surface of the substrate 310 and the trench 301, and filling a polysilicon layer 340 in the trench 301. As shown in fig. 7, since the arc-shaped chamfer is formed at the opening of the trench 301, the gate oxide layer 330 is difficult to form accumulation at the opening of the trench 301, thereby increasing the opening width of the trench 301 and reducing the probability of generating voids by filling the polysilicon layer 340.
Optionally, in this embodiment, during the process of forming the gate oxide layer 330 on the surface of the substrate 310 and the trench 301, hydrogen baking (H) is performed2Bake) to make the gate oxide layer 330 form an arc-shaped chamfer (as shown by a dotted line in fig. 7) at the opening of the trench 301, thereby avoiding the gate oxide layer 330 from deteriorating due to too sharp chamfer, and causing electric leakage.
Optionally, in this embodiment, the "forming a polysilicon layer on the surface of the gate oxide layer" includes but is not limited to: depositing a polysilicon layer 340 on the surface of the gate oxide layer 330 by a PVD process; the polysilicon layer outside the trench 301 is removed by a planarization process (e.g., a chemical mechanical polishing process) to expose the gate oxide layer 330 outside the trench 301.
In summary, in the embodiment, the hard mask layer is formed on the substrate of the trench gate device, and after the trench corresponding to the gate is formed, the hard mask layer and the substrate are etched, so that the arc-shaped chamfer is formed at the opening of the trench while the hard mask layer is removed, and therefore, after the gate oxide layer is formed on the trench and the substrate, the gate oxide layer is not easy to accumulate at the opening of the trench, thereby improving the opening width of the trench, reducing the probability of forming a cavity during later-stage polysilicon filling, and improving the yield of device manufacturing.
In an alternative embodiment, in the embodiment of fig. 2, step S2 includes but is not limited to:
in the first stage, the hard mask layer is etched for the first time, the hard mask layer is thinned, and the substrate in the preset width range of the groove opening is exposed.
Referring to fig. 4, a schematic cross-sectional view of the hard mask layer 320 after a first etch is shown. Taking the thickness of the hard mask layer 320 as 2000 angstroms for example, as shown in fig. 4, after the first etching, the thickness of the hard mask layer 320 is reduced to about 1000 angstroms (for example, 800 angstroms to 1200 angstroms), the substrate 310 near the opening of the trench 301 is exposed, and the predetermined width (the width of the region shown by the dotted line in fig. 4) of the exposed substrate 310 may range from 100 angstroms to 300 angstroms.
Optionally, in this embodiment, the "etching the hard mask layer for the first time" includes but is not limited to: performing a first etching on the hard mask layer 320 by a wet etching process; optionally, the reaction solution in the wet etching process includes hydrogen fluoride.
And at the second stage, performing second etching on the substrate to form a C-shaped recess at the opening of the trench.
Referring to fig. 5, a schematic cross-sectional view of the substrate 310 after a second etch is shown. Illustratively, as shown in fig. 5, after this stage, the thickness of the hard mask layer 320 is reduced to about 400 a (300 a to 500 a), and a C-shaped recess (shown by a dotted line in fig. 5) is formed at the opening of the trench 301.
Optionally, in this embodiment, the "etching the substrate for the second time" includes, but is not limited to: the silicon substrate 310 is etched a second time through a dry etching process.
And in the third stage, carrying out third etching on the hard mask layer, removing the residual hard mask layer and forming an arc chamfer at the opening of the groove.
Referring to fig. 6, a schematic cross-sectional view of the hard mask layer 320 after a third etching is shown. As shown in fig. 6, after this stage, the hard mask layer 320 is removed and an arc-shaped chamfer is formed at the trench opening (shown by the dashed line in fig. 6).
Optionally, in this embodiment, the "performing the third etching on the hard mask layer" includes, but is not limited to: performing a third etching on the hard mask layer 320 by a wet etching process; optionally, the reaction solution in the wet etching process includes hydrogen fluoride.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (10)
1. A gate trench filling method is applied to a manufacturing process of a trench gate device, and comprises the following steps:
providing a substrate, wherein a groove is formed on the substrate, and a hard mask layer is formed on the substrate except the groove;
etching the hard mask layer and the substrate, removing the hard mask layer and forming an arc-shaped chamfer at the opening of the groove;
forming a gate oxide layer on the surface of the substrate and the surface of the groove;
and forming a polycrystalline silicon layer on the surface of the gate oxide layer, wherein the polycrystalline silicon layer fills the groove to form a gate.
2. The method of claim 1, wherein etching the hard mask layer and the substrate, removing the hard mask layer and forming an arc-shaped chamfer at the trench opening comprises:
in the first stage, carrying out first etching on the hard mask layer, thinning the hard mask layer and exposing the substrate within a preset width range at the opening of the groove;
in the second stage, performing second etching on the substrate to form a C-shaped recess at the opening of the trench;
and in the third stage, carrying out third etching on the hard mask layer, removing the residual hard mask layer and forming the arc-shaped chamfer at the opening of the groove.
3. The method of claim 2, wherein the first etching of the hard mask layer comprises:
and carrying out the first etching on the hard mask layer by a wet etching process.
4. The method of claim 3, wherein the third etching of the hard mask layer comprises:
and carrying out the third etching on the hard mask layer by a wet etching process.
5. The method of claim 4, wherein the hard mask layer comprises silicon oxide.
6. The method of claim 5, wherein the reaction solution in the wet etching process comprises hydrogen fluoride.
7. The method of claim 2, wherein said second etching of said substrate comprises:
and performing the second etching on the substrate by a dry etching process.
8. The method of any of claims 1 to 7, wherein during said forming of a gate oxide layer on said substrate and said trench surface, said gate oxide layer is formed into an arc-shaped chamfer at said trench opening by a hydrogen bake.
9. The method of any of claims 1 to 7, wherein forming a polysilicon layer on a surface of the gate oxide layer comprises:
and depositing the polycrystalline silicon layer on the surface of the gate oxide layer by a PVD (physical vapor deposition) process.
10. The method of claim 9, wherein after the forming the polysilicon layer by the PVD process deposited on the gate oxide layer surface, further comprising:
and removing the polysilicon layer outside the groove through a planarization process to expose the gate oxide layer outside the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010060925.0A CN111244167B (en) | 2020-01-19 | 2020-01-19 | Gate trench filling method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010060925.0A CN111244167B (en) | 2020-01-19 | 2020-01-19 | Gate trench filling method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111244167A true CN111244167A (en) | 2020-06-05 |
| CN111244167B CN111244167B (en) | 2023-07-04 |
Family
ID=70872817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010060925.0A Active CN111244167B (en) | 2020-01-19 | 2020-01-19 | Gate trench filling method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111244167B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900124A (en) * | 2020-08-18 | 2020-11-06 | 华虹半导体(无锡)有限公司 | Method for forming isolation structure |
| CN112736024A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Etching method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277488A (en) * | 1999-03-23 | 2000-10-06 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| US20050153521A1 (en) * | 2004-01-14 | 2005-07-14 | Kenji Kanamitsu | Method of manufacturing a semiconductor device |
| CN104347378A (en) * | 2013-08-09 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Preparing method of trench gate applied to trench type MOS (metal oxide semiconductor) device |
| CN104576340A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for forming top fillets of deep trenches |
| CN105225940A (en) * | 2015-09-22 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | Trench process method |
| CN109904223A (en) * | 2019-01-23 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The process of gate trench top chamfer |
-
2020
- 2020-01-19 CN CN202010060925.0A patent/CN111244167B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277488A (en) * | 1999-03-23 | 2000-10-06 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| US20050153521A1 (en) * | 2004-01-14 | 2005-07-14 | Kenji Kanamitsu | Method of manufacturing a semiconductor device |
| CN104347378A (en) * | 2013-08-09 | 2015-02-11 | 上海华虹宏力半导体制造有限公司 | Preparing method of trench gate applied to trench type MOS (metal oxide semiconductor) device |
| CN104576340A (en) * | 2013-10-16 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for forming top fillets of deep trenches |
| CN105225940A (en) * | 2015-09-22 | 2016-01-06 | 上海华虹宏力半导体制造有限公司 | Trench process method |
| CN109904223A (en) * | 2019-01-23 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The process of gate trench top chamfer |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900124A (en) * | 2020-08-18 | 2020-11-06 | 华虹半导体(无锡)有限公司 | Method for forming isolation structure |
| CN112736024A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Etching method |
| CN112736024B (en) * | 2020-12-23 | 2022-06-07 | 华虹半导体(无锡)有限公司 | Etching method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111244167B (en) | 2023-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5945724A (en) | Trench isolation region for semiconductor device | |
| JP4763234B2 (en) | Deep insulating trench and method for forming the same | |
| US7910437B1 (en) | Method of fabricating vertical channel semiconductor device | |
| JP2000012676A (en) | Method of isolating elements through trenches of semiconductor device | |
| CN111244167B (en) | Gate trench filling method | |
| US20100129983A1 (en) | Method of Fabricating Semiconductor Device | |
| US7067387B2 (en) | Method of manufacturing dielectric isolated silicon structure | |
| CN111524800B (en) | Preparation method of field plate | |
| CN110867413A (en) | Method for forming single diffusion region cut | |
| CN113675078B (en) | Forming method of MOS device | |
| CN113506822A (en) | SGT structure and manufacturing method thereof | |
| CN110854073B (en) | Method for manufacturing grid | |
| WO2022083076A1 (en) | Manufacturing method for split-gate trench mosfet | |
| CN113594042A (en) | Manufacturing method of MOSFET | |
| KR100508535B1 (en) | Method for forming gate pole in a semiconductor | |
| KR100728649B1 (en) | Method for forming the isolation layer of semiconductor device | |
| JP2002237518A (en) | Semiconductor device and manufacturing method therefor | |
| CN111524801B (en) | Method for forming high-voltage field plate | |
| CN112259497B (en) | STI structure forming method | |
| CN112736024B (en) | Etching method | |
| JPH11274288A (en) | Manufacture of semiconductor device | |
| JPH09153542A (en) | Method of manufacturing semiconductor device | |
| CN114242650A (en) | High-voltage LDMOS device and preparation method thereof | |
| KR100202196B1 (en) | Method of forming an element isolation region in a semiconductor device | |
| CN113964079A (en) | STI structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |