JPH09129720A - Manufacture of trench-isolated separated semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the concentration of an electric field effectively by forming a gentle shape of the edge part, i.e., the shoulder part of a trench forming part in a semiconductor substrate. SOLUTION: An oxidation-resistant film 21 is formed on the surface of a semiconductor substrate 11 through an oxide film 15 so called a pad oxide film. Then, a trench 13, which is made in the semiconductor substrate 11 penetrating the oxidation-resistant film 21 and the oxide film 15, is formed. Thereafter, an undercut part 15u, which is expending with a width (d), is formed on the oxide film 15 by isotropic etching from the edge part of the trench 13 to the outside. Furthermore, an oxide film with a thickness (t) is formed on the inner surface of the trench 13 including the exposed surface of the semiconductor substrate exposed by the undercut of the oxide film. Thus, a trench- isolated separated semiconductor device is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench insulation isolation type in which insulation isolation between semiconductor elements in a semiconductor integrated circuit or insulation isolation between required portions in a semiconductor element is performed by trenches filled with an insulation layer. Related to the manufacturing method of semiconductor devices.

[0002]

2. Description of the Related Art In a semiconductor device, for example, a semiconductor integrated circuit, a so-called trench insulation isolation type semiconductor device is used in which isolation between semiconductor elements or required portions in the semiconductor element is performed by trenches filled with an insulating layer. Is widely practiced.

FIG. 8 is a schematic plan view of a main part of an example of the trench isolation semiconductor device, and FIG. 9 is a sectional view taken along the line AA. In this example, as a circuit element, M
A trench 3, that is, a cut groove is dug between element formation regions 2 where IS-FETs (insulated gate field effect transistors) are formed. Then, by thermally oxidizing the semiconductor substrate 1, SiO 2 is formed on the inner surface of the trench 3.
_{A 2} oxide film 8 is formed, and an oxide film 5 serving as a gate insulating film of the MIS-FET by thermal oxidation is formed on the surface of the element forming region 2 on the main surface 1a of the substrate 1. And trench 3
The inside is filled with a SiO ₂ insulating layer 4 formed by, for example, a CVD (Chemical Vapor Deposition) method.

Then, a polycrystalline semiconductor layer 6 made of polycrystalline silicon in which a gate electrode G is formed is formed in a predetermined pattern across the element formation region 2. Further, in the element formation region 2, the source S and the drain D are formed by introducing impurities, for example, by ion implantation using the gate electrode of the polycrystalline semiconductor layer 6 as a mask, thereby forming the MIS-FET.

The drain-source current _IDS characteristics with respect to the gate voltage of the MIS-FET having the trench isolation type semiconductor device structure should have a curve originally shown by a broken line as shown in FIG. A so-called hump current is generated as shown by the solid line curve.

As one of the causes, as shown in FIG. 11 in which the cross section of the trench portion is further enlarged, as shown in FIG.
The shape of the boundary portion with the trench 3, that is, the shape of the shoulder portion 2s is sharp, and the electric field is concentrated due to this shape. Such a sharp shoulder 2s is formed because an SiN film which is an oxidation resistant film is formed on a semiconductor substrate via a so-called pad oxide film in the process of manufacturing the trench isolation semiconductor device. Based on. That is, in the manufacturing process of this trench isolation semiconductor device, as shown in FIG.
The SiO ₂ oxide film 15 is formed on the element formation region 2 of the semiconductor substrate 1.
SiN oxidation resistant film 21 via so-called pad oxide film 15
Is formed, and thermal oxidation is performed using the oxidation resistant film 21 as a mask to form the oxide film 8 on the inner surface of the trench 3. At this time, element formation is performed due to the influence of the stress of the SiN oxidation resistant film 21. Compressive stress is generated on the surface of the region 2. Therefore, the degree of progress of oxidation differs between the surface of the element formation region 2 where the SiN oxidation resistant film 21 is formed and the inside of the trench 3 where the oxidation resistant film is not formed, so that the inner surface of the trench 3 is not oxidized. On the other hand, in the element formation region 2, the progress of the oxidation is slower, and as a result, the boundary between the element formation region 2 and the trench 3, that is, the shoulder portion 2s, is directed outward as shown in FIG. A protrusion 30 that protrudes sharply is generated. That is, the shoulder 2s is bent with a small radius of curvature.

The filling of the SiO ₂ insulating layer 4 into the trench 3 is accomplished by forming SiO ₂ on the entire surface by CVD.
After that, a method of etching back SiO ₂ from its surface is generally used. In this case, however, the surface of the SiO ₂ film entirely formed before the etching back has a dent at the portion where the trench 3 exists. Since it exists, when the etching back is performed on this, the recess 7 shown in FIG. 11 is generated.

Therefore, when the polycrystalline semiconductor layer 6 to be the gate electrode is formed over the shoulder portion 2s, the polycrystalline semiconductor layer 6 comes closer to the shoulder portion 2s and the electric field is further concentrated. The hump current described in FIG. 10 will be generated. Further, due to the concentration of the electric field, the withstand voltage is lowered and the threshold voltage V _th is lowered.

Various proposals have been made to avoid such inconvenience. For example, by tilting the side surface of the trench 3 with respect to the main surface 1a of the substrate 1 toward the bottom of the trench 3 to make the shoulder 2s obtuse, or by shouldering the shoulder 2s by high temperature thermal oxidation. A method such as making the curvature of the portion 2s gentle is adopted. However, these conventionally proposed methods are still not sufficient for avoiding the occurrence of the above-mentioned hump current and improving the decrease in the threshold voltage V _th .

Moreover, as described above, when the inclination of the side surface of the trench is made gentle, if the depth of the trench is sufficiently secured, it is inevitably necessary to make the opening width of the trench large, so that in the semiconductor integrated circuit. , Hinders high integration. However, it is known that when the inclination is made larger than 80 °, that is, closer to 90 °, the shape of the shoulder 2s is deteriorated, that is, the radius of curvature is reduced and the angle becomes an acute angle, and the hump current described above is generated.

Further, the heat treatment is performed at 950 ° C. to 1000 ° C.
By performing thermal oxidation under high temperature, especially in an atmosphere containing hydrochloric acid gas, the shoulder shape can be obtuse and hump current can be less likely to occur as compared with normal dry oxidation. However, this is only the effect of raising the inclination of the side surface of the trench capable of suppressing the hump current to about 80 °.

[0012]

DISCLOSURE OF THE INVENTION The present invention, in the above-mentioned trench isolation type semiconductor device, makes the shape of the edge portion, that is, the shoulder portion of the trench forming portion in the semiconductor substrate gentle to effectively concentrate the electric field there. To be able to avoid.

[0013]

A method of manufacturing a trench isolation semiconductor device according to the present invention comprises a step of forming an oxidation resistant film on a surface of a semiconductor substrate such as a silicon substrate through an oxide film, a so-called pad oxide film, and an oxidation resistant film. A trench formation step of forming a trench dug in the semiconductor substrate through the oxide film and the oxide film, and the oxide film is isotropically etched outward from the edge of the trench, that is, toward the bottom of the oxidation resistant film. An etching step of forming an undercut portion having a width d and an oxidation step of forming an oxide film having a thickness t on the inner surface of the trench including the exposed surface of the semiconductor substrate exposed by the undercut of the oxide film. Then, the intended trench isolation type semiconductor device is formed.

According to the above-described method of the present invention, an oxidation resistant film is formed on the semiconductor surface via an oxide film, the oxide film is once undercut, and then the semiconductor substrate surface and the trench inner surface at the undercut portion are formed. Since the oxide film is formed on the trench, it is possible to avoid the influence of the stress of the oxidation resistant film on the shoulder portion around the trench, and a large difference in the thickness of the oxide film between this portion and the trench inner surface may occur. This is effectively avoided, and the occurrence of sharp shoulders can be avoided.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a method for manufacturing a trench isolation semiconductor device according to the present invention will be described. An example of the manufacturing method of the present invention will be described in detail with reference to the process drawings shown in FIGS. As shown in the cross-sectional view in FIG. 1A, the surface of the semiconductor substrate 11 made of a single crystal silicon substrate is thermally oxidized to form an oxide film 15 having a thickness of, for example, about 10 nm, a so-called pad oxide film. An oxide resistant film 21 made of, for example, SiN, which is not affected by undercutting wet etching of the oxide film 15 and which serves as an oxidation mask, is formed to a thickness of, for example, about 100 nm. In addition, polycrystalline silicon is further deposited on the anti-oxidation film 21 to a thickness of about 100 nm to form the polycrystalline semiconductor layer 2
Form 2

As shown in FIG. 1B, the polycrystalline semiconductor layer 22
An etching mask layer 23 having an opening 23w formed in a trench formation portion is formed thereon. The etching mask layer 23 can be formed by photolithography by applying a photoresist layer, pattern exposure, and development. Then, using the etching mask layer 23 as an etching mask, the polycrystalline semiconductor layer 22, the oxidation resistant film 21, the oxide film 15, and the semiconductor substrate 11 are sequentially subjected to dry etching, for example, RIE (reactive ion etching).
Then, the pattern corresponding to the opening 23w is etched to form the trench 13 having a depth of, for example, 500 nm in the substrate 1.

As shown in FIG. 1C, the etching mask layer 23 is removed by so-called ashing, for example, and isotropic etching is performed by hydrofluoric acid, that is, so-called wet etching. The undercut portion 15u is formed by etching under the film 21 with a width d of, for example, about 30 nm from the edge portion toward the central portion.

Thereafter, as shown in FIG. 2A, an oxide film is formed on the surface of the silicon semiconductor substrate 1 exposed to the outside, that is, the inner surface of the trench and the main surface of the substrate 1 exposed to the outside by the undercut portion 15u, as shown in FIG. 2A. 18 is formed. In this thermal oxidation, for example, heating is performed at 1000 ° C. in a dry oxidizing atmosphere containing 1% hydrochloric acid to form an oxide film 18 having a thickness t of about 20 nm. Reference numeral 28 denotes an oxide film formed on the surface of the polycrystalline semiconductor layer by this thermal oxidation.

The relationship between the width d of the undercut portion 15u and the thickness t of the oxide film 18 is as follows.
It is desired that d ≧ t / 2, which is equal to or more than the amount of penetration from the surface of the silicon semiconductor substrate before the formation of the oxide film 18.

As shown in FIG. 2B, the inside of the trench 13 is buried and the SiO ₂ insulating layer 14 is entirely covered with the bias ECR.
(Electron Cyclotron Resonance) 1 by CVD method
It is formed to a thickness of about 000 nm.

As shown in FIG. 3A, the insulating layer 14 is flattened from its surface by chemical mechanical polishing so-called CMP to a position where the oxidation resistant film 21 is exposed, that is, this oxidation resistant film 21 is used as a stopper. Grind.

As shown in FIG. 3B, the oxidation resistant film 21 made of SiN is removed by etching with an etching solution of H ₃ PO ₄ . In this way, the element forming region 12 electrically separated by the trench 13 filled with the oxide film 18 and the insulating film 14 is formed.

As shown in FIG. 3C, for example, a polycrystalline silicon semiconductor layer 16 to be a gate electrode is entirely formed by a CVD method or the like, and pattern etching is performed by photolithography to form a desired pattern. By forming source and drain regions (not shown) in the element formation region 12 as a mask, the oxide film 15 is formed.
Is used as a gate insulating layer, and a circuit element such as a MIS-FET having a gate electrode formed of the polycrystalline semiconductor layer 16 is formed thereon.

According to the above-described method of the present invention, the shoulder portion 12s at the boundary between the element forming region 12 and the trench 13 is
It is formed with a gentle roundness, that is, with a large radius of curvature.

As described above, the shoulder 12s is formed with a gentle roundness as shown in FIG. 4C.
In the step shown in FIG. 5, an undercut portion 15u is formed in the pad oxide film 15 at the shoulder portion of the oxide film 15 to form a cavity here, so to speak, and is given to the shoulder portion 12s due to the stress of the SiN oxidation resistant film 21. Since the compression is eliminated, as shown in FIG. 5, in the thermal oxidation step of forming the oxide film 18 on the inner surface of the trench 13, due to the difference in the progress of oxidation as described in FIGS. 6 and 7. The occurrence of protrusions can be avoided and the shoulder 12s is gentle,
That is, a curve having a large radius of curvature is formed.

Further, after the trench 13 is entirely formed so as to be filled with the insulating layer 14, the SiN oxidation resistant film 2 is formed.
1 is, so to speak, a planar polishing by CMP to avoid the formation of a dent in the insulating layer 14 on the trench 13, thereby forming the polycrystalline semiconductor layer and the shoulder portion of the element formation region as described in FIG. It is possible to avoid the inconvenience that the two approach each other and further increase the concentration of the electric field.

In the above example, the circuit element is MIS-
Although the case of the FET has been mainly described, it goes without saying that the invention is not limited to such an example.

Further, in the above-mentioned example, the case where the isolation by the trench is formed between the circuit elements has been mainly described, but it is applicable to the case where the trench is formed in the region where the isolation is desired in the circuit element. You can also

[0029]

As described above, according to the present invention, since the shoulder portion of the element forming region can be made smooth, concentration of an electric field can be avoided.
In forming the FET, the problem of hump current and the reduction of the threshold voltage V _th can be avoided, and a highly reliable semiconductor device can be constructed.

Further, when the depression of the insulating layer on the trench is avoided, the concentration of the electric field can be avoided more and a more reliable trench insulation type semiconductor device can be constructed.

Further, since it is not always necessary to make the inclination angle of the trench gentle, in the semiconductor integrated circuit,
It is possible to avoid a decrease in integration density. It can be avoided.

[Brief description of the drawings]

1A to 1C are cross-sectional views of essential parts of some steps of an example of a method for manufacturing a trench isolation semiconductor device according to the present invention.

FIG. 2A and FIG. 2B are cross-sectional views of essential parts of some steps of an example of the method for manufacturing the trench isolation semiconductor device according to the present invention.

3A to 3C are cross-sectional views of essential parts of some steps of an example of the method for manufacturing the trench isolation semiconductor device according to the present invention.

FIG. 4 is a sectional view of an essential part in one manufacturing process for explaining the effect of the method of the present invention.

FIG. 5 is a cross-sectional view of a main part in one manufacturing process for explaining the effect of the method of the present invention.

FIG. 6 is a cross-sectional view of a main part in one manufacturing process for explaining the problem of the conventional method.

FIG. 7 is a cross-sectional view of a main part in one manufacturing process for explaining the problem of the conventional method.

FIG. 8 is a schematic plan view of a main part of a conventional trench isolation semiconductor device.

9 is a schematic sectional view taken along the line AA of FIG.

FIG. 10 is a transistor characteristic curve diagram in a conventional trench isolation semiconductor device.

11 is a sectional view of a further main part of FIG.

[Explanation of symbols]

 1, 11 Semiconductor substrate 2, 12 Element formation region 3, 13 Trench 4 Insulation layer 5, 8, 15, 18 Oxide film 6,16 Polycrystalline semiconductor layer 21 Oxidation resistant film 22 Polycrystalline semiconductor layer 23 Etching mask layer

Claims (3)

[Claims] 1. A step of forming an oxidation resistant film on a surface of a semiconductor substrate via an oxide film, and a step of forming a trench penetrating the oxidation resistant film and the oxide film into the semiconductor substrate. An etching step of forming an undercut portion in the oxide film, which is widened with a width d from the periphery of the trench to a lower portion of the oxidation resistant film by isotropic etching, and the semiconductor substrate exposed by the undercut of the oxide film And an oxidation step of forming an oxide film having a thickness t on the inner surface of the trench including the exposed surface of the trench insulation isolation type semiconductor device. 2. The method for manufacturing a trench isolation semiconductor device according to claim 1, wherein the undercut width d and the thickness t of the oxide film in the trench are set such that d ≧ t. 3. The method for manufacturing a trench isolation semiconductor device according to claim 1, wherein the oxidation resistant film is composed of a single layer having a silicon nitride layer or a laminated film with another material layer. .