JP2003218195A - Manufacturing method for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent remaining of a film at a side wall part of an element separating insulating film and decreasing of a lower layer film at a post-process, and to improve a process margin. <P>SOLUTION: A method of manufacturing a semiconductor device containing a mesa separation insulating film 18 that has an inclining side wall contains a process wherein a silicon nitride film 13 is formed on a p-type semiconductor substrate 11 (Fig. 1 (a)), a process wherein an opening 15 is formed in a region, where the mesa separation insulating film 18 should be formed, out of the silicon nitride film 13 (Fig. 1 (b)), a process wherein a burying silicon oxide film 17 consisting of an insulating material different from that of the silicon nitride film 13 is accumulated at least in the opening 15 (Fig. 1 (c), 1 (d)), and a process wherein the silicon nitride film 13 and a part of the burying oxide film 17 are so etched that a side wall of the burying oxide film 17 inclines (Fig. 1 (e)). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that is suitable for manufacturing a solid-state image pickup device.

[0002]

2. Description of the Related Art In recent years, as a next-generation image pickup device mounted on a portable device or the like, the power consumption is lower than that of a CCD image pickup device and the peripheral circuit parts such as an A / D conversion circuit and a signal processing circuit are the same. Attention has been focused on a MOS-type solid-state image pickup device (hereinafter, referred to as “MOS-type image pickup device”) which has an advantage that it can be formed on a chip.

However, conventionally, an element isolation technique using a thick thermally oxidized film selectively oxidized as an element isolation insulating film has been generally adopted. For this reason, the imaging element is likely to cause imaging failure.

(Prior Art 1) FIG. 6 is a sectional view showing a schematic structure of a MOS type image pickup device as a semiconductor device of the prior art 1.

A gate oxide film 10 is formed on the semiconductor substrate 101.
2 is formed, and the element isolation region field oxide film 103 is partially formed. Field oxide film 10
3 and the semiconductor substrate 101, the semiconductor substrate 101
An inversion prevention layer (channel stop layer) 104 is formed to prevent the surface of the element from being inverted by an electric field.

On the other hand, in the device region, the gate oxide film 10 is formed.
2, the gate electrode 105 of the MOS transistor is selectively provided. A drain region 106 of the MOS transistor is formed on the semiconductor substrate 101 adjacent to the gate electrode 105. Further, a photodiode 107 is formed on the semiconductor substrate 101 between the gate electrode 105 and the field oxide film 103.

(Prior Art 2) FIG. 7 is a cross-sectional view showing a schematic structure of a MOS image pickup element as a semiconductor device of the prior art 2. The MOS type image sensor of FIG. 7 has a CVD insulating film isolation structure in the element isolation region. P-type semiconductor substrate 201
A gate oxide film (insulating film) 202 is formed on the upper side, and a CVD insulating film (oxide film) 203 is partially formed on the gate oxide film (insulating film) 202. A P ⁺ type channel stop layer 204 is formed in a non-self-aligned manner at the interface between the CVD insulating film 203 and the P type semiconductor substrate 201.

FIG. 8 is a schematic manufacturing process diagram of the MOS type image pickup device shown in FIG.

First, a p-type semiconductor substrate 2 is used as a semiconductor substrate.
01 is prepared (FIG. 8A).

Next, the channel stop layer 204, which is a p + type inversion prevention layer, is formed on the surface of the p-type semiconductor substrate 201 by photolithography, etching and ion implantation.
Are formed (FIG. 8B).

Next, thermal oxidation is performed to form a gate oxide film 202 (FIG. 8C).

After that, p through the gate oxide film 202
A CVD insulating film 2031 is deposited on the entire surface of the mold semiconductor substrate 201 (FIG. 8D).

Next, a resist 1 is formed on the CVD insulating film 2031.
41 is applied (FIG. 8E).

Further, alignment is performed, and exposure and development are performed so that the resist 14 remains only on the channel stop layer 204 via the CVD oxide film 2031 (FIG. 8).
(F)).

Then, the region where the resist 14 is not applied is etched by anisotropic etching, and the resist 14 is peeled off to form the CVD insulating film 203 (FIG. 8G).

Then, as shown in FIG. 7, a gate electrode 205 of the MOS transistor is selectively provided in the element region via a gate oxide film 202. Further, on the semiconductor substrate 201, the drain region 206 of the MOS transistor and the photodiode 207 are formed.

[0017]

However, the conventional techniques have the following problems.

First, the MOS type image pickup device shown in FIG.
When the gate electrode 105 is turned on and a channel is formed immediately below the gate electrode 105, the signal of the photodiode 107 is read out via the drain region 106.

In the case of the MOS type image pickup device having this structure, since the field oxide film 103 is present in the vicinity of the photodiode 107, the field oxide film 1 formed by thermal oxidation is used.
Due to the high stress in the end portion (bird's beak) X of 03, a leak current due to thermal excitation is likely to occur. The leak current is caused to flow into the photodiode 107, which causes an increase in defective imaging such as white scratches and dark current, which are fatal to the imaging device.

In order to suppress the occurrence of such defective imaging, a method of providing a sufficient distance between the end portion X and the photodiode 107 is adopted, but this hinders miniaturization.

In the MOS type image pickup device shown in FIG. 7, the gate electrode 205 is turned on and a channel is formed immediately below the gate electrode 205, whereby the photodiode 20
7 signals are read out via the drain region 206.

According to the MOS type image pickup device having this structure, the leak current that causes an increase in image pickup defects can be reduced, but the angle of the side wall portion of the CVD insulating film 203 with respect to the semiconductor substrate 201 becomes steep and, for example, When the gate electrode 205 is formed by applying an electrode material film on the CVD insulating film in the process and forming the gate electrode 205, a film residue Y of the electrode material film easily occurs on the side wall of the CVD insulating film 203, which causes a wiring short circuit. Sometimes.

On the other hand, if etching is performed so that the film residue Y does not occur, overetching occurs and the gate oxide film 2
A film loss Z of 02 occurs, narrowing the process margin.

The cause of the steep angle of the side wall of the CVD insulating film 203 is that the CVD insulating film 2 is formed by anisotropic etching.
Although 031 was etched, in the conventional anisotropic etching, the formed sidewall shape is likely to be vertical.

On the other hand, isotropic etching, which is another etching method, can be used because the etching rates of the insulating film to be removed and the insulating film to be left are the same (because the same oxide film is left by etching). Can not.

Further, in the above-mentioned MOS type image pickup device, the inversion prevention layer 104 is formed in a self-aligned manner, whereas in the case of CVD insulating film separation, the channel stop layer 20 is formed.
4 is formed in a non-self-aligned manner with respect to the CVD insulating film 203, the channel stop layer 204 and the CV
It is necessary to provide a margin for aligning the D insulating film 203, and there is a limit to miniaturization.

Therefore, it is an object of the present invention to form an element isolation insulating film free from bird's beaks that cause a leak current.

Further, in the CVD insulating film 203, which is an insulating film for element isolation without bird's beaks, since the side wall is steep, the wiring short circuit due to the remaining film of the electrode material film and the gate oxide film 202 are formed in the subsequent process. This has caused a problem of narrowing the process margin such as film reduction.

Therefore, an object of the present invention is to improve the process margin.

A further object of the present invention is to form a channel stop layer, which is an inversion prevention layer, in a self-aligned manner even in the case of CVD insulating film separation, for example.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having an insulating film for element isolation in which bird's beak does not exist, and further forming a side wall of the insulating film for element isolation in an inclined manner. To do.

In addition, an object of the present invention is to provide a method of manufacturing a semiconductor device in which a channel stop layer for preventing inversion is formed in a self-aligned manner.

[0033]

In order to solve the above problems, the present invention provides a method of manufacturing a semiconductor device having an element isolation region whose sidewalls are inclined, in which a first insulating film is formed on a semiconductor substrate. A step of opening a region of the first insulating film where the element isolation region is to be formed, and an insulator made of an insulating material different from the insulating material of the first insulating film in at least the opened region. It is characterized by including a step of depositing and a step of etching the first insulating film and a part of the insulator so that a sidewall of the insulator is inclined.

That is, the present invention provides a manufacturing method which can easily form a bird's beak-free semiconductor device having an insulating film for element isolation whose sidewalls are inclined. In this way, a process margin for film remaining on the side wall of the element isolation insulating film and film loss of the lower layer film is sufficiently obtained.

Moreover, the effect of stress (generation of leak current) is reduced by forming the element isolation insulating film without high temperature heat treatment.

Furthermore, by forming the inversion prevention layer in a self-aligned manner with respect to the element isolation insulating film, it is possible to easily cope with high integration (miniaturization).

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1A to 1E.
FIG. 3A is a schematic cross-sectional view showing the outline of the method for manufacturing the semiconductor device according to the first embodiment of the present invention. In this embodiment,
An explanation will be given by taking an example of a MOS type image pickup device having an insulating deposited film separation structure whose sidewalls are inclined.

In FIGS. 1 (a) to 1 (e), 11 is a p-type semiconductor substrate as a semiconductor substrate, and 18 is a device isolation insulation having a shape in which the side wall and the p-type semiconductor substrate 11 form an angle θ. A mesa isolation insulating film as a film, 13 is a silicon nitride film as a first insulating film formed on the p-type semiconductor substrate 11, 15 is an opening formed at a position where the mesa isolation insulating film 18 is formed, 14 Is a resist film for forming the opening 15, 171 is a silicon oxide film as an insulator formed on the silicon nitride film 13 so as to include the opening 15,
Reference numeral 17 denotes a buried silicon oxide film which is a silicon oxide film deposited in the opening 15.

Next, the method for manufacturing the semiconductor device of this embodiment will be described in detail.

First, the silicon nitride film 13 is deposited on the semiconductor substrate 11 by a method such as a CVD method or a sputtering method (FIG. 1A).

At this time, if necessary, the silicon nitride film 1
Prior to the formation of 3, a silicon oxide film that can serve as a gate insulating film may be formed on the p-type semiconductor substrate 11.

Next, a resist film 14 is formed on the silicon nitride film 13, and the position of the resist film 14 where the opening 15 is to be formed is patterned and opened by photolithography. Then, the silicon nitride film 13 is etched using the resist film 14 as a mask to form the opening 15
Are formed (FIG. 1B).

Then, after peeling off the resist film 14,
Low pressure CVD is performed on the silicon nitride film 13 including the opening 15.
After depositing the silicon oxide film 171 by a method or the like, the silicon oxide film 171 is heat-treated at a high temperature to be densified in order to form an electrically stable insulating film as needed (FIG. 1C). ).

Next, using the silicon nitride film 13 as a polishing stopper, for example, CMP of the silicon oxide film 171 is performed to remove the silicon oxide film 171 above the silicon nitride film 13. In this way, the buried silicon oxide film 17 to be the element isolation region is left in the opening 15 (FIG. 1).
(D)).

Next, the silicon nitride film 13 and a part of the buried silicon oxide film 17 are etched to form a mesa isolation insulating film 18 (FIG. 1 (e)).

In this way, the buried silicon oxide film 17 is formed.
The side wall of is inclined, and the mesa isolation insulating film 18 is obtained.

The angle θ of the inclination angle formed by the mesa isolation insulating film 18 and the semiconductor substrate 11 makes it difficult for the electrode material film to remain near the sidewalls when the electrode material film is formed in a later step.
At least 85 degrees or less. Here, in order to make it more preferable, it is set to 70 degrees to 80 degrees.

By the way, if the angle θ is too gentle, the area occupied by the element isolation region in the semiconductor device becomes large, leading to a decrease in the aperture ratio. As described above, it is suitable that the angle θ is 70 degrees to 80 degrees.

In the present embodiment, the etching method may be either wet etching or dry etching. In particular, the etching rate for the silicon oxide film 17 is slower than the etching rate for the silicon nitride film 13. It is preferable to perform the etching under the conditions.

As the etching under the conditions, there may be mentioned wet etching using an etchant of phosphoric acid and hydrofluoric acid.

Further, dry etching is preferable to wet etching because the shape after etching can be easily controlled. As the dry etching used in the present invention, plasma etching mainly using radicals or reactive ion etching (RIE) is performed.
Is preferably used.

As the etching device, a plasma etching device having a barrel type or parallel plate type electrode structure or a microwave plasma etching device can be used.

For example, a parallel plate type RF plasma etching apparatus was used to place a semiconductor substrate on the cathode.
When reactive ion etching is performed, when the etching pressure is about 0.43 Pa, the RF power is 180 W, the etching gas is SF ₆ 100 sccm, and CHF ₃ is 10 sccm, the embedded silicon oxide film 17 is used.
The etching rate ratio of the silicon nitride film 13 to the silicon nitride film 13 is 1: 4.5, and the side wall angle θ of the mesa isolation insulating film 18 is about 75 degrees.

The angle θ of the side wall depends on the etching gas S
Since it can be controlled by the mixing ratio of F ₆ / CHF ₃ , the side wall angle θ
Is greater than 75 degrees, the proportion of CHF _{3 in} the mixed etching gas is increased, and conversely, when the side wall angle θ is desired to be smaller than 75 degrees, the proportion of CHF ₃ may be decreased.

As described above, in the method of manufacturing a semiconductor device of the present invention, the step of forming the first insulating film on the semiconductor substrate and the step of forming the element isolation region in the first insulating film are performed. Opening step, depositing an insulator made of an insulating material different from the insulating material of the first insulating film in at least the opened area, and insulating the first insulating film so that the sidewalls of the insulator are inclined. A step of etching a part of the body,
It does not form bird's beaks. Thus, the stress is low and the high temperature thermal oxidation step is not included.

In addition, in the step of etching the insulator to be the element isolation insulating film, the sidewalls are etched at an angle, so that various films remain in the subsequent steps and the lower layer film is reduced by overetching. Is earning enough process margin against.

The insulating film may be a silicon oxide nitride film. In that case, it is preferable to use hydrofluoric acid as the etchant.

(Second Embodiment) FIG. 2 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention. The semiconductor device shown in FIG. 2 is manufactured by the method described in FIG.

In FIG. 2, 12 is a p-type semiconductor substrate 11.
A gate insulating film formed on the insulating film 19 and a gate insulating film 12
The gate electrode 20 formed on the p-type semiconductor substrate 11
A drain electrode 21 is formed inside the gate electrode 19 so as to be adjacent to the gate electrode 19, and a photodiode (light receiving portion) 21 is formed at a position that is paired with the drain electrode 20 with the gate electrode below. 2, the same parts as those shown in FIG. 1 are designated by the same reference numerals.

The semiconductor device of this embodiment has the p-type semiconductor substrate 11 after the step of FIG. 1E described in the first embodiment.
By forming the gate insulating film 12 on the p-type semiconductor substrate 11 and selectively forming the gate electrode 19, the drain region 20, and the photodiode (light receiving portion) 21 of the MOS transistor in the element region on the p-type semiconductor substrate 11, It is a semiconductor device including the image pickup device section of the manufactured MOS type image pickup device.

As described in the first embodiment, the semiconductor device of the present embodiment can prevent the film loss of the lower layer film and the like, so that the process margin is improved.

(Third Embodiment) FIG. 3 is a schematic sectional view showing an outline of a method for manufacturing a semiconductor device according to a third embodiment of the present invention. In FIG. 3, 16 is a channel stop layer as an inversion prevention layer. In FIG. 3, the same parts as those shown in FIG. 1 are designated by the same reference numerals.

In addition to the first embodiment, the present embodiment further includes the step of forming an inversion prevention layer on the semiconductor substrate in a self-aligned manner. That is, it differs from the first embodiment in that the channel stop layer 16 is formed in the step of FIG. The other steps are the same as those in the first embodiment.

In FIG. 3B, a resist film is formed on the silicon nitride film 13, and the resist film is patterned by photolithography to form a resist film 14 having an opening at a portion where an element isolation region is to be formed. Form. Using the resist film 14 as a mask, the silicon nitride film 13 is etched to form an opening 15 in the silicon nitride film 13 corresponding to the element isolation region.

Next, an impurity element such as boron [B] or gallium [Ga] is ion-implanted through the opening 15 in a self-aligned manner to p-type channel stop serving as an inversion prevention layer in the p-type semiconductor substrate 11. Form layer 16.

As in this embodiment, the channel stop layer 1
By forming 6 on the p-type semiconductor substrate 11, the mesa isolation insulating film 18 can be thinned, which is suitable for miniaturization.

Further, since the channel stop layer 16 is formed in a self-aligned manner with respect to the mesa isolation insulating film 18, it is not necessary to consider an alignment margin, which is suitable for higher integration (miniaturization). Is.

(Fourth Embodiment) FIG. 4 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device shown in FIG. 4 is manufactured by the method described in FIG.

Similar to the second embodiment, the semiconductor device of the present embodiment is manufactured by forming the gate insulating film 12 and the like after the step of FIG. 3E described in the third embodiment.

(Fifth Embodiment) FIG. 5 is a schematic sectional view showing an outline of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. In FIG. 5, the same parts as those shown in FIG. 3 are designated by the same reference numerals.

In this embodiment, the step of forming the gate insulating film 12 is included before the step of forming the silicon nitride film 13. That is, in the step of FIG. 5A, the step of forming the gate insulating film 12 as the second insulating film made of a material different from the silicon nitride film between the p-type semiconductor substrate 11 and the silicon nitride film 13. Is further included. The other steps are the same as those in the third embodiment, except that FIG.
It is not necessary to separately form the gate insulating film 12 in the process corresponding to.

In this embodiment, the gate insulating film 12 is formed by thermally oxidizing the p-type semiconductor substrate 11 before depositing the silicon nitride film 13 on the p-type semiconductor substrate 11. Next, the silicon nitride film 13 is deposited by a method such as a CVD method or a sputtering method (FIG. 5A).

By forming the gate insulating film 12 before forming the silicon nitride film 13 as in this embodiment, the occurrence of substrate defects due to the stress of the silicon nitride film 13 is suppressed and the embedded CVD oxide film 17 is formed. It is suitable because it plays a role of a substrate protective film when the side wall of the is etched at an inclination.

[0075]

As described above in detail, according to the present invention,
Since the side wall of the element isolation region is inclined, it is possible to manufacture a semiconductor device having an element isolation insulating film in which no bird's beak exists. It is possible to prevent film loss and improve the process margin.

Furthermore, according to the present invention, it is possible to form the channel stop layer which is the inversion prevention layer in a self-aligned manner with respect to the element isolation region.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view schematically showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing the outline of the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 4 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing the outline of the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a schematic configuration of a MOS type image pickup device as a semiconductor device of Prior Art 1.

FIG. 7 is a cross-sectional view showing a schematic configuration of a MOS image pickup element as a semiconductor device according to the related art 2.

FIG. 8 is a schematic manufacturing process diagram of the MOS-type image pickup device shown in FIG. 7.

[Explanation of symbols]

11 p-type semiconductor substrate 12 Gate insulating film 13 Silicon nitride film 14 Resist film 15 openings 16 channel stop layer 17 Embedded silicon oxide film 171 Silicon oxide film 18 Mesa isolation insulation film 19 Gate electrode 20 drain region 21 photodiode

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device having an element isolation region whose sidewalls are inclined, comprising a step of forming a first insulating film on a semiconductor substrate, and forming the element isolation region of the first insulating film. Opening a region to be formed, depositing an insulator made of an insulating material different from the insulating material of the first insulating film in at least the opened region, and so that a sidewall of the insulator is inclined. And a step of etching the first insulating film and a part of the insulator, the method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an inversion prevention layer on the semiconductor substrate in a self-aligned manner via the opened region. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is dry etching or wet etching. 4. The method according to claim 1, further comprising the step of forming a second insulating film made of an insulating material different from that of the first insulating film, between the semiconductor substrate and the first insulating film. A method for manufacturing a semiconductor device as described above. 5. The method of manufacturing a semiconductor device according to claim 1, wherein etching is performed so that an angle of inclination formed between the sidewall of the element isolation region and the semiconductor substrate is 85 degrees or less. 6. The method of manufacturing a semiconductor device according to claim 1, which is a step of etching so that an inclination angle formed by the sidewall of the element isolation region and the semiconductor substrate is 70 degrees or more and 80 degrees or less. ..