JPH05304143A - Formation of isolation region - Google Patents

Formation of isolation region

Info

Publication number
JPH05304143A
JPH05304143A JP11021692A JP11021692A JPH05304143A JP H05304143 A JPH05304143 A JP H05304143A JP 11021692 A JP11021692 A JP 11021692A JP 11021692 A JP11021692 A JP 11021692A JP H05304143 A JPH05304143 A JP H05304143A
Authority
JP
Japan
Prior art keywords
isolation region
film
forming
silicon
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11021692A
Other languages
Japanese (ja)
Inventor
Kenichi Azuma
賢一 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP11021692A priority Critical patent/JPH05304143A/en
Publication of JPH05304143A publication Critical patent/JPH05304143A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To grow a LOCOS oxide sufficiently by etching a silicon substrate, removing side wall, and then performing oxidation to expose a polysilicon film thereby suppressing bird's beak. CONSTITUTION:A silicon substrate 1 is sequentially deposited with a silicon oxide 2, a polysilicon 3, and a silicon nitride 4, and then subjected to isolation patterning. Silicon nitride is then removed from an isolation region to expose the surface of the polysilicon 3 thus forming an opening. A pattern 8 is then removed and a silicon oxide 5 is deposited on the entire surface by CCD method and subsequently etched back to form a side wall 6 at the opening. The polysilicon 3 and silicon oxide 2 are then removed through etching with the silicon nitride 4 and the side wall 6 as a mask. Thereafter, the side wall 6 is removed by means of diluted HF solution and oxidation is performed in wet atmosphere thus forming an isolation region 7.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は素子分離領域の形成方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an element isolation region.

【0002】[0002]

【従来の技術】大容量の超LSIを開発するには、限ら
れたチップ面積内での集積度の高い集積回路を開発する
ことが必要となり、トランジスタの微細化、素子分離領
域の微細化が要求される。
2. Description of the Related Art In order to develop a large-capacity VLSI, it is necessary to develop an integrated circuit having a high degree of integration within a limited chip area, which requires miniaturization of transistors and element isolation regions. Required.

【0003】通常、素子分離領域の形成には、選択酸化
法と呼ばれる方法が用いられる。この方法は、シリコン
基板にシリコン窒化膜を形成し、フォトリソグラフィ工
程によりパターニングし、素子分離領域となる部分のシ
リコン窒化膜を除去し、露出したシリコン基板表面を選
択的に酸化して、素子分離領域を形成する方法である。
Generally, a method called selective oxidation method is used for forming the element isolation region. This method involves forming a silicon nitride film on a silicon substrate, patterning it by a photolithography process, removing the silicon nitride film in the area that will become the element isolation region, and selectively oxidizing the exposed silicon substrate surface to isolate the element. This is a method of forming a region.

【0004】[0004]

【発明が解決しようとする課題】しかし、従来の技術を
用いた場合、素子分離領域の縮小に関して、以下の点が
問題となる。
However, in the case of using the conventional technique, the following points are problems regarding the reduction of the element isolation region.

【0005】まず、選択酸化時に、開口部周辺のシリコ
ン窒化膜との界面のシリコン基板が酸化され、バーズビ
ークと呼ばれるシリコン酸化膜が広がり、マスクサイズ
より素子領域が狭くなり、集積回路の微細化が困難にな
る。
First, at the time of selective oxidation, the silicon substrate at the interface with the silicon nitride film around the opening is oxidized, the silicon oxide film called bird's beak spreads, the element region becomes narrower than the mask size, and the integrated circuit is miniaturized. It will be difficult.

【0006】また、バーズビークを抑制する技術とし
て、シリコン窒化膜の横にサイドウォールを形成する方
法、基板上にシリコン酸化膜、ポリシリコン膜及びシリ
コン窒化膜を順に形成し、シリコン窒化膜を開口し、選
択酸化を行うポリロコス法などがある。
As a technique for suppressing bird's beak, a method of forming a sidewall beside a silicon nitride film, a silicon oxide film, a polysilicon film and a silicon nitride film are sequentially formed on a substrate, and a silicon nitride film is opened. , There is a polylocos method for performing selective oxidation.

【0007】サイドウォールを形成する方法において
は、パターンの微細化に伴い選択酸化膜の開口幅が小さ
くなり、ロコス膜厚が、広い開口部の場合に比べ薄くな
るという問題が生じ、フィールドのしきい値電圧が下が
る等の問題が生じる。また、ポリロコス法においては、
ロコス膜厚は、微細なパターンにおいても確保される
が、上面のポリシリコン膜が酸化された後に基板が酸化
されるため、基板における酸化が少なくなり、実効的な
分離距離が短くなるため、分離耐圧が下がるという問題
が生じる。
In the method of forming the sidewall, there is a problem that the opening width of the selective oxide film becomes smaller as the pattern becomes finer, and the locos film thickness becomes thinner than that in the case of a wide opening portion. Problems such as a decrease in the threshold voltage occur. In the Polylocos method,
Although the Locos film thickness is ensured even in a fine pattern, since the substrate is oxidized after the polysilicon film on the upper surface is oxidized, the oxidation in the substrate is reduced and the effective separation distance is shortened, so that the separation There is a problem that the breakdown voltage is lowered.

【0008】本発明は、十分のロコス酸化膜が成長した
素子分離領域を形成する方法を提供することを目的とす
る。
An object of the present invention is to provide a method of forming an element isolation region in which a sufficient amount of locos oxide film has been grown.

【0009】[0009]

【課題を解決するための手段】本発明の素子分離領域の
形成方法は、シリコン基板上に第1の酸化膜、ポリシリ
コン膜及び窒化膜を順に形成する工程と、パターニング
及びエッチングにより素子分離領域となる部分の前記窒
化膜を除去し、前記ポリシリコン膜表面を露出させ、開
口部を形成する工程と、全面に第2の酸化膜を形成し、
エッチバックにより前記開口部の側壁にサイドウォール
を形成する工程と、前記サイドウォールをマスクとし
て、前記ポリシリコン膜及び第1の酸化膜を除去し、所
定の深さまで前記シリコン基板をエッチングする工程
と、前記サイドウォールを除去した後、酸化を行い、素
子分離領域を形成する工程とを有することを特徴とする
ものである。
A method of forming an element isolation region according to the present invention comprises a step of sequentially forming a first oxide film, a polysilicon film and a nitride film on a silicon substrate, and patterning and etching. A step of removing the nitride film in a portion to be formed, exposing the surface of the polysilicon film and forming an opening, and forming a second oxide film on the entire surface,
Forming a side wall on the side wall of the opening by etching back; and using the side wall as a mask to remove the polysilicon film and the first oxide film and etch the silicon substrate to a predetermined depth. After removing the sidewall, oxidation is performed to form an element isolation region.

【0010】[0010]

【作用】上記発明を用いることにより、シリコン基板表
面から十分な深さまでシリコン酸化膜が形成され、かつ
従来よりバーズビークが抑制された素子分離領域が形成
される。
By using the above-described invention, a silicon oxide film is formed to a sufficient depth from the surface of a silicon substrate, and an element isolation region in which bird's beak is suppressed as compared with the conventional case is formed.

【0011】[0011]

【実施例】以下に、一実施例に基づいて本発明を詳細に
説明する。図1は、本発明の一実施例の製造工程図であ
る。
EXAMPLES The present invention will be described in detail below based on examples. FIG. 1 is a manufacturing process diagram of an embodiment of the present invention.

【0012】まず、シリコン基板1上に、酸化防止膜と
してシリコン酸化膜2を膜厚約100Åに、ポリシリコ
ン膜3を膜厚300〜900Åに、及びシリコン窒化膜
4を膜厚1200〜1600Åに順に形成し、次にフォ
トリソグラフィ工程により素子分離領域となる部分のパ
ターニングを行う(図1(a))。
First, on the silicon substrate 1, a silicon oxide film 2 as an antioxidant film having a film thickness of about 100 Å, a polysilicon film 3 having a film thickness of 300 to 900 Å, and a silicon nitride film 4 having a film thickness of 1200 to 1600 Å. The layers are sequentially formed, and then a portion to be an element isolation region is patterned by a photolithography process (FIG. 1A).

【0013】次に、プラズマエッチング等により、素子
分離領域となる部分のシリコン窒化膜4を除去し、ポリ
シリコン膜3表面を露出させ、開口部を形成する。次
に、リソグラフィ工程により形成されたパターン8を除
去した後、全面にCVD法によりシリコン酸化膜5を形
成し(図1(b))、RIE法を用いてエッチバックを
行うことにより、開口部側面に膜厚約1000Åのサイ
ドウォール6を形成する(図1(c))。
Next, by plasma etching or the like, the silicon nitride film 4 in the portion which becomes the element isolation region is removed, the surface of the polysilicon film 3 is exposed, and an opening is formed. Next, after removing the pattern 8 formed by the lithography process, the silicon oxide film 5 is formed on the entire surface by the CVD method (FIG. 1B), and the etch-back is performed by the RIE method to form the opening. A side wall 6 having a film thickness of about 1000Å is formed on the side surface (FIG. 1C).

【0014】次に、シリコン窒化膜4及びサイドウォー
ル6をマスクとして、ポリシリコン膜3及びシリコン酸
化膜2を除去し、シリコン基板1の表面から深さ700
〜800Åまでエッチングする(図1(d))。
Next, the polysilicon film 3 and the silicon oxide film 2 are removed using the silicon nitride film 4 and the sidewall 6 as a mask, and the depth 700 from the surface of the silicon substrate 1 is removed.
Etching is performed up to 800 Å (Fig. 1 (d)).

【0015】次に、サイドウォール6を希HF溶液で除
去し(図1(e))、ウェット雰囲気中で酸化を行い、
素子分離領域7を形成する(図1(f))。
Next, the side wall 6 is removed with a dilute HF solution (FIG. 1E), and oxidation is performed in a wet atmosphere.
The element isolation region 7 is formed (FIG. 1F).

【0016】次に、煮沸リン酸を用いて、シリコン窒化
膜4を、RIE法を用いてポリシリコン膜3を除去し、
通常の工程に従って、トランジスタ等の半導体素子を形
成すれば、半導体集積回路が構成される。
Next, the silicon nitride film 4 is removed by using boiling phosphoric acid, and the polysilicon film 3 is removed by using the RIE method.
A semiconductor integrated circuit is formed by forming a semiconductor element such as a transistor according to a normal process.

【0017】[0017]

【発明の効果】以上、詳細に説明した様に、本発明を用
いることにより、予めシリコン基板をエッチングしてお
くため、ポリロコス法で問題となる基板の深さ方向に対
して実効的な素子分離距離を確保できる。また、サイド
ウォールを除去した後、酸化を行うので、従来よりもポ
リシリコン膜が露出されており、バーズビークを抑制
し、且つロコス酸化膜を十分に成長させることができ
る。
As described above in detail, since the silicon substrate is previously etched by using the present invention, effective element isolation in the depth direction of the substrate, which is a problem in the polylocos method, is obtained. The distance can be secured. Further, since the oxidation is performed after removing the sidewalls, the polysilicon film is exposed more than in the conventional case, bird's beak can be suppressed, and the locos oxide film can be sufficiently grown.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の形成工程図である。FIG. 1 is a process drawing of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 シリコン酸化膜 3 ポリシリコン 4 シリコン窒化膜 5 シリコン酸化膜 6 サイドウォール 7 素子分離領域 8 パターン 1 Silicon Substrate 2 Silicon Oxide Film 3 Polysilicon 4 Silicon Nitride Film 5 Silicon Oxide Film 6 Sidewall 7 Element Isolation Area 8 Pattern

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板上に第1の酸化膜、ポリシ
リコン膜及び窒化膜を順に形成する工程と、 パターニング及びエッチングにより素子分離領域となる
部分の前記窒化膜を除去し、前記ポリシリコン膜表面を
露出させ、開口部を形成する工程と、 全面に第2の酸化膜を形成し、エッチバックにより前記
開口部の側壁にサイドウォールを形成する工程と、 前記サイドウォールをマスクとして、前記ポリシリコン
膜及び第1の酸化膜を除去し、所定の深さまで前記基板
をエッチングする工程と、 前記サイドウォールを除去した後、酸化を行い、素子分
離領域を形成する工程とを有することを特徴とする、素
子分離領域の形成方法。
1. A step of sequentially forming a first oxide film, a polysilicon film and a nitride film on a silicon substrate, and a step of patterning and etching to remove the nitride film in a portion to be an element isolation region, and the polysilicon film Exposing the surface to form an opening; forming a second oxide film on the entire surface and forming a sidewall on the sidewall of the opening by etching back; and using the sidewall as a mask A step of removing the silicon film and the first oxide film and etching the substrate to a predetermined depth; and a step of removing the side wall and then oxidizing the substrate to form an element isolation region. A method for forming an element isolation region.
JP11021692A 1992-04-28 1992-04-28 Formation of isolation region Pending JPH05304143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11021692A JPH05304143A (en) 1992-04-28 1992-04-28 Formation of isolation region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11021692A JPH05304143A (en) 1992-04-28 1992-04-28 Formation of isolation region

Publications (1)

Publication Number Publication Date
JPH05304143A true JPH05304143A (en) 1993-11-16

Family

ID=14530018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11021692A Pending JPH05304143A (en) 1992-04-28 1992-04-28 Formation of isolation region

Country Status (1)

Country Link
JP (1) JPH05304143A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970053411A (en) * 1995-12-22 1997-07-31 김주용 Device Separation Method of Semiconductor Device
KR100337073B1 (en) * 1994-10-04 2002-11-23 주식회사 하이닉스반도체 Isolation method of semiconductor device
KR100364124B1 (en) * 1995-12-22 2003-02-11 주식회사 하이닉스반도체 Method for manufacturing isolation layer in semiconductor device
KR20030051001A (en) * 2001-12-20 2003-06-25 동부전자 주식회사 Method for forming isolation layer in semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100337073B1 (en) * 1994-10-04 2002-11-23 주식회사 하이닉스반도체 Isolation method of semiconductor device
KR970053411A (en) * 1995-12-22 1997-07-31 김주용 Device Separation Method of Semiconductor Device
KR100364124B1 (en) * 1995-12-22 2003-02-11 주식회사 하이닉스반도체 Method for manufacturing isolation layer in semiconductor device
KR20030051001A (en) * 2001-12-20 2003-06-25 동부전자 주식회사 Method for forming isolation layer in semiconductor device

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