KR100568028B1 - Structure And Method For Isolation Of Semiconductor Device - Google Patents

Abstract

The semiconductor device isolation structure and method of the present invention is to form a trench in an isolation region of a semiconductor substrate, form a spacer on the sidewall of the trench, gap fill an oxide layer in the trench, and planarize the oxide layer to isolate the trench. To form.

Therefore, according to the present invention, the sidewalls of the trench can be changed from a vertical plane to a sloping plane by the spacers, thereby gap filling without creating voids in the trenches and further preventing grooves from occurring on the surface of the isolation layer. This improves the reliability of the shallow trench isolation process.

Accordingly, the present invention can prevent a defect such as electrical connection of the transistor gate by conductive residue remaining in the trench portion of the isolation layer even after a subsequent gate forming process or silicide process, thereby reducing leakage current of the transistor. It can reduce and improve the electrical characteristics of the semiconductor device. As a result, the yield of the semiconductor element can be improved.

Trench, Spacer, Gap Filling, Grooved

Description

Structure and Method for Isolation of Semiconductor Device             

1A and 1D are cross-sectional process diagrams illustrating a conventional shallow trench isolation process.

2 is a cross-sectional view showing a semiconductor device isolation structure according to the present invention.

3A to 3G are cross-sectional process diagrams illustrating a semiconductor device isolation method according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device isolation, and more particularly to semiconductor device isolation to improve the reliability of shallow trench isolation processes by preventing grooves from occurring on the surface of the isolation layer in the trench. It relates to a structure and a method.

In general, LOCOS (Local Oxidation of Silicon) technology has been used as an isolation technology for semiconductor devices. Since then, new isolation technologies have been actively developed to compensate for the shortcomings of LOCOS technology, and among them, technologies such as PBL (Poly Buffer LOCOS) and R-LOCOS (Recessed LOCOS) have been widely used. These techniques are not only complicated, but also fundamentally prevent the Bird's Beak, which leads to the erosion of the channel region by the silicon oxide film, thereby limiting the high integration of semiconductor devices. Moreover, since the surface step between the active area and the field area of the silicon substrate is severely generated, the planarization process must be subsequently performed to reduce the surface step.

Recently, a shallow trench isolation (STI) process has been introduced that improves this. The shallow trench isolation process is very advantageous for high integration of semiconductor devices because of excellent device isolation characteristics and a small occupied area as compared to conventional isolation technologies.

The shallow trench isolation process includes forming a trench in an isolation region of a silicon substrate, gap filling an oxide layer in the trench by a gap filling process, and then chemically mechanically polishing the oxide layer. CMP) is used to planarize the oxide film and the silicon substrate in the trench. Therefore, the oxide film is formed only in the trench of the isolation region of the silicon substrate.

The oxide film gap-filling the trench may be an O ₃ -TEOS (Tetra-Ethyl-Ortho-Silicate) Atmospheric Pressure Chemical Vapor Deposition (APCVD) process or a sub-atmospheric chemical vapor phase having good gap filling and planarization characteristics. Oxide films using the Subatmospheric Pressure Chemical Vapor Deposition (SACVD) process, or High Density Plasma Chemical Vapor Deposition (HDP CVD) or plasma enhanced chemical vapor deposition (PECVD) The used oxide film is mainly used.

On the other hand, the conventional shallow trench isolation process, as shown in FIG. 11), and a nitride film 13 as an etch mask layer is deposited thereon. Then, an opening 14 of the nitride film 13 and the buffer oxide film 11 is formed on the isolation region of the semiconductor substrate 10 using a photolithography process.

Next, the trench 15 is formed by etching the exposed semiconductor substrate 10 in the opening 14 to a desired depth by using the nitride film 13 as an etch masking layer. Subsequently, although not shown in the drawings, a thermal oxide film (not shown) may be grown to a thickness of, for example, several hundred microseconds on an etched surface of the exposed semiconductor substrate 10 in the trench 15 using a thermal oxidation process. It is possible.

As shown in FIG. 1B, an oxide film 17 such as an insulating film for gap filling, for example a nondoped silicate glass (NSG) film, is then used in the trench 15, for example, using a high density plasma deposition process. Gap fill. At this time, the oxide film 17 is also deposited on the surface of the nitride film 13.

As shown in FIG. 1C, the oxide film 17 is subsequently etched to an arbitrary thickness to remove impurities in the oxide film 17 of FIG. 1B, and the oxide film 17 is densified by a high temperature heat treatment process.

Then, the oxide film 17 is planarized using a planarization process such as a chemical mechanical polishing process to completely remove the oxide film 17 on the nitride film 13 and to form a material of the oxide film 17 in the trench 15. An isolation layer 19 is formed.

As shown in FIG. 1D, the isolation layer 19 is then wet etched to a certain thickness with a hydrofluoric acid solution to lower the surface of the isolation layer 19.

Subsequently, the nitride oxide layer 13 is etched with a phosphoric acid solution to expose the buffer oxide layer 11 under the nitride layer 13, and the buffer oxide layer 11 is etched with a hydrofluoric acid solution to thereby etch the active region of the semiconductor substrate 10. Expose Thus, the shallow trench isolation process is complete.

However, in the conventional shallow trench isolation process, the gap filling process is performed in a state where the vertical sidewall of the trench 15 and the vertical sidewall of the opening 14 are exposed, so that the oxide layer 17 is applied to the trench 15. It is difficult to fully gap fill. An empty space, that is, a void 18, is formed in the oxide film 17 of the trench 15.

After the planarization of the oxide layer 17 and etching of the nitride layer 13 and the buffer oxide layer 11, the groove 20 is exposed on the surface of the isolation layer 19. Moreover, it is difficult to detect the groove portion 20 in the inspection step.

Therefore, after the gate electrode forming process is performed in the exposed state of the groove 20, a conductive residue 21 such as a polycrystalline silicon material, such as a material for the gate electrode, is likely to remain in the groove 20. . In addition, when the groove 20 is exposed after the gate electrode forming process, a material for silicide formation, for example, conductive residues 21 such as Ti and Co may easily remain in the subsequent silicide process. This increases the leakage current of the transistor by causing a gate bridge to electrically connect the transistor gates to each other. Therefore, the electrical characteristics of the semiconductor device are deteriorated, and further, the yield of the semiconductor device is lowered. In addition, the reliability of the shallow trench isolation process is degraded.

Such phenomena are intensified as the integration of semiconductor devices increases, and thus a method for solving them is urgently needed.

Accordingly, an object of the present invention is to improve the reliability of the shallow trench isolation process by preventing grooves from occurring on the surface of the isolation layer in the trench.                         

Another object of the present invention is to reduce the electrical current of the semiconductor device by reducing the leakage current of the semiconductor device.

Another object of the present invention is to improve the yield of semiconductor devices.

The semiconductor device isolation structure according to the present invention for achieving the above object is

A semiconductor substrate having an active region in which elements are formed and a trench separating the elements; Spacers formed on sidewalls of the trenches; And an insulating film gap-filled and planarized in the trench.

Preferably, the liner insulating layer may be formed outside the spacer in the trench.

The semiconductor device isolation method according to the present invention for achieving the above object is

Forming a trench that separates the elements of the semiconductor substrate; Forming a spacer on sidewalls of the trench; Gap filling an insulating film for gap filling in the trench; And planarizing the entire substrate including the insulating film for gap filling.

Preferably, the spacer can be formed of either an oxide film or a nitride film.

Preferably, the method may further include forming a nitride film and an oxide film on the entire substrate before forming the trench.

Preferably, forming a nitride film and an oxide film on the entire substrate before forming the trench; And forming a trench liner insulating layer before forming the spacer.

Hereinafter, a semiconductor device isolation structure and method according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part which has the same structure and the same action as the conventional part.

2 is a cross-sectional structural view showing a semiconductor device isolation structure according to the present invention. Referring to FIG. 2, in the semiconductor device isolation structure of the present invention, an active region of the semiconductor substrate 10 is exposed, a trench 25 is formed in an isolation region that is an isolation region of the semiconductor substrate 10, and the trench is formed. A liner oxide film 31 is formed on the inner surface of the trench 25, a spacer 35 is formed on the sidewall of the trench 25, and an insulating film for gap filling, eg, an oxide film 39, is formed on the trench 25. Gap filling. In addition, the liner oxide film 31, the spacer 35, and the oxide film 39 in the trench 25 form a substantially isolation layer 40, and planarize the active region of the semiconductor substrate 10.

In addition, since the spacer 35 is formed on the vertical sidewall of the trench 25 to form a gentle slope, the oxide layer 39 is gap-filled in the trench 25 without generation of voids, and the isolation layer 40 is formed. Grooves are not formed on the surface of).

Therefore, the reliability of the semiconductor device isolation structure of the present invention can be improved. That is, it is possible to prevent the conductive residue such as a polycrystalline silicon layer for the gate electrode from remaining on the surface of the isolation layer in a subsequent gate electrode forming step. In addition, since the groove portion does not occur even after the gate electrode forming process, it is possible to prevent the remaining metal material for forming the silicide, for example, conductive residues such as Ti and Co in the subsequent silicide process.

Accordingly, the present invention can prevent a defective phenomenon such as the electrical connection of the transistor gate by the conductive residue, thereby reducing the leakage current of the transistor and improving the electrical characteristics of the semiconductor device. As a result, the yield of the semiconductor element can be improved.

3A to 3G are cross-sectional process diagrams illustrating a semiconductor device isolation method according to the present invention.

Referring to FIG. 3A, first, a buffer oxide film 11 is formed on a semiconductor substrate 10 such as, for example, a single crystal silicon substrate. In more detail, the buffer oxide film 11 is grown to a thickness of 40 to 150 Å on the entire surface of the semiconductor substrate 10 by a high temperature thermal oxidation process. Subsequently, a nitride film 13 serving as a hard mask layer is laminated on the buffer oxide film 11 by a chemical vapor deposition process, for example, a low pressure chemical vapor deposition process.

Here, the buffer oxide film 11 is to relieve stress that the semiconductor substrate 10 is subjected to when the nitride film 13 is directly deposited on the semiconductor substrate 10. The nitride film 13 serves as an etch mask layer when the trench 25 is formed, and also serves as an anti-oxidation film in a thermal oxidation process of the semiconductor substrate 10, and may be etched in a planarization process such as a chemical mechanical polishing process. It plays a role as stop film.

 Then, a pattern of the photosensitive film 21 having an opening 22 for exposing the isolation region of the semiconductor substrate 10 is formed on the nitride film 13. Subsequently, the nitride film 13 and the buffer oxide film 11 in the opening 22 are dry-etched using a pattern of the photoresist film 21 as an etch masking layer, for example, reactive ion etching (RIE). By etching completely by the process, an isolation region which is an isolation region of the semiconductor substrate 10 is exposed.

Referring to FIG. 3B, after the photoresist layer 21 of FIG. 3A is removed, the exposed isolation region of the semiconductor substrate 10 may be dry-etched, for example, using the nitride layer 13 as an etch masking layer. The trench 25 is formed by etching to a desired depth by a Reactive Ion Etching (RIE) process.

Referring to FIG. 3C, a liner oxide film 31, on the surface of the nitride film 13 as well as the inner surface of the trench 25, is then subjected to a chemical vapor deposition process, for example a low pressure chemical vapor deposition process. For example, a TEOS film is deposited to a thickness of 100 to 150 kPa. Of course, it is also possible to form a liner oxide film on the surface of the trench 25 by a thermal oxidation process.

Subsequently, an insulating film for the spacer 35 of FIG. 3D, for example, an oxide film 33 is formed on the liner oxide film 31 using a chemical vapor deposition process, for example, a low pressure chemical vapor deposition process. Deposit to thickness. Of course, it is also possible to use a nitride film or the like as the insulating film for the spacer 35.

Referring to FIG. 3D, the spacers 35 are formed on both sidewalls of the trench 25 by treating the oxide film 33 of FIG. 3C by, for example, an etch back process. In this case, it is preferable to remove both the oxide film 33 and the liner oxide film 31 on the nitride film 13. This is to easily etch the nitride film 13 in a subsequent etching process of the nitride film 13.

Therefore, since the spacer 35 forms the sidewalls of the trench 25 in a gentle inclined surface, voids may be prevented from occurring in the oxide film 37 in the trench 25 in a subsequent gap filling process.

Referring to FIG. 3E, an oxide film 37 such as a gap filling insulating film, for example, a nondoped silicate glass (NSG) film, is desired in the trench 25 by using, for example, a high density plasma chemical vapor deposition process. The gap filling is performed by vapor deposition.

In this case, since the spacer 35 changes the sidewall of the trench 25 from a vertical plane to a gentle inclined plane, the oxide film 37 may be completely gap-filled in the trench 25. Therefore, the present invention can prevent the occurrence of voids in the oxide film 37 of the trench 25.

Thereafter, the oxide film 37 is densified by a heat treatment process and then etched by an arbitrary thickness to remove impurities present on the surface of the oxide film 37.

Referring to FIG. 3F, the oxide film 37 of FIG. 3E is then planarized by a planarization process, for example, a chemical mechanical polishing process or an etch back process, to thereby completely remove the oxide film 37 outside the trench 25. And the oxide film 39 is left in the trench 25. In this case, the spacer 35 and the liner oxide layer 31 are also planarized together with the oxide layer 39.

Subsequently, the oxide layer 39, the spacer 35, and the liner oxide layer 31 in the trench 25 are etched by, for example, a wet etching process, thereby reducing the surface step with the active region of the semiconductor substrate 10. . At this time, no groove is formed on the surface of the oxide film 39 because voids do not occur when the oxide film 37 of FIG. 3E is gap-filled in the trench 25.

Referring to FIG. 3G, the active of the semiconductor substrate 10 is then removed by, for example, removing the nitride film 13 outside the trench 25 and removing the buffer oxide film 11 using a wet etching process. The region is exposed and a substantial isolation layer 40 is formed in the trench 25. Thus, the shallow trench isolation process of the present invention is completed.

Here, when the buffer oxide layer 11 is etched, the oxide layer 39, the spacer 35, and the liner oxide layer 31 are also etched together, and thus, between the isolation layer 40 and the active region of the semiconductor substrate 10. Surface steps can be significantly reduced. In addition, no groove is formed on the surface of the isolation 40.

Therefore, the reliability of the semiconductor device isolation process of the present invention can be improved. In other words, it is possible to prevent the conductive residue such as the polycrystalline silicon layer for the gate electrode from remaining on the surface of the isolation layer in a subsequent gate electrode forming process. In addition, since the groove portion does not occur even after the gate electrode forming process, it is possible to prevent the remaining of a conductive material such as Ti, Ta, Co, etc. for silicide formation in a subsequent silicide process.

Accordingly, the present invention can prevent a defective phenomenon such as the electrical connection of the transistor gate by the conductive residue, thereby reducing the leakage current of the transistor and improving the electrical characteristics of the semiconductor device. As a result, the yield of the semiconductor element can be improved.

As described in detail above, in the semiconductor device isolation structure and method according to the present invention, a trench is formed in an isolation region of a semiconductor substrate, a spacer is formed on a sidewall of the trench, a gap fill is formed in the trench, and the oxide film is formed. By planarizing the isolation layer is formed in the trench.

Therefore, according to the present invention, the sidewalls of the trench can be changed from a vertical plane to a sloping plane by the spacers, thereby gap filling without creating voids in the trenches and further preventing grooves from occurring on the surface of the isolation layer. This improves the reliability of the shallow trench isolation process.

Accordingly, the present invention can prevent a defect such as electrical connection of the transistor gate due to the conductive residue remaining in the trench portion of the isolation layer even after the subsequent gate formation process or silicide process, and thus leakage of the transistor. It can reduce the current and improve the electrical characteristics of the semiconductor device. As a result, the yield of the semiconductor element can be improved.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (7)

A semiconductor substrate having an active region in which elements are formed and a trench separating the elements; And A liner insulating film, a spacer, and a gap filling insulating film are formed sequentially along the inner circumferential surface of the trench, and each has an upper surface exposed at a surface height of the active region. Semiconductor device isolation structure comprising a. delete A first step of sequentially forming an oxide film and a nitride film on the entire surface of the semiconductor substrate; Forming a trench in the semiconductor substrate to separate the elements; Forming a liner insulating layer on an entire surface of the substrate on which the trench is formed; Forming an oxide film or a nitride film on the liner insulating film, removing the upper film of the liner insulating film and the liner insulating film by an etch back process, and forming a spacer; A fifth step of gap filling the insulating film for gap filling in the trench; And And a sixth step of planarizing the entire substrate including the gap filling insulating film. delete delete delete The method of claim 3, wherein the sixth step of planarizing the entire substrate comprises: Removing the gap filling insulating film outside the trench; Etching the gap filling insulating film, the spacer, and the liner insulating film inside the trench to reduce a surface step with the active region of the substrate; And Sequentially etching the nitride film and the oxide film outside the trench formed in the first step to reduce the surface step Semiconductor device separation method further comprising.

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