KR100979711B1 - Method for gapfill in semiconductor device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a trench gapfill method of a semiconductor device capable of suppressing the generation of voids during a trench gapfill process and suppressing defects such as displacement of the trench periphery due to a difference in thermal expansion coefficient. Forming a first trench by etching one side of the silicon substrate using the pad layer as an etch barrier; Recessing the pad layer; Forming a spacer on sidewalls of the first trench and sidewalls of the pad layer; Forming a polysilicon film gap-filling the inside of the first trench; Forming a second trench shallower than the first trench on the other side of the silicon substrate; And forming an oxide film gap-filling the second trench, and the present invention described above can gap fill a deep trench without voids by widening the inlet of the trench by a pull back process and a spacer process of the pad nitride film. By using a polysilicon film as a gap fill material, there is almost no difference in coefficient of thermal expansion, so defects such as displacement around the trench can be prevented.

Trench, High Voltage Device, Defect, Gap Fill, Polysilicon Film

Description

Trench gap fill method of semiconductor device {METHOD FOR GAPFILL IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly, to a trench gap fill method.

Deep Trench Isolation (DTI) is a method of forming a trench having a depth of several μm or more and gap-insulating the inside of the trench with an insulating material such as an oxide film.

As the integration progresses, the width decreases faster than the depth of the deep trench, which makes it difficult to gapfill the inside of the trench without voids.

1A to 1D are cross-sectional views illustrating a trench gap fill method of a semiconductor device according to the related art.

As shown in FIG. 1A, after the pad oxide film 12 and the pad nitride film 13 are formed on the silicon substrate 11, a DTI process is performed. For example, after etching the pad nitride layer 13 and the pad oxide layer 12 using the hard mask layer 14 as an etch barrier, the silicon substrate 11 is etched to form the first trenches 15. The first trench 15 is a deep trench.

As shown in FIG. 1B, after forming the photoresist 16 for the STI process, an etching process is performed to form the second trench 17.

As shown in FIG. 1C, after removing the photoresist 16, an oxide film 19 gap-filling the first and second trenches is deposited. The liner oxide film 18 may be formed before the oxide film 19 is deposited.

As shown in FIG. 1D, after the planarization of the oxide film 19, the pad nitride film is removed. As a result, the device isolation film 20A gap-filling the first trench and the device isolation film 20B gap-filling the second trench are formed.

However, in the prior art, since the photoresist 16 applied for the STI process is also applied in the deep first trench, the photoresist residue remains in the first trench even after the photoresist is removed. This remaining photoresist residue contaminates subsequent processes.

Further, the prior art cannot avoid the generation of voids (see reference 'A') due to the high aspect ratio of the deep first trench. These voids are exposed by a subsequent planarization process, a cleaning process, etc., so that a photoresist, a gate conductive film, etc. remain in the voids, which causes leakage currents and defects.

In addition, in the related art, due to a difference in thermal expansion coefficient between an oxide film and a silicon substrate used as a gapfill material, strain is largely generated around the trench in subsequent thermal processes, thereby causing defects such as displacement.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and an object thereof is to provide a trench gap fill method of a semiconductor device capable of suppressing the generation of voids during a trench gap fill process.

Another object of the present invention is to provide a trench gap fill method of a semiconductor device capable of suppressing defects such as displacement of trench peripheral portions due to differences in thermal expansion coefficients.

The trench gapfill method of the present invention for achieving the above object comprises the steps of forming a trench by etching the first silicon film using the pad film as an etch barrier; Recessing the pad layer; Forming a spacer on sidewalls of the trench and sidewalls of the pad layer; Forming a second silicon film gap-filling the inside of the trench; Recessing a surface of the second silicon film; And gap-filling an oxide film on the recessed second silicon film.

In addition, the trench gapfill method of the present invention comprises the steps of forming a first trench by etching one side of the silicon substrate using the pad layer as an etch barrier; Recessing the pad layer; Forming a spacer on sidewalls of the first trench and sidewalls of the pad layer; Forming a polysilicon film gap-filling the inside of the first trench; Recessing a portion of the polysilicon film gap-filled in the first trench while forming a second trench shallower than the first trench on the other side of the silicon substrate; And forming an oxide film gap-filling the first trench and the second trench.

According to the present invention described above, since the photo process for STI is performed after gap trenching the deep trench, photoresist can be prevented from remaining.

In addition, by widening the trench inlet by the pull back process and the spacer process of the pad nitride film, a deep trench can be gap-filled without voids.

In addition, by using the polysilicon film as the gap fill material, there is almost no difference in coefficient of thermal expansion, so that defects such as displacement around the trench can be prevented.

In addition, since the oxide film is gap-filled on the polysilicon film used as the device isolation film, the polysilicon film may be prevented from being doped during the subsequent ion implantation process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

2A to 2H are cross-sectional views illustrating a trench gapfill method according to a first embodiment of the present invention.

As shown in FIG. 2A, a pad oxide film 22 and a padding film 23 are formed on the first silicon film 21. The first silicon layer 21 may have a region in which a deep trench is formed. The pad oxide film 22 is a material for stress relaxation of the pad nitride film 23. The first silicon film 21 includes a silicon substrate doped with impurities.

Next, a trench 24 is formed in the first silicon film 21 by performing a photo process and an etching process for the trench. In order to form the trench 24, the pad nitride film 23 and the pad oxide film 22 are etched using a photoresist pattern (not shown) as an etch barrier, and the pad silicon film 23 is subsequently etched into the first silicon film. Proceed in the order of etching (21). In order to secure an insufficient etching margin of the photoresist pattern, a hard mask such as an oxide film may be applied.

The trench 24 is used as a trench for isolation between devices of a high voltage semiconductor device, and is thus also referred to as a deep trench.

As shown in FIG. 2B, a pullback process for recessing the pad film is performed. The recess of the pad film may proceed only to the pad nitride film or to the pad oxide film. Hereinafter, it is assumed that only the pad nitride film is recessed.

As a result, the pad nitride film 23A having the reduced surface thickness and the sidewall thickness remains, and the pad nitride film 23A is recessed in the shoulder portion of the trench 24 (see reference numeral 'R').

The pull back process of the pad nitride layer uses a wet etching method, for example, a dip method using an etching solution. Phosphoric acid (H ₃ PO ₄ ) solution is used as an etching solution.

According to the above, the inlet of the trench 24 is widened by the pull back process of the pad nitride film 23A. As such, when the inlet of the trench 24 is widened, the aspect ratio of the trench 24 is reduced to allow gap fill without voids in the subsequent trench gap fill process.

As illustrated in FIG. 2C, an oxide film is deposited on the entire surface and then dry-etched to form the spacers 25. The spacer 25 is formed to cover the sidewall of the trench 24 and the sidewall of the pad nitride film 23A. The spacer 25 has a thickness of 500 to 3000 mm 3.

As shown in FIG. 2d, an annealing process is performed in an oxygen atmosphere. By such an annealing process, the damage generated during the dry etching described above can be removed, and the spacer 25 is densified.

In particular, as the annealing process proceeds in an oxygen atmosphere, the bottom and sidewall surfaces of the trench 24 may be oxidized. Accordingly, the sidewall oxide layer 26 may be grown on the bottom and sidewalls of the trench 24. Here, as the bottom surface of the trench 24 is directly exposed to the annealing process, the thickness grown on the bottom surface of the trench 24 grows thicker than the thickness grown on the sidewall surface.

As shown in FIG. 2E, a second silicon film 27 gap-filling the inside of the trench 24 is formed. In order to form the gap fill inside of the trench 24, the second silicon film 27 is deposited on the entire surface until the gap 24 is gap-filled, and then chemical mechanical polishing is performed until the pad nitride film 23A is exposed. It is planarized by Mechanical Poishing (CMP) process. Since the inlet of the trench 24 is widened by the pull back process of the pad nitride film 23A during the deposition of the second silicon film 27, a gap fill is possible without voids.

Unlike the first silicon layer 21, the second silicon layer 27 is an undoped polysilicon layer that is not doped with impurities. Typically, the polysilicon film has an insulating property unless impurities are doped. When the polysilicon film is used as a gap fill film, there is no difference in coefficient of thermal expansion with the first silicon film 21, so that stress is not generated around the trench in a subsequent thermal process. For reference, the thermal expansion coefficient of the oxide film is 5.6 × 10 ⁻⁷ / K, but the polysilicon film is about 2.6 × 10 ⁻⁶ / K.

As shown in FIG. 2F, the surface of the second silicon film 27 is recessed. The recess of the second silicon film 27 uses dry etching. After the recess of the second silicon film, a groove may be formed on the second silicon film 27A.

As shown in FIG. 2G, a liner oxide 28 is formed on the recessed second silicon film 27A. The liner oxide film 28 may be formed by an oxidation process.

Subsequently, after forming the gap fill oxide film 29 gap-filling the upper portion of the second silicon film 27A on the liner oxide film 28, the chemical mechanical polishing process (CMP) is performed until the pad nitride film 23A is exposed. ), The gap fill oxide film 29 is planarized. Here, the gapfill oxide layer 29 may include a silicon oxide layer (SiO ₂ ) series or polysilasane spin on glass (PSOG).

As shown in FIG. 2H, the pad nitride film 23A is removed using a phosphoric acid solution.

Looking at the result after the pad nitride film 23A is removed, the device isolation film embedded in the trench 24 includes a spacer 25, a sidewall oxide film 26, a liner oxide film 28, and a gap fill oxide film 29. A second silicon film 27A surrounded by these oxide films is included.

According to the first embodiment described above, by using the second silicon film 27A, which is a polysilicon film, as a gap fill material, it is possible to prevent the occurrence of a defect due to stress around the trench. In addition, since the second silicon film 27A is not exposed to the outside by the gap fill oxide film 29, the second silicon film 27A may be prevented from being doped by a subsequent ion implantation process. In addition, a trench gap fill is possible without voids by the pull back process and the spacer.

FIG. 2I illustrates a trench gapfill structure according to the first exemplary embodiment of the present invention. The deep trench 24 has a structure in which the second silicon film 27A is positioned inside the oxide film 200. This is because the oxide film 200 includes all of the materials surrounding the second silicon film 27A in FIG. 2H. That is, since the pad oxide film 22, the spacer 25, the sidewall oxide film 26, the liner oxide film 28, and the gap fill oxide film 29 of FIG. 2H are all oxide films, the second silicon film 27A is formed inside the oxide film 200. ) Will be located.

3A to 3H are cross-sectional views illustrating a trench gapfill method according to a second exemplary embodiment of the present invention.

As shown in FIG. 3A, a pad oxide film 32 and a pad nitride film 33 are formed on the semiconductor substrate 31. In the semiconductor substrate 31, a first trench region DTI and a second trench region STI are defined. The first trench region is a region where deep trenches are formed, and the second trench region is a region where shallow trenches are formed. The semiconductor substrate 31 includes a silicon substrate and is doped with impurities. Deep trenches have a depth of at least 1 μm and shallow trenches have a depth of 0.5 μm or less.

Subsequently, a photo trench and an etching process for the first trenches are performed to form the first trenches 34 in the semiconductor substrate 31. In order to form the first trenches 34, the pad nitride layer 33 and the pad oxide layer 32 are etched using a photoresist pattern (not shown) as an etch barrier, and the pad nitride layer 33 is subsequently etched using a semiconductor substrate. Proceed in the order of etching (31). In order to secure an insufficient etching margin of the photoresist pattern, a hard mask such as an oxide film may be applied.

The first trench 34 is used as a trench for isolation between devices of the high voltage semiconductor device, and is thus also referred to as a deep trench.

As shown in FIG. 3B, a pullback process of recessing the pad nitride layer 33 is performed. Accordingly, the pad nitride film 33A having the reduced surface thickness and the sidewall thickness remains, and the pad nitride film 33A is recessed in the shoulder portion of the first trench 34 (see reference numeral 'R').

The pull back process of the pad nitride layer uses a wet etching method, for example, a dip method using an etching solution. Phosphoric acid (H ₃ PO ₄ ) solution is used as an etching solution.

According to the above, the inlet of the first trench 34 is widened by the pull back process of the pad nitride film 33A. As such, when the inlet of the first trench 34 is widened, the aspect ratio of the first trench 34 is reduced to allow gap fill without voids in the subsequent trench gapfill process.

As shown in FIG. 3C, the insulating layer is deposited on the entire surface and then dry-etched to form the spacers 35. At this time, the spacer 35 is formed by depositing an oxide film and then dry etching. The spacer 35 may be formed to cover the sidewall of the first trench 34 and the sidewall of the pad nitride layer 33A. The spacer 35 has a thickness of 500 to 3000 mm 3.

As shown in FIG. 3d, an annealing process is performed in an oxygen atmosphere. By the annealing process, the damage generated during the dry etching described above can be removed, and the spacer 35 is densified.

In particular, as the annealing process is performed in an oxygen atmosphere, the bottom and sidewall surfaces of the first trench 34 may be oxidized. Accordingly, the sidewall oxide layer 36 may be grown on the bottom and sidewalls of the first trench 34. Here, as the bottom surface of the first trench 34 is directly exposed to the annealing process, the thickness grown on the bottom surface of the first trench 34 grows thicker than the thickness grown on the sidewall surface.

As shown in FIG. 3E, a polysilicon film 37 gap-filling the inside of the first trench 34 is formed. In order to form the gap fill inside of the first trench 34, the polysilicon film 37 is deposited on the entire surface until the first trench 34 is gap filled, and then the chemical mechanical and mechanical properties thereof are exposed until the pad nitride film 33A is exposed. Planarization is performed by a chemical mechanical polishing (CMP) process. Since the inlet of the first trench 34 is widened by the pull back process of the pad nitride film 33A when the polysilicon film 37 is deposited, a gap fill is possible without voids. Typically, the polysilicon film has an insulating property unless impurities are doped. When the polysilicon film 37 is used as a gap fill film, there is no difference in coefficient of thermal expansion with the semiconductor substrate 31, so that stress is not generated around the trench in a subsequent thermal process.

As shown in FIG. 3F, the second trench 38 is formed by performing a shallow trench isolation (STI) photo and an etching process. For example, after the pad nitride layer and the pad oxide layer are etched using the photoresist pattern (not shown) as an etch barrier, the second substrate 38 is formed by etching the semiconductor substrate using the pad nitride layer as the etch barrier. The second trench 38 is shallower than the first trench 34.

When the second trench 38 is formed, the polysilicon film 37 gap-filling the first trench 34 may be recessed to a predetermined depth, and a groove having a predetermined depth may be formed on the polysilicon film 37A. .

After the deep first trench 34 is gap-filled, a photo process for the STI is performed, thereby preventing the photoresist from remaining.

As shown in FIG. 3G, a sidewall oxidation process is performed to form a liner oxide layer 39 on the bottom and sidewalls of the second trench 38. At this time, since the polysilicon film 37A is exposed to the sidewall oxidation process, the liner oxide film 39 may be formed on the surface of the polysilicon film 37A. The liner oxide film 39 may be formed to a thickness of 100 to 3000 GPa.

Next, the gap fill oxide film 40 is formed on the entire surface until the second trench 38 is gap filled. The gapfill oxide film 40 may include a silicon oxide film (SiO ₂ ) -based or PSOG (Polysilasane Spin On Glass), such as a high density plasma oxide (High Density Plasma Oxide).

Subsequently, the chemical mechanical polishing process (CMP) is performed until the surface of the pad nitride film 33A is exposed to planarize the gap fill oxide film 40.

As shown in FIG. 3H, the pad nitride film 33A is removed.

Accordingly, the gap fill oxide film 40B gap fills the second trench 38, and the gap fill oxide film 40A also gap fills over the polysilicon film 37A.

As described above, the first trench 34 used as a trench for isolation between devices of the high voltage semiconductor device includes a sidewall oxide layer 36, a spacer 35, a liner oxide layer 39, and a gap fill oxide layer 40A. As a result, the polysilicon film 37A is surrounded by oxide films to form a structure located inside the first trench 34.

According to the second embodiment described above, by using the polysilicon film 37A as a gap fill material, it is possible to prevent the occurrence of a defect due to stress around the trench. In addition, since the polysilicon film 37A is not exposed to the outside by the gap fill oxide film 40A, the polysilicon film 37A may be prevented from being doped by a subsequent ion implantation process. In addition, a trench gap fill is possible without voids by the pull back process and the spacer.

3I illustrates a trench gapfill structure according to a second embodiment of the present invention.

Referring to FIG. 3I, in the deep first trench 34, the polysilicon film 37A is positioned inside the oxide film 300. Only the oxide layer 301 is present in the shallow second trench 38.

This is because the oxide film 300 includes all of the materials surrounding the polysilicon film 37A in FIG. 3H. That is, since the pad oxide film 32, the spacer 35, the sidewall oxide film 36, the liner oxide film 38, and the gap fill oxide film 40A of FIG. 3H are all oxide films, the polysilicon film 37A inside the oxide film 300 is formed. This structure is located.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1A to 1D are cross-sectional views illustrating a trench gap fill method of a semiconductor device according to the related art.

2A to 2H are cross-sectional views illustrating a trench gapfill method according to a first embodiment of the present invention.

FIG. 2I illustrates a trench gapfill structure according to a first embodiment of the present invention. FIG.

3A to 3H are cross-sectional views illustrating a trench gapfill method according to a second embodiment of the present invention.

3I illustrates a trench gapfill structure according to a first embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 pad oxide film

33A: pad nitride film 34: first trench

35 spacer 36 sidewall oxide film

37A: polysilicon film 38: second trench

39: Lysium oxide film 40A, 40B: Gap fill oxide film

Claims (16)

Etching the silicon substrate using the pad layer as an etch barrier to form a trench; Recessing the pad layer; Forming a spacer on sidewalls of the trench and sidewalls of the pad layer; Gap-filling the inside of the trench with a polysilicon layer; Recessing a surface of the polysilicon film; Forming a liner oxide film on a surface of the recessed polysilicon film; And, Gap-filling an oxide film on the liner oxide film Trench gapfill method of a semiconductor device comprising a. The method of claim 1, The trench gap fill method of the semiconductor device, wherein the recess of the pad layer is wet etching. The method of claim 2, The pad film includes a nitride film, and the nitride film is recessed using a phosphoric acid solution. The method of claim 1, Forming the spacers, A trench gap fill method of a semiconductor device formed by etching the entire surface after deposition of an oxide film. The method of claim 1, A trench gap fill method of a semiconductor device in which annealing is performed in an oxygen atmosphere after forming the spacer. The method of claim 1, The oxide film is a trench gap fill method of a semiconductor device comprising a silicon oxide film or PSOG. delete The method of claim 1, The silicon substrate is a silicon substrate doped with impurities, and the polysilicon film is an undoped polysilicon film not doped with impurities. Forming a first trench by etching one side of the silicon substrate using the pad layer as an etch barrier; Recessing the pad layer; Forming a spacer on sidewalls of the first trench and sidewalls of the pad layer; Forming a polysilicon film gap-filling the inside of the first trench; Recessing a portion of the polysilicon film gap-filled in the first trench while forming a second trench shallower than the first trench on the other side of the silicon substrate; And Forming an oxide layer gap-filling the first trench and the second trench Trench gapfill method of a semiconductor device comprising a. 10. The method of claim 9, The trench gap fill method of the semiconductor device, wherein the recess of the pad layer is wet etching. The method of claim 10, The pad film includes a nitride film, and the nitride film is recessed using a phosphoric acid solution. 10. The method of claim 9, Forming the spacers, A trench gap fill method of a semiconductor device formed by etching the entire surface after deposition of an oxide film. 10. The method of claim 9, A trench gap fill method of a semiconductor device in which annealing is performed in an oxygen atmosphere after forming the spacer. 10. The method of claim 9, The oxide film is a trench gap fill method of a semiconductor device comprising a silicon oxide film or PSOG. 10. The method of claim 9, And forming a liner oxide film on a surface of the recessed polysilicon film and a surface of the second trench before forming the oxide film. 10. The method of claim 9, The polysilicon film is a trench gap fill method of a semiconductor device comprising an undoped polysilicon film.

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