KR100493065B1 - Semiconductor device having trench gate type transistor and manufacturing method thereof - Google Patents

Abstract

In order to form a trench gate type transistor, a gate trench is first formed in a semiconductor substrate, and then a device isolation trench is formed, thereby forming a recess channel having an increased length near the bottom of the gate trench along the direction of extending the active region. Disclosed are a semiconductor device and a method of manufacturing the same, in which a silicon region does not remain between the device isolation film and the gate insulating film in a cross section along a direction perpendicular to the region extending direction, so that unnecessary channels are not formed. The semiconductor device according to the present invention has a first both inner side wall facing each other in an active region in a first direction orthogonal to the extending direction of the active region and a second both side facing each other in a second direction in which the active region extends. A plurality of gate trenches having inner walls are formed. The device isolation film is in direct contact with the gate insulating film at the entire length of the first inner side walls extending from the inlet to the bottom of the gate trench. A plurality of channel regions are positioned around the gate insulating layer along the second inner sidewalls and the bottom surfaces of the gate trenches.

Description

Semiconductor device having a trench gate transistor and a method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a trench gate transistor and a method for manufacturing the same.

As semiconductor memory devices such as DRAMs are highly integrated, memory cells are becoming more and more miniaturized. Accordingly, various efforts have been made to secure a predetermined cell capacitance in the miniaturized memory cell and to improve cell transistor characteristics. As memory cells become smaller, cell transistors of smaller sizes are required. In response to such miniaturization, many attempts have been made to control the impurity concentration in the diffusion layer in order to implement a cell transistor having no problem in terms of characteristics. However, as the length of the channel decreases, it is difficult to control the depth of the diffusion layer of the transistor through various heat treatment processes during the device fabrication process, and the short channel effect due to the reduction of the effective channel length and the decrease of the threshold voltage. ) Is remarkably generated, causing serious problems in the operation of the cell transistors.

As a method for solving such a problem, a trench gate type transistor has been proposed in which a trench is formed on a substrate surface and a gate electrode of a transistor is formed in the trench. In the trench gate type transistor, the gate electrode is formed in the trench to increase the effective channel length by increasing the distance between the source and the drain, thereby reducing the short channel effect.

In the prior art, an isolation region for defining an active region is first formed in a semiconductor substrate for fabricating a trench gate type transistor, and then a trench for forming a gate electrode is formed in the active region of the semiconductor substrate. (See US Pat. No. 6,476,444 and US Pat. No. 6,498,062.)

However, when forming the device isolation region first and then forming the gate electrode forming trench as in the prior art, there is a problem in that unwanted short channels are formed between the device isolation region and the gate electrode when the distance is short. have.

Referring to FIG. 1, the device isolation region 12 in contact with the active region 14 when the device isolation region 12 is formed by a shallow trench isolation (STI) process in the semiconductor substrate 10 made of silicon ( On the side wall 12a of 12), the inclined surface due to the inclined etching remains. In this state, when the trench 16 for forming the gate electrode 20 (hereinafter, referred to as the “gate trench 16”) is formed, the inclined surface due to the inclined etching is formed on the sidewall of the gate trench 16. Is formed. Therefore, when the distance between the device isolation region 12 and the gate electrode 20 is sufficiently close as shown in FIG. 1, after the completion of the transistor, the device isolation region 12 is separated from the device isolation region 12 in the semiconductor substrate 10. A narrow silicon region 18 remains between the gate electrode 20 by the inclined surfaces 12a and 16a. The silicon region 18 forms an unwanted channel between the device isolation region 12 and the gate electrode 20, and as a result, a sufficient threshold voltage cannot be secured in the cell transistor.

As an alternative to overcome the above problem, a method of controlling the inclination direction of the trench profile during the etching process for forming the gate trench or using wet etching may be considered, but in this case, between the device isolation region and the gate electrode The problem that the silicon region remains in the solution is not completely solved, so that not only the unwanted short channel is always present, but also adversely affects the reliability of the resulting transistor.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the prior art, and in a trench gate type transistor, a semiconductor device capable of fundamentally preventing unwanted channels from being formed around a gate electrode recessed in a semiconductor substrate. To provide.

Another object of the present invention is to provide a method of manufacturing a semiconductor device for forming a structure in which a trench gate transistor can fundamentally prevent the formation of unwanted channels around a gate electrode recessed in a semiconductor substrate.

In order to achieve the above object, the semiconductor device according to the present invention includes the first both inner sidewalls of the active region positioned in the cell array region of the semiconductor substrate and face each other in a first direction perpendicular to the extending direction of the active region. A plurality of gate trenches having second inner sidewalls facing each other along the second direction in which the region extends is formed. Gate insulating films are formed on inner walls of the gate trenches, respectively. A gate electrode is formed on the gate insulating layer, and the gate electrode includes a gate bottom filling the gate trench and a gate upper portion extending in a first direction on the semiconductor substrate to cross the active region. The device isolation layer is in direct contact with the gate insulating layer at the entire length of the first inner side walls extending from the inlet to the bottom of the gate trench. A plurality of sources / drains are formed in the semiconductor substrates on both sides of the gate electrode. A plurality of channel regions are positioned around the gate insulating layer along the second inner sidewalls and the bottom surfaces of the gate trenches in the semiconductor substrate.

A gate bottom of the gate electrode has a width defined by the device isolation layer in a length direction extending in the first direction. The gate bottom of the gate electrode has the largest width at its bottom when viewed in a cross section along the first direction.

In order to achieve the above another object, in the method of manufacturing a semiconductor device according to the present invention, a plurality of gate trenches extending in a first direction are formed in a semiconductor substrate. The sacrificial layer may be formed by filling the gate trenches with a predetermined material. A device isolation trench is formed in the semiconductor substrate to define a plurality of active regions extending in a second direction perpendicular to the first direction. An isolation material is formed in the isolation trench to form an isolation layer defining the active region. The sacrificial layer inside the gate trench is completely removed from the active region to expose the gate region. A gate insulating film is formed in the gate region. A gate electrode is formed on the gate insulating film. The gate region has the largest width at its bottom when viewed in a cross section along the first direction.

Preferably, if the semiconductor substrate is a silicon substrate, the predetermined material is composed of silicon nitride. Also preferably, the sacrificial layer has a planarized top surface covering the top surface of the semiconductor substrate.

The isolation trench is formed to have a deeper depth than the gate trench. In order to form the device isolation trench, first, a mask pattern covering the active region is formed on the sacrificial layer. Thereafter, the sacrificial film and the semiconductor substrate are etched by the anisotropic etching method using the mask pattern as an etching mask. In this case, the sacrificial film and the semiconductor substrate are etched by a single etching process using a first etching gas that provides an etching selectivity having an etching selectivity between the sacrificial film and the semiconductor substrate in a range of 1: 3 to 3: 1. do.

When the semiconductor substrate is a silicon substrate and the sacrificial layer is formed of a silicon nitride layer, a mixed gas of CF ₄ and CHF ₃ may be used as the first etching gas. At least one gas selected from Cl ₂ and HBr may be further added to the first etching gas.

In the method of manufacturing a semiconductor device according to the present invention, when the semiconductor substrate is a silicon substrate, the sacrificial layer may be made of SiGe. In this case, in order to form the sacrificial film, a SiGe layer is first formed on the semiconductor substrate to a thickness sufficient to fill the gate trench. Thereafter, a portion of the SiGe layer covering the upper surface of the semiconductor substrate is removed by a wet etching method to form the sacrificial layer filling the gate trench and to expose the upper surface of the semiconductor substrate.

In order to remove a portion of the SiGe layer covering the upper surface of the semiconductor substrate, NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ An etchant selected from the group consisting of O, and HF / H ₂ O ₂ / CH ₃ COOH is used. The sacrificial layer may be formed to have an upper surface recessed by a predetermined depth from an upper surface of the semiconductor substrate.

In addition, in the method of manufacturing a semiconductor device according to the present invention, after forming the gate trench using the first mask pattern formed on the semiconductor substrate as an etching mask, a SiGe layer is formed on the gate trench and the first mask pattern. It may be. In this case, in order to remove a portion of the SiGe layer covering the upper surface of the semiconductor substrate, first, the SiGe layer is polished by a chemical mechanical polishing (CMP) process until the upper surface of the first mask pattern is exposed, and then the necessary So that the sacrificial layer remains only in the gate trench according to NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, and HF / H ₂ O A part of the polished SiGe layer is removed using an etchant selected from the group consisting of ₂ / CH ₃ COOH.

Further, in order to form the device isolation trench, a second mask pattern covering the active region is formed on the top surface and the sacrificial layer of the semiconductor substrate, and the sacrificial layer is formed by a dry etching method using the second mask pattern as an etching mask. And etching the semiconductor substrate. Here, in the etching of the sacrificial film made of SiGe and the semiconductor substrate, a mixed gas containing Cl ₂ and HBr is used as an etching gas. The mixed gas may further include H ₂ gas.

In the step of exposing the gate region by removing the sacrificial film made of SiGe, NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, And a wet etching process using an etchant selected from the group consisting of HF / H ₂ O ₂ / CH ₃ COOH.

According to the present invention, in order to form a trench gate transistor, a gate trench is first formed in a semiconductor substrate, followed by an isolation trench. In the semiconductor device according to the present invention, a recess channel having an increased length near the bottom surface of the gate trench in the trench gate transistor may be normally formed in the extending direction of the active region. On the other hand, in the cross section along the direction orthogonal to the extending direction of the active region, no silicon region remains between the device isolation layer and the gate insulating layer, and thus, there is no fear of forming unnecessary channels other than the normal channel around the gate trench.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2, 3A, and 3B are diagrams for describing a configuration of a semiconductor device according to a preferred embodiment of the present invention. More specifically, FIG. 2 is a layout illustrating some components of a cell array region of a semiconductor device according to an exemplary embodiment of the present invention, FIG. 3A is a cross-sectional view taken along line IIIa-IIIa 'of FIG. 2, and FIG. 3B is IIIb of FIG. 2. Section IIIb '

2, 3A, and 3B, the semiconductor device according to the present invention includes a plurality of active regions 112 extending in the x direction in a straight type on the semiconductor substrate 100. The active region 112 is defined by an isolation layer 118 formed on the semiconductor substrate 100. The plurality of gate electrodes 150 extend in the y direction perpendicular to the extending direction of the active region 112.

The gate electrode 150 intersects the gate bottom 150a recessed into the semiconductor substrate 100 with the gate trench 120 filled therein, and intersects with the active region 112 on the semiconductor substrate 100. It includes a gate top 150b extending in the y direction. As can be seen in FIG. 3B, the width of the gate bottom 150a of the gate electrode 150 is defined by the device isolation layer 118 in a length direction extending along the y direction. In addition, the gate bottom 150a has the largest width Wg at its bottom when viewed in a cross section along the y direction.

The gate trench 120 extends in a direction orthogonal to an extension direction of the active region 112, that is, in an extension direction of the first inner side wall 120a and the active region 112 that face each other along a y direction. It has the 2nd both inner side wall 120b which mutually opposes along a direction.

A gate insulating layer 130 is formed between the semiconductor substrate 100 and the gate electrode 150. In the gate trench 120, the gate insulating layer 130 may extend from an upper surface of the semiconductor substrate 100, that is, from an inlet of the gate trench 120 to a bottom surface of the gate trench 120. The device isolation layer 118 is in contact with the entire length of 120a).

As can be seen in FIG. 3A, a plurality of sources / drains 180 are disposed in the semiconductor substrate 100 on both sides of the gate electrode 150 near the second inner sidewalls 120b of the gate trench 120. Formed. Accordingly, a plurality of channel regions are formed along the direction of the arrow A near the second inner side walls 120b of the gate trench 120 and the bottom of the gate trench 120. However, as shown in FIG. 3B, the gate insulating layer 130 has a bottom surface of the gate trench 120 from the inlet of the gate trench 120 in the first inner side wall 120a of the gate insulating layer 130. Since it is in contact with the device isolation layer 118 over its entire length, there is no fear that unnecessary channels are formed between the device isolation layer 118 and the gate insulating layer 130.

4A and 4B to 13A and 13B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention in the order of their processes. 4A, 5A, 13A, and 13A are views corresponding to the section IIIa-IIIa 'of FIG. 2, respectively, and FIGS. 4B, 5B, 13B, and 13B respectively show IIIB- of FIG. It is a figure corresponding to a IIIb 'line cross section.

First, referring to FIGS. 4A and 4B, a plurality of gate trenches having a predetermined depth and extending in the y direction (see FIG. 2) are etched by etching a semiconductor substrate 100 formed of a silicon substrate using an etching mask (not shown). 102 is formed. The gate trench 102 is formed in the shape of a groove extending in the y direction. In FIG. 4B, the area indicated by the dotted line represents the inside of the gate trench 102. A hard mask pattern such as a photoresist pattern or a silicon nitride layer may be used as an etching mask that may be used in an etching process for forming the gate trench 102. In this case, after removing the etching mask used, the semiconductor substrate 100 may be further etched by a dry etching method using O ₂ , CF ₄ gas, or the like, to round the profile of the gate trench 102.

Referring to FIGS. 5A and 5B, the surface of the semiconductor substrate 100 is oxidized by thermal oxidation in order to cure damage to the semiconductor substrate 100 during etching for forming the gate trench 102. Thereafter, a first material is deposited on the semiconductor substrate 100 on which the gate trench 102 is formed to completely fill the gate trench 102 and to cover the top surface of the semiconductor substrate 100 to a predetermined thickness. The film 104 is formed. The first sacrificial layer 104 may be formed of, for example, a silicon nitride layer. However, the present invention is not limited to the silicon nitride film as the material of the first sacrificial film 104, and when the first sacrificial film 104 is removed using a predetermined etching gas or an etchant after the formation of a subsequent device isolation film. Any film can be used as long as it can be removed with an excellent etching selectivity with respect to the oxide film constituting the device isolation film. The first sacrificial layer 104 is advantageously formed to have a flat top surface for subsequent photolithography processes.

6A and 6B, in order to define the active region 112 in the semiconductor substrate 100, first, a mask covering the active region 112 on the first sacrificial layer 104 using a photolithography process. Pattern 106 is formed. As the mask pattern 106, for example, a hard mask pattern such as a photoresist pattern or a silicon oxide film may be used.

7A and 7B, the first sacrificial layer 104 and the semiconductor substrate 100 are etched by the anisotropic etching method using the mask pattern 106 as an etching mask, and the device is formed on the semiconductor substrate 100. The isolation trench 110 is formed. A plurality of active regions 112 extending in the x direction in FIG. 2 are defined by the device isolation trench 110. The isolation trench 110 is formed to have a deeper depth than the gate trench 102.

As the isolation trench 110 is formed, the first sacrificial layer 104 remains on the active region 112 only on the semiconductor substrate 100. As shown in FIG. 7B, some of the inner walls of the isolation trench 110, that is, the inner wall constituting the sidewall of the isolation trench 110 when viewed in a cross section along the y direction in the arrangement of FIG. 2, are active. In the region 112, the first sacrificial layer 104 filling the inside of the gate trench 102 is exposed. On the other hand, as shown in Figure 7a, in the inner wall constituting the side wall of the isolation trench 110 in the cross section along the x direction in the arrangement of Figure 2 the first filling the inside of the gate trench (102) 1 The sacrificial film 104 is not exposed.

In etching the first sacrificial layer 104 and the semiconductor substrate 100, a single etching gas may be formed by using a first etching gas having a very small difference in etching selectivity between the first sacrificial layer 104 and the semiconductor substrate 100. The first sacrificial layer 104 and the semiconductor substrate 100 are simultaneously removed by an etching process. Preferably, as the first etching gas, an etching selectivity having an etching selectivity between the first sacrificial layer 104 and the semiconductor substrate 100 is in a range of 1: 3 to 3: 1. For example, when the semiconductor substrate 100 is made of silicon and the first sacrificial layer 104 is made of silicon nitride, a mixed gas of CF ₄ and CHF ₃ may be used as the first etching gas. If necessary, at least one gas selected from Cl 2 and HBr may be further added to the first etching gas.

8A and 8B, the mask pattern 106 is removed. Thereafter, the exposed portion of the semiconductor substrate 100 may be further etched in the device isolation trench 110 to have a rounded corner near the bottom surface of the device isolation trench 110 as necessary. At this time, for example, a second etching gas composed of a mixed gas of Cl ₂ and HBr is used.

Referring to FIGS. 9A and 9B, an isolation material 118 may be formed by filling an insulating material in the isolation trench 110 and planarization by chemical mechanical polishing (CMP) to define the active region 112. The insulating material constituting the device isolation film 118 is composed of an oxide film. In forming the device isolation film 118, a liner (not shown) made of a silicon nitride film may be formed near the inner wall of the device isolation trench 110.

10A and 10B, the first sacrificial layer 104 inside the gate trench 102 is completely removed from the active region 112, and thus the gate trench 102 existing in the active region 112 is removed. Expose the gate region 122 defined by. In order to remove the first sacrificial layer 104, for example, a wet etching method using phosphoric acid may be used.

The gate trench 102, which is exposed through the isolation layer 118 and constitutes the gate region 122, has the largest width Wt at its bottom surface as shown in FIG. 10B when viewed in the y-direction section of FIG. 1. Has

11A and 11B, the device isolation layer 118 is partially removed from the upper portion of the device isolation layer 118 by a wet etching method to expose the upper surface of the semiconductor substrate 100 exposed through the device isolation layer 118 and the device isolation layer 118. We match step with).

12A and 12B, a gate insulating layer 130 is formed on an inner wall of the gate trench 102 constituting the gate region 122 in the active region 112, and a conductive layer for forming a gate electrode thereon is formed thereon. 140). The conductive layer 140 may be formed of, for example, a conductive polysilicon film or a double film in which a conductive polysilicon film and a metal silicide film are sequentially stacked.

An insulating layer 142 formed of a silicon nitride layer is formed on the conductive layer 140, and a photoresist pattern 144 covering the gate region 122 is formed on the insulating layer. The insulating layer 142 is used as a hard mask when patterning the gate electrode and serves as a capping layer for protecting the gate electrode.

13A and 13B, the insulation layer 142 is etched using the photoresist pattern 144 as an etch mask to form an insulation layer pattern 142a, and then the insulation layer pattern 142a is an etch mask. The conductive layer 140 is etched to form the gate electrode 150. As described with reference to FIGS. 3A and 3B, the gate electrode 150 may include a gate bottom 150a recessed into the semiconductor substrate 100 while being filled in the gate trench 102, and the semiconductor substrate ( A gate top 150b extending in the y direction from the top of the substrate 100 and crossing the active region 112. In addition, the width of the gate bottom portion 150a of the gate electrode 150 is defined by the device isolation layer 118 in a length direction extending in the y direction, and the width of the gate bottom 150a of the gate electrode 150 is lowest at the bottom surface when viewed in a cross section along the y direction. It has a large width Wg.

Thereafter, an ion implantation process for forming the source / drain 180 on the semiconductor substrate 100 and an insulation film deposition and etch back process for forming the spacer 160 on the sidewall of the gate electrode 150 are performed. And a structure as shown in FIG. 3B.

14A and 14B to 21A and 21B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention in the order of their processes. Here, FIGS. 14A, 15A, ..., and 21A are views corresponding to the section IIIa-IIIa 'of FIG. 2, respectively, and FIGS. 14B, 15B, ..., 21B are IIIB- of FIG. 2, respectively. It is a figure corresponding to a IIIb 'line cross section. In describing the second embodiment, components corresponding to those in the first embodiment are denoted by the same reference numerals as in the first embodiment, and detailed description thereof is omitted.

The second embodiment has the same basic technical idea as forming the isolation trench for device isolation after first forming a gate trench in the semiconductor substrate as in the first embodiment, but the first sacrificial layer 104 and the semiconductor are the same. The present invention relates to a method for completely eliminating the possibility of occurrence of surface irregularities on the bottom of the isolation trench, which may be caused by the difference in etching rate between the substrate 100 and the substrate 100. This will be described in detail below.

14A and 14B, after the plurality of gate trenches 102 are formed in the semiconductor substrate 100 in the same manner as described with reference to FIGS. 4A and 4B, a second sacrificial layer is formed on the semiconductor substrate 100. The film 204 is formed to a thickness sufficient to fill the gate trench 102. The dry etching characteristic of the second sacrificial layer 204 is the same as that of silicon (Si) constituting the semiconductor substrate 100, and the wet etching characteristic thereof is different from that of Si constituting the semiconductor substrate 100. Materials are used that can provide good etch selectivity for Si to be selectively removed. Preferably, the second sacrificial layer 204 is made of SiGe. The SiGe film has an etching rate difference of 20% or less from the Si film in a dry etching process using an etching gas containing Br and Cl (see JVST A 9 (3), p768 (1991)), and contains Br and Cl. By adding a gas such as H ₂ to the etching gas, the dry etching rates of the SiGe film and the Si film can be controlled to the same level.

Referring to FIGS. 15A and 15B, a wet etching process may be performed on a portion of the second sacrificial layer 204 covering the upper surface of the semiconductor substrate 100 such that the second sacrificial layer 204 remains only in the gate trench 102. The upper surface of the semiconductor substrate 100 is exposed by removing the semiconductor layer 100. In the wet etching process, a first etchant having excellent SiGe etching selectivity with respect to Si may be used to selectively remove the second sacrificial layer 204 with respect to the semiconductor substrate 100. As the first etchant, for example, NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, or HF / H ₂ O ₂ / CH _An etchant such as ₃ COOH can be used. When the portion of the second sacrificial layer 204 on the upper surface of the semiconductor substrate 100 is removed by a wet etching process, as shown in FIG. 15A, the gate is formed by over-etching as shown in FIG. 15A. An upper surface of the second sacrificial layer 204 remaining in the trench 102 may be recessed by a predetermined depth from the upper surface of the semiconductor substrate 100.

16A and 16B, after the pad oxide film 212 and the silicon nitride film 214 are sequentially formed on the top surface of the semiconductor substrate 100 and the top surface of the second sacrificial layer 204, the silicon nitride film ( A photoresist pattern 216 is formed on the 214 to cover the active region 112 (see FIG. 2) of the semiconductor substrate 100.

17A and 17B, the silicon nitride film 214 is etched by an anisotropic etching method using the photoresist pattern 216 as an etching mask to form a mask pattern 214a, and the photoresist pattern 216. ) Is removed by an ashing and strip process.

18A and 18B, after the pad oxide layer 212 is removed using the mask pattern 214a as an etch mask, the semiconductor substrate 100 and the second sacrificial layer 204 are subsequently exposed. The device isolation trench 220 is formed in the semiconductor substrate 10 by etching by a dry etching method. Here, during the dry etching, the second sacrificial layer 204 filled in the gate trench 102 formed in the device isolation region of the semiconductor substrate 100 and the semiconductor substrate 100 around the substrate are removed at the same etching rate. Dry etching may be performed under such a condition that there is little difference in etching selectivity between the second sacrificial layer 204 and the semiconductor substrate 100. Preferably, a mixed gas of Cl ₂ and HBr is used as the etching gas in the dry etching, and H ₂ gas is added and used as necessary. As such, the device isolation trench 220 is formed by a dry etching process in which the etching rate of the second sacrificial layer 204 and the semiconductor substrate 100 has little difference between the second sacrificial layer 204 and the second sacrificial layer 204. And the possibility of surface irregularities occurring on the bottom surface of the isolation trench 220, which may be caused by the difference in the etching selectivity between the semiconductor substrate 100 and the semiconductor substrate 100, may be completely excluded.

In the semiconductor substrate 100, a plurality of active regions 112 extending in the x direction in FIG. 2 are defined by the device isolation trench 220. The isolation trench 220 is formed to have a deeper depth than the gate trench 102.

As the isolation trench 220 is formed, the second sacrificial layer 204 remains only in the active region 112 on the semiconductor substrate 100. As shown in FIG. 18B, a portion of the inner wall of the isolation trench 220, that is, the inner wall constituting the sidewall of the isolation trench 220 when viewed in a cross section along the y direction in the arrangement of FIG. 2 is active. In the region 112, the second sacrificial layer 204 filling the inside of the gate trench 102 is exposed. On the other hand, as shown in FIG. 18A, in the inner wall constituting the sidewall of the device isolation trench 220 when viewed in the cross section along the x direction in the arrangement of FIG. 2, the first filling the inside of the gate trench 102 is formed. The sacrificial layer 204 is not exposed.

Referring to FIGS. 19A and 19B, an isolation material 118 may be formed in the isolation trench 220 by filling an insulating material and planarization by a CMP method to define the active region 112. As described above, the insulating material constituting the device isolation film 118 is formed of an oxide film, and a liner (not shown) made of a silicon nitride film may be formed near the inner wall of the device isolation trench 220.

Referring to FIGS. 20A and 20B, the mask pattern 214a is completely removed by a wet etching process using phosphoric acid, and the pad oxide layer 204 exposed as a result is collected to allow the pad oxide layer 204 to be exposed. An upper surface of the semiconductor substrate 100 and the second sacrificial layer 204 are exposed. At this time, if necessary, the device isolation layer 118 is partially removed from the upper portion of the device isolation layer 118 by a wet etching method, and the upper surface of the semiconductor substrate 100 exposed through the device isolation layer 118 and the device isolation layer 118 are separated. Match the steps. Here, the gate trench 102 has the largest width Wt at the bottom thereof as shown in FIG. 20B when viewed in the y-direction cross section of FIG. 1.

21A and 21B, the second sacrificial layer 204 filling the inside of the gate trench 102 is completely removed from the active region 112, and thus the gate trench existing in the active region 112 is removed. The gate region 222 defined by 102 is exposed. In order to remove the second sacrificial layer 204, a wet etching method having a large etching selectivity of the second sacrificial layer 204 with respect to the semiconductor substrate 100 may be used. For example, when the second sacrificial layer 204 is made of SiGe, a second etchant having excellent SiGe etching selectivity with respect to Si constituting the semiconductor substrate 100 is used. As the second etchant, for example, NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, or HF / H ₂ O ₂ / CH _An etchant such as ₃ COOH can be used.

Thereafter, the transistor fabrication process as described with reference to FIGS. 12A and 12B and FIGS. 13A and 13B is performed to complete the device.

22 to 24 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention in the order of their processes. 22 to 24 are diagrams corresponding to the section IIIa-IIIa 'of FIG. 2, respectively. In describing the third embodiment, components corresponding to those in the first and second embodiments are denoted by the same reference numerals as in the first and second embodiments, and detailed description thereof. Description is omitted.

In the third embodiment, as in the first and second embodiments, the basic technical idea of forming the gate trench on the semiconductor substrate first and then forming the isolation trench for device isolation is the same. However, as described with reference to FIGS. 15A and 15B in the second exemplary embodiment, the semiconductor substrate 100 of the second sacrificial layer 204 remains so that the second sacrificial layer 204 remains only in the gate trench 102. It is generally similar to the second embodiment except that only the wet etching process is used to remove the portion on the upper surface, and the CMP process and the wet etching process are used. This will be described in more detail below.

Referring to FIG. 22, a plurality of gate trenches 102 are formed in the semiconductor substrate 100 using a mask pattern composed of a pad oxide film 302 and a silicon nitride film 303.

Referring to FIG. 23, while the pad oxide layer 302 and the silicon nitride layer 303 remain on the semiconductor substrate 100, the second sacrificial layer 204 may be formed on the semiconductor substrate 100 by the gate trench. 102) to a thickness sufficient to fill. As the constituent material of the second sacrificial film 204, it is preferable to use SiGe as described in the second embodiment.

Referring to FIG. 24, the second sacrificial layer 204 is polished by a CMP process until the top surface of the silicon nitride layer 303 is exposed, thereby removing the silicon nitride layer 303 of the second sacrificial layer 204. Remove the covering.

Thereafter, the first etchant having excellent SiGe etching selectivity with respect to Si so as to selectively remove the second sacrificial layer 204 with respect to the semiconductor substrate 100, that is, NH ₄ OH / H ₂ O ₂ / H ₂ The second sacrificial layer may be formed by a wet etching process using an etchant such as O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, or HF / H ₂ O ₂ / CH ₃ COOH. A portion of the 204 may be selectively removed to leave the second sacrificial layer 204 only inside the gate trench 102. Here, by adjusting the wet etching amount of the second sacrificial layer 204, the top surface of the second sacrificial layer 204 remaining in the gate trench 102 may be the same as or slightly above the top surface of the semiconductor substrate 100. Can be recessed to a lower height.

Thereafter, the silicon nitride film 303 and the pad oxide film 302 are removed, and a process according to the second embodiment as described with reference to FIGS. 16A and 16B to 21A and 21B is performed.

In the method of fabricating a semiconductor device according to the present invention, in forming a trench gate transistor, a gate trench is first formed in a semiconductor substrate, followed by an isolation trench for device isolation. In the trench gate type transistor of the semiconductor device according to the present invention formed by the above method, a recess channel having an increased length near the bottom of the gate trench may be normally formed in the extending direction of the active region. On the other hand, in the cross section along the direction orthogonal to the extending direction of the active region, since the gate insulating film is in contact with the device isolation film over the entire length from the inlet to the bottom of the gate trench, no silicon region remains between the device isolation film and the gate insulating film. Therefore, there is no fear of forming unnecessary channels other than the normal channel around the gate trench.

In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes by those skilled in the art within the spirit and scope of the present invention. This is possible.

1 is a cross-sectional view illustrating a problem of a structure of a semiconductor device and a method of manufacturing the same according to the prior art.

2 is a layout illustrating some components of a cell array region of a semiconductor device according to an exemplary embodiment of the present invention.

3A is a cross-sectional view taken along the line IIIa-IIIa 'of FIG. 2.

3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 2.

4A and 4B to 13A and 13B are cross-sectional views for describing a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, in accordance with a process sequence thereof. FIGS. 4A, 5A, 13A, and 13A. Are diagrams corresponding to the section IIIa-IIIa 'of FIG. 2, respectively, and FIGS. 4B, 5B, ..., and 13B are diagrams corresponding to the section IIIb-IIIb' of FIG.

14A and 14B to 21A and 21B are cross-sectional views for describing a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, according to a process sequence thereof. FIGS. 14A, 15A, ..., 21A Are diagrams corresponding to the section IIIa-IIIa 'of FIG. 2, respectively, and FIGS. 14B, 15B, ..., 21B are diagrams corresponding to the section IIIb-IIIb' of FIG.

22 to 24 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention according to a process sequence thereof.

<Explanation of symbols for the main parts of the drawings>

Reference Signs List 100: semiconductor substrate, 102: gate trench, 104: first sacrificial film, 106: mask pattern, 110: device isolation trench, 118: device isolation film, 120: gate trench, 120a: first both inner walls, 120b: second both sides Inner wall, 122: gate region, 130: gate insulating film, 140: conductive layer, 142: insulating film, 142a: insulating film pattern, 144: photoresist pattern, 150: gate electrode, 150a: gate bottom, 150b: gate top, 160: spacer 180: source / drain, 204: second sacrificial film, 212: pad oxide film, 214: silicon nitride film, 214a: mask pattern, 216: photoresist pattern, 220: device isolation trench, 302: pad oxide film, 303: silicon nitride film .

Claims (30)

A semiconductor substrate having an active region located in the cell array region, A plurality of gate trench inner walls each having a first inner side wall facing each other along a first direction perpendicular to the extending direction of the active region and a second inner side wall facing each other along a second direction in which the active region extends; A plurality of gate insulating films formed; A plurality of gate electrodes including a gate bottom portion filling the gate trench on the gate insulating layer, and a gate upper portion extending in a first direction on the semiconductor substrate to cross the active region; An isolation layer directly contacting the gate insulating layer at an entire length of the first inner sidewalls extending from the inlet to the bottom of the gate trench; A plurality of sources / drains formed in the semiconductor substrate at both sides of the gate electrode; And a plurality of channel regions positioned around the gate insulating layer along the second inner sidewalls and the bottom surfaces of the gate trenches in the semiconductor substrate. The method of claim 1, And a gate bottom portion of the gate electrode has a width defined by the device isolation film in a length direction extending in the first direction. The method of claim 1, And the gate bottom of the gate electrode has the largest width at its bottom when viewed in a cross section along the first direction. The method of claim 1, And the cell array region constitutes a DRAM device. Forming a plurality of gate trenches extending in the first direction in the semiconductor substrate, Forming a sacrificial film made of a predetermined material filling the plurality of gate trenches; Forming an isolation trench in the semiconductor substrate defining a plurality of active regions extending in a second direction perpendicular to the first direction; Forming an isolation layer filling the isolation region to define the active region by filling an insulating material in the isolation trench; Completely removing the sacrificial layer inside the gate trench in the active region to expose the gate region; Forming a gate insulating film in the gate region; Forming a gate electrode on the gate insulating film. The method of claim 5, The semiconductor substrate is a silicon substrate, and the sacrificial film is a semiconductor device manufacturing method, characterized in that made of silicon nitride. The method of claim 5, The sacrificial layer has a planarized top surface covering the top surface of the semiconductor substrate. The method of claim 5, The device isolation trench may be formed to have a deeper depth than the gate trench. The method of claim 7, wherein Forming the device isolation trench Forming a mask pattern covering the active region on the sacrificial layer; Etching the sacrificial layer and the semiconductor substrate by an anisotropic etching method using the mask pattern as an etching mask. The method of claim 9, The etching of the sacrificial film and the semiconductor substrate may be performed by a single etching process using a first etching gas that provides an etching selectivity with an etching selectivity between the sacrificial film and the semiconductor substrate in a range of 1: 3 to 3: 1. The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 10, The semiconductor substrate is a silicon substrate, the sacrificial film is a silicon nitride film, the first etching gas is a manufacturing method of a semiconductor device, characterized in that made of a mixed gas of CF ₄ and CHF ₃ . The method of claim 11, The first etching gas further comprises at least one gas selected from Cl ₂ and HBr. The method of claim 9, And etching the exposed portion of the semiconductor substrate using a second etching gas to form the device isolation trench having rounded corners near the bottom surface. The method of claim 13, The second etching gas is a manufacturing method of a semiconductor device, characterized in that consisting of a mixed gas of Cl ₂ and HBr. The method of claim 13, wherein the etching using the second etching gas is performed after removing the mask pattern. The method of claim 5, A method of manufacturing a semiconductor device, characterized in that to use a wet etching method to remove the sacrificial film. The method of claim 5, And after the device isolation trench is formed, the sacrificial layer filling the gate trench is exposed in a portion of an inner wall of the device isolation trench. The method of claim 5, And the gate region has the largest width at the bottom thereof when viewed in a cross section along the first direction. The method of claim 5, The semiconductor substrate is a silicon substrate, and the sacrificial film is a manufacturing method of a semiconductor device, characterized in that made of SiGe. The method of claim 19, Forming the sacrificial layer Forming a SiGe layer on the semiconductor substrate to a thickness sufficient to fill the gate trench; Removing a portion of the SiGe layer covering the top surface of the semiconductor substrate by a wet etching method to form the sacrificial layer filling the gate trench, and simultaneously exposing the top surface of the semiconductor substrate. Manufacturing method. The method of claim 20, Removing the portion of the SiGe layer covering the upper surface of the semiconductor substrate is NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, And an etching solution selected from the group consisting of HF / H ₂ O ₂ / CH ₃ COOH. The method of claim 20, And the sacrificial layer is formed to have an upper surface recessed from the upper surface of the semiconductor substrate by a predetermined depth. The method of claim 20, In order to form the gate trench, a first mask pattern formed on the semiconductor substrate is used as an etching mask. And the SiGe layer is formed on the gate trench and the first mask pattern. The method of claim 23, Removing the portion of the SiGe layer covering the upper surface of the semiconductor substrate is Polishing the SiGe layer by a chemical mechanical polishing (CMP) process until the top surface of the first mask pattern is exposed. The method of claim 24, NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, and HF / H ₂ O ₂ / so that the sacrificial layer remains only in the gate trench. And removing a part of the polished SiGe layer using an etchant selected from the group consisting of CH ₃ COOH. The method of claim 19, Forming the device isolation trench Forming a second mask pattern covering the active region on the top surface and the sacrificial layer of the semiconductor substrate; And etching the sacrificial layer and the semiconductor substrate by a dry etching method using the second mask pattern as an etching mask. The method of claim 26, And etching the sacrificial layer and the semiconductor substrate using a mixed gas including Cl ₂ and HBr as an etching gas. The method of claim 27, The mixed gas further comprises a H ₂ gas manufacturing method of a semiconductor device. The method of claim 29, The second mask pattern includes a silicon nitride film. The method of claim 5, Removing the sacrificial layer to expose the gate region may include NH ₄ OH / H ₂ O ₂ / H ₂ O, HF / HNO ₃ / H ₂ O, HF / H ₂ O ₂ / H ₂ O, and HF / H ₂ A method for manufacturing a semiconductor device, characterized by a wet etching process using an etchant selected from the group consisting of O ₂ / CH ₃ COOH.