KR100732269B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and its manufacturing method are provided to uniformly maintain a threshold voltage by forming an active region of a source/drain region lower than an active region of a gate lower portion. An isolation layer(130) is formed in a semiconductor substrate(110) and defines an active region. A recess channel region of SIO(Silicon-on-Insulator) structure is formed in the active region and adjoins a sidewall of the isolation layer. The recess channel region includes a gate dielectric(160) formed by using gas including O2, H2O, O3, and mixture thereof. A gate structure(190) is formed on an upper portion of the recess channel region of a gate region. A source/drain region(205) is formed on the semiconductor substrate which is etched between the gate structures.

Description

Semiconductor device and manufacturing method thereof {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is a layout of a semiconductor device according to the prior art.

2A to 2C and 3 are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art.

4 is a layout of a semiconductor device in accordance with an embodiment of the present invention.

5 and 7 are cross-sectional views of a semiconductor device in accordance with an embodiment of the present invention.

6A through 6J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

8 is a three-dimensional cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, by designing a semiconductor device to form a recess channel region including a silicon-on-insulator (SOI) structure, the short channel effect is increased by increasing the effective channel area. by designing the device so that the upper portion of the source / drain region is lower than the semiconductor substrate under the gate, so that the upper region of the SOI channel where the electric field is concentrated is kept away from the source / drain to maintain the threshold voltage uniformly. And a method for manufacturing the same.

In general, as the channel length of the cell transistor decreases, the ion concentration of the cell channel is increased to meet the threshold voltage of the cell transistor, and as a result, the electric field of the source / drain region is increased, thereby increasing the leakage current. Falls out. Therefore, the following semiconductor device structure has been proposed in order to increase the channel length of the cell transistor.

1 is a layout of a semiconductor device showing an active region 1 and a gate region 3 defined by a device isolation film 30 according to the prior art.

2A through 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art, and FIGS. 2A through 2C are cross-sectional views taken along line II ′ of FIG. 1.

Referring to FIG. 2A, a trench (not shown) defining a fin-type active region 20 by etching a semiconductor substrate 10 having a pad insulating film (not shown) with an element isolation mask (not shown). ). Next, after forming a device isolation insulating film (not shown) filling the trench, the device isolation film 30 is formed by planarizing etching of the device isolation insulating film until the pad insulating film is exposed. Thereafter, the pad insulating film is removed and the upper surface of the fin type active region 20 is exposed.

Referring to FIG. 2B, the device isolation layer 30 is removed by using a recess gate mask (not shown) defining the gate region 3 of FIG. 1 as an etch mask to remove the fin type active region 20 from the device isolation layer ( 30) Protrude upwards.

Referring to FIG. 2C, after the gate insulating layer 60 is formed on the protruding fin-type active region 20, the planarized fin is filled with the protruding fin-type active region 20 in the gate region 3 of FIG. 1. The gate electrode 70 and the gate hard mask layer pattern 80 are formed on the gate electrode 70 and the gate hard mask layer pattern 80 to fill the sidewalls and the upper channel region of the fin type active region 20. The gate structure 90 formed of a stacked structure of () is formed.

3 is a cross-sectional view of a semiconductor device according to the prior art.

Referring to FIG. 3, when a voltage equal to or higher than a threshold voltage is applied to a gate, an inversion layer IL and a depletion layer DR are formed on a semiconductor substrate under the gate insulating layer 60.

However, according to the above-described method for manufacturing a semiconductor device, by etching the device isolation film to form a protruding fin type active region, the fin type active region protruding by a subsequent cleaning process including hydrofluoric acid (HF) inevitably causes loss. do. Accordingly, there is a problem in that device fabrication is difficult due to an increase in CD and an increase in difficulty of gate patterning.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and in particular, by designing a semiconductor device to form a recess channel region including a silicon-on-insulator (SOI) structure, an effective channel area is increased to short channel effects. By designing the device so that the upper portion of the source / drain region is lower than the semiconductor substrate under the gate, the upper region of the SOI channel where the electric field is concentrated is kept away from the source / drain, so that the threshold voltage is uniform. The present invention provides a sustainable semiconductor device and a method of manufacturing the same.

The present invention is to achieve the above object, the semiconductor device according to the present invention,
An isolation layer formed in the semiconductor substrate and defining an active region;
A silicon-on-insulator (SOI) structure is formed in the active region and includes a gate insulating layer formed in contact with a sidewall of the device isolation layer and formed using a gas including 0 ₂ , H ₂ O, O _3, and a combination thereof. A set channel region;
A gate structure formed over the recess channel region of the gate region;

And a source / drain region formed on the semiconductor substrate etched between the gate structures by a predetermined thickness.

Moreover, the manufacturing method of the semiconductor element which concerns on this invention is

(a) forming an isolation layer defining an active region in the semiconductor substrate including the pad insulating film, and (b) etching the pad insulating film with the recess gate mask to expose the pad insulating film to expose the semiconductor substrate in the recess region. Forming a spacer, and (c) forming a spacer on the sidewalls of the pad insulating film pattern, and (d) etching the semiconductor substrate exposed to the lower portion of the recess region using the spacer and the pad insulating film pattern by an etching mask to a predetermined thickness. Forming a semiconductor substrate, (e) removing the spacer and pad insulating film patterns to expose the semiconductor substrate, and (f) forming a top surface of the exposed semiconductor substrate including the recess 0 ₂ , H ₂ O, O _3. Forming a gate insulating film using a gas comprising a combination thereof; and (g) a planarized gate conductive layer and a gate hard mask filling a recess over the entire surface. Forming a gate structure by forming a gate hard mask layer and a gate conductive layer using the gate mask as an etching mask, and (i) etching a semiconductor substrate between the gate structures to a predetermined thickness; And forming a source / drain region on the etched semiconductor substrate by performing an impurity ion implantation process.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

4 is a layout of a semiconductor device illustrating an active region 101 and a gate region 103 defined by an isolation layer 130, according to an exemplary embodiment.

5 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention, FIG. 5 (i) is a cross-sectional view taken along line II ′ of FIG. 4, and FIG. 5 (ii) is a cross-sectional view taken along line II-II ′ of FIG. 4. It is a cross section.

Referring to FIG. 5, a recess channel region (not shown) is formed by etching a semiconductor substrate 110 having a predetermined thickness and positioned in an active region defined by the device isolation layer 130. In the longitudinal direction of the gate region 103 of 4, a silicon-on-insulator (SOI) structure is formed. In addition, a gate structure 190 including a stacked structure of the gate electrode 170 and the gate hard mask layer pattern 180 is formed on the recess channel region of the gate region 103 of FIG. 4. In addition, a source / drain region 205 is formed in the semiconductor substrate 110 etched between the gate structures 190 so that the upper portion of the source / drain region 205 is disposed on the semiconductor substrate 110 under the gate structure 190. Is located lower. Meanwhile, the gate spacer 195 is formed on the sidewall of the gate structure 190. The etched depth of the semiconductor substrate 110 in the recess channel region is 50 to 500 nm, and the etched depth of the semiconductor substrate 110 in the source / drain region 205 is 10 to 200 nm. Accordingly, the semiconductor device according to the present invention can improve the short channel effect by forming a recess channel region including an SOI structure in contact with the device isolation layer, and keep the gate under which the electric field is concentrated away from the source / drain region 205. The threshold voltage of the semiconductor device can be easily controlled by locating it.

7 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure, and illustrates a recess channel region under the gate structure 190 in detail.

Referring to FIG. 7, the recess channel region includes an upper channel region L1, a sidewall channel region L2 including a silicon-on-insulator (SOI) structure, and a lower channel region L2. In this case, when a voltage having a threshold voltage or more is applied to the gate, an inversion layer IL and a depletion layer DR are formed on the semiconductor substrate 110 under the gate insulating layer 160. In this case, the sidewall channel region L2 including the SOI structure between the device isolation layer 130 and the gate electrode 170 is converted into a complete depletion layer, which is excellent in the short channel effect.

8 is a three-dimensional cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

Referring to FIG. 8, the source / drain regions 205 are formed on the semiconductor substrate 110 etched to a predetermined thickness so that the upper channel region L1 where the electric field by the gate is concentrated is located away from the source / drain regions 205. do. Therefore, the semiconductor device according to the present invention can easily control the threshold voltage.

6A to 6J are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 6A (i) to 6J (i) are cross-sectional views taken along line II ′ of FIG. 5, and FIG. ii) to 6j (ii) are sectional views along II-II 'of FIG.

Referring to FIG. 6A, a pad nitride film 115, a pad oxide film 113, and a semiconductor substrate 110 having a predetermined thickness are used as a device isolation mask using a semiconductor substrate 110 on which a pad oxide film 113 and a pad nitride film 115 are formed. To form a trench (not shown). Next, after forming an isolation layer (not shown) for filling the trench, the device isolation layer 130 is formed by planarization by the CMP method until the pad nitride layer 115 is exposed. Here, it is preferable that the insulating film for element isolation is a silicon oxide film.

Referring to FIG. 6B, the pad nitride layer 115 and the pad oxide layer 113 are etched using a recess gate mask (not shown) defining the gate region 103 of FIG. 4 as an etch mask. A stack structure of the pad oxide film pattern 113a and the pad nitride film pattern 115a exposing the semiconductor substrate 110 is formed.

6C and 6D, the first insulating layer 140 is formed on the entire surface. Next, the spacer 145 is formed on sidewalls of the pad nitride layer pattern 115a and the pad oxide layer pattern 113a by etching the first insulating layer 140. Here, the first insulating layer 140 is formed of a silicon nitride film, a silicon oxide film, a polysilicon layer or a combination thereof, and SiH ₄ , O ₂ , Si (OC ₂ H ₅ ) ₄ , SiH ₂ Cl ₂ , NH ₃ , N It is preferable to form by CVD method using a source gas containing ₂ , He or a combination thereof. In addition, the etching process for forming the spacer 145 is preferably performed by a plasma etching method using a gas including C _x F _y H _z , O ₂ , HCl, or a combination thereof. The thickness of the spacer 145 is preferably 1 to 50 nm.

6E and 6F, the recess 150 is formed by etching a predetermined thickness of the semiconductor substrate 110 exposed under the recess region using the spacer 145 and the pad nitride layer pattern 115a as an etch mask. Next, the semiconductor substrate 110 including the recess 150 is exposed by removing the spacer 145, the pad nitride layer pattern 115a, and the pad oxide layer pattern 113a. Here, the etching process for forming the recess 150 is preferably performed by a plasma etching method, the etched thickness of the semiconductor substrate 110 in the recess 150 is preferably 50 to 500nm. In addition, the exposed surface of the semiconductor substrate 110 may be cleaned using a solution containing hydrofluoric acid (HF).

Referring to FIG. 6G, after forming the gate insulating layer 160 on the exposed semiconductor substrate 110 including the recess 150, the planarized lower gate conductive layer filling the recess 150 (not shown) ). Next, an upper gate conductive layer (not shown) and a gate hard mask layer (not shown) are formed on the lower gate conductive layer. Subsequently, the gate hard mask layer, the upper gate conductive layer, and the lower gate conductive layer are patterned using a gate mask (not shown) as an etch mask to form the gate structure 190 of the gate electrode 170 and the gate hard mask layer pattern 180. Form. Here, the gate insulating layer 160 is O ₂ , H ₂ O, O ₃ or these It is preferable to form in the thickness of 1-10 nm using the gas containing a combination. In addition, the lower gate conductive layer is preferably formed of a polysilicon layer doped with an impurity containing phosphorus (P) or boron (B). In this case, the doped polysilicon layer is formed by implanting impurity ions into the polysilicon layer which is not doped with impurities, or using an impurity source gas including silicon (Si) source gas and phosphorus (P) or boron (B). Can be formed. The upper gate conductive layer may be formed of a titanium (Ti) layer, a titanium nitride (TiN) film, a tungsten (W) layer, an aluminum (Al) layer, a copper (Cu) layer, a tungsten silicide (WSix) layer, or a combination thereof. It is desirable to.

Referring to FIG. 6H, the semiconductor substrate 110 between the gate structures 190 is etched to form an etched active region 193, and then an ion implantation process is performed on the etched active region 193. / Drain region (not shown) is formed. In this case, an additional gate insulating layer (not shown) may be formed on the surface of the etched active region 193 before the ion implantation process on the etched active region 193. Here, the additional gate insulating film is formed to a thickness of 1 to 10 nm of a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a silicon nitride film or a combination thereof. Meanwhile, the etched thickness of the semiconductor substrate 110 between the gate structures 190 is preferably 10 to 200 nm.

6I and 6J, after forming a second insulating film (not shown) on the entire surface, the second insulating film is etched to form gate spacers 195 on sidewalls of the gate structure 190. Next, a landing plug (not shown) is formed between the gate structures 190 including the gate spacers 195. Here, the landing plug is in contact with the source / drain region 205.

Subsequent processes perform general transistor manufacturing processes such as bit line contact and bit line formation, capacitor contact and capacitor formation, metal wiring contact and metal wiring formation to complete a semiconductor device.

As described above, a semiconductor device and a method of manufacturing the same according to the present invention are designed to form a recess channel region including a silicon-on-insulator (SOI) structure, thereby making it more suitable than a conventional planar or recess transistor. There is an advantage that a large operating current can be obtained. In addition, the SOI structural characteristics may improve threshold voltage reduction, body effect, and gate on / off characteristics due to drain voltage.

In addition, by designing the device so that the active region of the source / drain region is lower than the active region under the gate, there is an advantage of maintaining the threshold voltage uniformly by keeping the SOI channel upper region where the electric field is concentrated away from the source / drain. .

In addition, the semiconductor device according to the present invention has expandability to sufficiently secure a channel area even with a reduction in design rules.

In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (20)

An isolation layer formed in the semiconductor substrate and defining an active region; A silicon-on-insulator (SOI) structure is formed in the active region and includes a gate insulating layer formed in contact with a sidewall of the device isolation layer and formed using a gas including 0 ₂ , H ₂ O, O _3, and a combination thereof. A set channel region; A gate structure formed over the recess channel region of the gate region; Source / drain regions formed on the semiconductor substrate with a predetermined thickness etched between the gate structures A semiconductor device comprising a. The method of claim 1, And the etched depth of the semiconductor substrate in the recess channel region is 50 to 500 nm. The method of claim 1, And an etched depth of the semiconductor substrate in the source / drain region is 10 to 200 nm. (a) forming a device isolation film defining an active region on a semiconductor substrate having a pad insulating film; (b) etching the pad insulating layer with a recess gate mask to form a pad insulating layer pattern exposing the semiconductor substrate in the recess region; (c) forming spacers on sidewalls of the pad insulating layer pattern; (d) forming a recess by etching a thickness of the semiconductor substrate exposed under the recess region using the spacer and the pad insulating layer pattern as an etching mask; (e) exposing the semiconductor substrate by removing the spacers and the pad insulating layer pattern; (f) forming a gate insulating film using a gas including 0 ₂ , H ₂ O, O _3, and a combination thereof on top of the exposed semiconductor substrate including the recess; (g) forming a planarized gate conductive layer and a gate hard mask layer filling the recess over the entire surface; (h) patterning the gate hard mask layer and the gate conductive layer using a gate mask as an etch mask to form a gate structure; And (i) etching the semiconductor substrate between the gate structures by a predetermined thickness, and then forming a source / drain region in the etched semiconductor substrate by performing an impurity ion implantation process Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein Step (c) is (c-1) forming an insulating film on the entire surface; And (c-2) etching the insulating film to form spacers on sidewalls of the pad insulating film pattern Method for manufacturing a semiconductor device comprising a. The method of claim 5, And the insulating film is formed of a silicon nitride film, a silicon oxide film, a polysilicon layer, or a combination thereof. The method of claim 6, The insulating film is formed by a CVD method using a source gas including SiH ₄ , O ₂ , N ₂ O, Si (OC ₂ H ₅ ) ₄ , SiH ₂ Cl ₂ , NH ₃ , N ₂ , He, and a combination thereof. The manufacturing method of the semiconductor element characterized by the above-mentioned. The method of claim 5, The etching process for forming the spacer of the step (c-2) is manufactured by a semiconductor etching method using a plasma etching method using a gas containing C _x F _y H _z , O ₂ , HCl and combinations thereof Way. The method of claim 5, The thickness of the spacer is a method of manufacturing a semiconductor device, characterized in that 1 to 50nm. The method of claim 4, wherein The etched thickness of the semiconductor substrate for forming the recess is a method of manufacturing a semiconductor device, characterized in that 50 to 500nm. The method of claim 4, wherein Before the step (f), further comprising the step of cleaning the surface of the exposed semiconductor substrate using a solution containing hydrofluoric acid (HF). The method of claim 4, wherein The gate insulating film of the step (f) is a semiconductor device manufacturing method, characterized in that formed to a thickness of 1 to 10nm. The method of claim 4, wherein Step (g) (g-1) forming a planarized lower gate conductive layer filling the recess over the entire surface; (g-2) forming an upper gate conductive layer on the lower gate conductive layer; And (g-3) forming a gate hard mask layer on the upper gate conductive layer Method of manufacturing a semiconductor device comprising a. The method of claim 13, The lower gate conductive layer is formed of a polysilicon layer doped with an impurity containing phosphorus (P) or boron (B). The method of claim 14, Step (g-1) is Forming a planarized impurity-free polysilicon layer filling the recess over the entire surface; And Implanting impurity ions containing phosphorus (P) or boron (B) into the polysilicon layer Method of manufacturing a semiconductor device comprising a. The method of claim 14, Step (g-1) is A planarized impurity doped polysilicon layer is formed over the entire surface, and the doped polysilicon layer comprises a silicon (Si) source gas and an impurity (P) or boron (B). A method of manufacturing a semiconductor device comprising the step of forming using a source gas. The method of claim 13, The gate upper conductive layer is any one selected from a titanium (Ti) layer, a titanium nitride (TiN) film, a tungsten (W) layer, an aluminum (Al) layer, a copper (Cu) layer, a tungsten silicide (WSix) layer, and a combination thereof. Method for manufacturing a semiconductor device, characterized in that formed in one. The method of claim 4, wherein Step (i) is (i-1) etching the semiconductor substrate between the gate structures by a predetermined thickness; (i-2) forming a gate insulating film on the etched semiconductor substrate; And (i-3) forming a source / drain region on the etched semiconductor substrate by performing an ion implantation process Method of manufacturing a semiconductor device comprising a. The method of claim 18, In (i-1), the etched thickness of the semiconductor substrate is a method of manufacturing a semiconductor device, characterized in that 10 to 200nm. The method of claim 18, The gate insulating film of step (i-2) is formed of any one selected from silicon oxide film, hafnium oxide film, aluminum oxide film, zirconium oxide film, silicon nitride film and combinations thereof.

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