KR20050083305A - Method for manufacturing fin field effect transistor - Google Patents

Abstract

The present invention discloses a method for manufacturing a fin field effect transistor (fin FET) that can maximize the performance of the device. A method of manufacturing a fin field effect transistor according to the present invention includes the steps of forming a mask film having a predetermined shape on a semiconductor substrate; Etching the semiconductor silicon substrate to a predetermined depth by using the mask layer as an etching mask to form a fin active region protruding from the semiconductor substrate; Forming an isolation layer over the entire surface of the silicon substrate to cover the fin active region and the mask layer, and removing and planarizing the isolation layer to expose the mask layer; Forming a first trench having a depth the same as or similar to that of the mask layer by removing the device isolation layer so that the sidewall of the mask layer is selectively exposed by crossing the fin active region at least once over the fin active region; Forming spacers on sidewalls of the first trenches; Forming a second trench by removing the device isolation layer to a predetermined depth by using the spacer and mask layer as an etching mask; Forming a gate electrode through a gate insulating layer in the gate region of the fin active region exposed by the second trench; And forming an impurity region by ion implanting conductive impurities into the source / drain regions of the fin active region exposed by the gate electrode, thereby improving the performance of the manufactured device.

Description

Method for manufacturing fin field effect transistor

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a fin field effect transistor having a fin active region protruding from a silicon substrate.

Recently, with the rapid development of the information and communication field and the popularization of information media such as computers, semiconductor devices are also rapidly developing. In addition, various methods have been researched and developed in order to maximize the device performance while reducing the feature size of individual devices formed on a substrate in accordance with the tendency of high integration of semiconductor devices in terms of their functions. Among these methods, the integration of devices based on silicon semiconductor technology can be improved. Among them, CMOS technology, which is a design or configuration of a field effect transistor (FET), is most competitive. However, scaling down of general field effect transistors due to high integration results in deterioration of device performance or reliability. Therefore, in order to facilitate the integration of such a field effect transistor, a fin-like fin field effect transistor generally resembling a fish's dorsal so that the body of the transistor has a vertical structure is hereinafter A fin field effect transistor) has been proposed.

On the other hand, planar field effect transistors using a conventional single crystal silicon substrate as a channel are very sensitive to process conditions as the gate electrode is scaled down to less than 500 microseconds, which makes it difficult to control device characteristics during the manufacturing process. There is a difficulty. Moreover, near 300 microns of channel length, the device's performance is still insufficient for practical circuitry. For example, the 300 Å field effect transistor developed by Intel has a gate electrode having a length of about 300 Å, but the current-to-current voltage (I-V) characteristic is not superior to that of a conventional field effect transistor having a channel of about 500 이상의 or more. In addition, since the area occupied by one field effect transistor element is not reduced compared to the conventional one due to the spacer region formed on the sidewall of the gate electrode which is not scaled down, there is little room for improvement in the degree of integration. Accordingly, in relation to the method of forming a three-dimensional device such as the fin field effect transistor, representative three-dimensional device formation methods include a fully depleted lean-channel TrAnsistor (DELTA) structure and a gate all around (GAA) structure. Among them, a metal oxide semiconductor field effect transistor (MOSFET) having a DELTA structure is described in US Patent No. 4,996,574 and the like. In such a DELTA structure, the fin active region for forming the channel is formed to protrude vertically with a predetermined width. In addition, the gate electrode is formed to surround the vertically protruding channel portion. Thus, the height of the protruding portion constitutes the width of the channel, and the width of the protruding portion becomes the channel layer thickness. In the channel formed as described above, since both surfaces of the protruding portion can be used, the width of the channel can be doubled. Therefore, in a conventional planar transistor, it is possible to prevent the channel width from decreasing as the device region is reduced and the narrow channel effect from occurring as the channel width is reduced. In addition, when the width of the protruding portion is reduced, the depletion layers of the channels formed on both surfaces can be overlapped with each other (fully depleted), and therefore, the channel conductivity is increased. For example, in the dual-gate fin field effect transistor, gate electrodes are provided on the upper and lower sides (bottom and upper side) or left and right sides (left and right side) of the channel through which current flows, thereby greatly improving the control characteristics of the channel by the gate electrode. When the control characteristics of the channel by the gate are large, the leakage current between the source and the drain can be greatly improved as compared with the conventional single gate device, and thus, the drain induced barrier lowering (DIBL) characteristic can be greatly improved. In addition, gates exist on both sides of the channel to dynamically change the threshold voltage of the device, which greatly improves the on-off characteristics of the channel compared to the conventional single gate structure and suppresses short channel effects. have.

However, the manufacturing method of the pin field effect transistor of the prior art has the following problems.

In the related art, a method of manufacturing a fin field effect transistor is a process of exposing the fin active region through a series of etching processes from a device isolation layer or an interlayer insulating layer that separates and protects a plurality of fin active regions protruding from the silicon substrate by a dry etching method. In this case, since the surface of the fin active region is damaged, the performance of the device is inferior.

An object of the present invention for solving the above problems is to manufacture a fin field effect transistor that can maximize the performance of the device by reducing or preventing damage to the fin active region exposed from the device isolation film or interlayer insulating film by the etching process To provide a way.

According to an aspect of the present invention for achieving some of the above technical problems, a method of manufacturing a fin field effect transistor, comprising: forming a mask film having a predetermined shape on a semiconductor substrate; Etching the semiconductor silicon substrate to a predetermined depth by using the mask layer as an etching mask to form a fin active region protruding from the semiconductor substrate; Forming an isolation layer over the entire surface of the silicon substrate to cover the fin active region and the mask layer, and removing and planarizing the isolation layer to expose the mask layer; Forming a first trench having a depth the same as or similar to that of the mask layer by removing the device isolation layer so that the sidewall of the mask layer is selectively exposed by crossing the fin active region at least once over the fin active region; Forming spacers on sidewalls of the first trenches; Forming a second trench by removing the device isolation layer to a predetermined depth by using the spacer and mask layer as an etching mask; Forming a gate electrode through a gate insulating layer in the gate region of the fin active region exposed by the second trench; And forming an impurity region by ion implanting conductive impurities into the source / drain regions of the fin active region exposed by the gate electrode.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions have been emphasized for clarity, and may be present in direct contact with other layers or semiconductor substrates or between them when a layer is described as being on another layer or semiconductor substrate. There may be three layers.

1 is a plan view schematically showing a fin field effect transistor according to the present invention.

As shown in FIG. 1, the fin field effect transistor according to the present invention includes a fin active region 100 protruding from a silicon substrate (110 in FIG. 2A) and arranged in one direction, and intersects the fin active region 100. And a gate line 102 to be formed. The fin active region 100 may include a source region S and a drain region D on both sides of the gate region G crossing the gate line 102. Here, when the pin field effect transistor according to the present invention is used as an element for controlling input and output of a memory device such as a DRAM (Dynamic Random Access Memory device, DRAM), the gate line 102 is connected to the cell capacitor (cell capacitor) A word line for inputting and outputting a gate signal for controlling input and output of data or charge applied thereto becomes a word line. Although not shown, a bit line intersecting the word line is formed in a direction parallel to the source / the fin active region 100, and a cell capacitor in which data or charge is stored in the upper or lower portion of the transistor through the transistor. Is formed. In addition, the fin field effect transistor is formed in the cell region 200 in which the fin active region 100 is formed, and the periphery of the periphery of the cell region to input / output data signals and control signals to the word lines and bit lines. In the peripheral region 300, a planar MOS field effect transistor is formed.

A method of manufacturing the fin field effect transistor according to the present invention configured as described above is as follows.

2A-2H are cross-sectional views taken along the lines I-I 'and II-II' of FIG. 1 to show the order of fabricating the fin field effect transistor of FIG.

As shown in FIG. 2A, a hard mask film 104 having a predetermined thickness is formed on the silicon substrate 110 by chemical vapor deposition, and the hard mask film is formed by using a conventional photolithography process. Pattern 104. The hard mask layer 104 may be formed of a silicon nitride layer or a silicon oxynitride layer. When the hard mask layer 104 is formed of the silicon oxynitride layer, an anti-reflection layer is formed on the silicon oxynitride layer and then the photolithography is performed. Patterned into the process. Although not illustrated, an etch stop layer having a predetermined thickness may be further formed between the silicon substrate 110 and the hard mask layer 104 by using a silicon oxide layer, and the profile may be improved when the hard mask layer is removed. For example, the etch stop layer is formed on the silicon substrate 110 to have a thickness of about 500 GPa or less, and the hard mask film 104 is formed to have a thickness of about 2000 GPa or less. In addition, in the photolithography process, the hard mask layer 104 may be patterned by using a dry etching method. The reaction gas used in the dry etching method may be larger than that of the etch stop layer or the silicon substrate 110. A reaction gas with an excellent etching rate of the hard mask film 104 is used.

As shown in FIG. 2B, the etch stop layer and the silicon substrate 110 are etched to a predetermined depth by using the hard mask layer 104 as an etch mask to form a lower portion of the first hard mask layer 104. A fin active region 100 having a predetermined height is formed from a surface of the lower layer of the silicon substrate 110. The etching of the silicon substrate 110 is performed by a dry etching method having excellent vertical etching characteristics, and the fin active region 100 having a predetermined height is removed by removing the silicon substrate 110 having a predetermined depth for a predetermined time. It is made of a time etching method performed to protrude from the silicon substrate 110. In this case, since the silicon substrate 110 is removed to a predetermined depth from the surface so that the fin active region 100 protrudes, the silicon substrate 110 is based on the lower portion of the silicon substrate 110. Is defined. In this case, the fin active region 100 is formed to have a height of about 1500 kPa to about 5000 kPa from the surface of the silicon substrate 110.

As shown in FIG. 2C, a liner layer 120 is formed by stacking a silicon oxide film and a silicon nitride film by thermal oxidation or chemical vapor deposition on the entire surface of the silicon substrate 110 on which the fin active region 100 is formed. And a silicon oxide film on the entire surface of the silicon substrate 110 on which the liner layer 120 is formed, and by using a chemical vapor deposition method, a Sallow Trench Insulator (STI) 106 or an interlayer dielectric layer. : ILD), and the device isolation layer 106 is removed and planarized by chemical mechanical polishing (CMP) to expose the first hard mask layer 104. Here, the liner layer 120 may later be a sidewall of the fin active region 100 adjacent to the gate line 102 when the device isolation layer 106 is removed to form the gate electrode 116 of FIG. 2H. Serves to protect the For example, the liner layer 120 is formed such that the silicon oxide layer or the silicon nitride layer has a thickness of about 300 GPa to 500 GPa or less. In addition, the device isolation layer 106 covers the entire surface of the fin active region 100 and the device isolation layer 106 formed between the plurality of fin active regions 100 has a height of the fin active region 100. It is formed to a thickness of about 3000 kPa to about 8000 kPa so as to be higher, and the hard mask film 104 is formed to be exposed and flattened by the chemical mechanical polishing method.

As illustrated in FIG. 2D, the device isolation layer 106 may be removed to cross the fin active region 100 at least once using a conventional photolithography process, and may have the same thickness as that of the hard mask layer 104. Form a first trench 108 or first groove having a similar depth. Here, the first trench 108 or the first groove defines the gate electrode 116 of FIG. 2H and the gate line 102. In addition, the first trench 108 or the first groove is formed by a time etching method for etching the device isolation layer 106 made of silicon oxide for a predetermined time using a dry etching method.

As shown in FIG. 2E, a silicon nitride film or polysilicon is formed on the entire surface of the silicon substrate on which the first trench is formed, and the device isolation layer 106 and the hard mask film 104 are exposed by a dry etching method. The polysilicon or silicon nitride layer is removed to form a first spacer 112 on sidewalls of the first trench 108 or the first groove.

The first spacer 112 may include a gate region G selectively exposed by the device isolation layer 106 as well as the sidewalls of the first trench 108 or the first groove formed in the device isolation layer 106. Is also formed on the sidewalls of the upper hard mask layer 104 of the fin active region 100. In this case, the first spacer 112 is formed in the groove such as the sidewalls of the first trench 108 or the first groove to have excellent step coverage in forming the polysilicon or silicon nitride film. The polysilicon or silicon nitride layer may be formed thicker than the planar surface, and even if the insulating layer is removed from the planar surface by using the perpendicularity and anisotropy of the dry etching, a part of the sidewall of the first trench 108 or the first groove may be removed. It is formed by remaining without being removed.

As illustrated in FIG. 2F, the device isolation layer may be formed by a self-aligned dry etching method using the first spacer 112, the device isolation layer 106, and the hard mask layer 104 as an etching mask. 106 is removed to a predetermined depth to form a second trench 114 or a second groove. Here, the depth of the second trench 114 or the second groove may be adjusted by time etching the device isolation layer 106 using a reaction gas having a constant etching rate with respect to the device isolation layer 106. Can be.

In this case, when the second trench 114 or the second groove is formed using the dry etching, the device isolation layer 106 may be selectively removed by the dry etching reaction gas, but the fin active region 100 may be removed. Is vertically protected by the hard mask film 104. In addition, the liner layer 120 formed along the sidewalls of the fin active region 100 may protect the sidewalls of the fin active region 100 from the reaction gas during the dry etching. For example, the second trench 114 or the second groove is formed to have a depth of about 200 μs to 800 μs from the upper surface of the fin active region 100 to the bottom.

Therefore, in the method of manufacturing the fin field effect transistor according to the present invention, the liner layer formed on the sidewall of the fin active region 100 during dry etching to selectively remove the device isolation layer 106 to expose the fin active region 100. Since the sidewall of the fin active region 100 may be protected from the dry etching reaction gas using the 120, damage to the fin active region 100 may be reduced or prevented.

As shown in FIG. 2G, wet etching or forming the first hard mask layer 104 formed on the fin active region 100 and the liner layer 120 formed on the sidewalls of the fin active region 100 is performed. Remove by dry etching. For example, the hard mask layer 104 and the liner layer 120 may be removed using a phosphate solution or a phosphate reaction gas having an excellent etching rate with respect to the silicon nitride layer during wet etching or dry etching.

Accordingly, the method of manufacturing the fin field effect transistor according to the present invention selectively removes the device isolation layer 106 by using the first spacer 108 and the hard mask layer 104 as an etch mask to form the second trench 114 or the like. A second groove may be formed, and the first spacer 108, the hard mask layer 108, and the liner layer 120 may be removed to selectively expose sidewalls of the fin active region 100 of the gate region G. Therefore, the gate region G of the fin active region 100 may be exposed in three dimensions.

As shown in FIG. 2H, a gate insulating film is formed by a thermal oxidation method using a silicon oxide film over the entire surface of the fin active region 100 selectively exposed by the device isolation layer 106. Here, the gate insulating film is formed to have a thickness of about 200 GPa or less.

In addition, a polysilicon or metal material including conductive impurities is formed on the entire surface of the fin active region 100 having the gate insulating layer formed thereon and the device isolation layer 106 having the trench 114 or the groove formed therein, and a conventional photolithography method. The polysilicon or metal material is patterned to form the gate electrode 116.

Thereafter, the first impurity region is formed by ion implanting the first conductive impurity into the source region S and the drain region D using the gate electrode 116 as an ion implantation mask. For example, the conductive impurity implanted into the first impurity region is ion implanted to have a concentration of about 1 × 10 ¹² atoms / cm ² to about 1 × 10 ¹⁴ atoms / cm ² at about 50 KeV energy or less. An insulating film, such as a silicon oxide film, is formed on the entire surface of the silicon substrate 110, and the insulating film is anisotropically removed to form a second spacer on the sidewall of the gate electrode 116, and the gate electrode 116 is formed. And a second impurity region is formed by ion implanting conductive impurities into the source / drain regions S and D using the second spacer as an ion implantation mask. The conductive impurity ion-implanted into the second impurity region is the same or similar conductive impurity as the conductive impurity ion-implanted into the first impurity region, and is about 1 × 10 ¹⁶ atoms / cm ² to about 1 at an energy of about 30 eV or less. Ion implantation is carried out at a concentration of about 10 ¹⁷ atoms / cm ² .

As a result, the method of manufacturing the fin field effect transistor according to the present invention includes a first spacer 108 formed on the sidewall of the hard mask layer 104 in the process of exposing the fin active region 100 from the device isolation layer 106; The liner layer 120 protecting the fin active region 100 may be used to reduce or prevent damage to sidewalls of the fin active region 100, thereby maximizing device performance.

In addition, the description of the above embodiment is merely given by way of example with reference to the drawings in order to provide a more thorough understanding of the present invention, it should not be construed as limiting the present invention. In addition, various changes and modifications are possible to those skilled in the art without departing from the basic principles of the present invention.

As described above, the method of manufacturing the fin field effect transistor of the present invention includes a first spacer formed on the sidewall of the hard mask layer and an liner layer protecting the fin active region in an etching process of exposing the fin active region from the device isolation layer. In this case, damage to the fin active region sidewalls can be reduced or prevented, thereby maximizing device performance.

1 is a plan view schematically showing the structure of a fin field effect transistor according to the present invention.

2A-2H are cross-sectional views taken along the lines I-I 'and II-II' of FIG. 2 to show the order of fabricating the fin field effect transistor of FIG.

* Description of the symbols for the main parts of the drawings

100: fin active region 102: gate line

104: hard mask film 106: device isolation film

108: first trench 110: silicon substrate

112: first spacer 114: second trench

116: gate electrode 118: gate insulating film

200: cell area 300: peripheral area

Claims (4)

In the manufacturing method of the fin field effect transistor, Forming a mask film having a predetermined shape on the semiconductor substrate; Etching the semiconductor silicon substrate to a predetermined depth by using the mask layer as an etching mask to form a fin active region protruding from the semiconductor substrate; Forming an isolation layer over the entire surface of the silicon substrate to cover the fin active region and the mask layer, and removing and planarizing the isolation layer to expose the mask layer; Forming a first trench having a depth the same as or similar to that of the mask layer by removing the device isolation layer so that the sidewall of the mask layer is selectively exposed by crossing the fin active region at least once over the fin active region; Forming spacers on sidewalls of the first trenches; Forming a second trench by removing the device isolation layer to a predetermined depth by using the spacer and mask layer as an etching mask; Forming a gate electrode through a gate insulating layer in the gate region of the fin active region exposed by the second trench; And And implanting conductive impurities into the source / drain regions of the fin active region exposed by the gate electrode to form an impurity region. According to claim 1, And forming a liner film between the fin active region and the mask film. The method of claim 2, And the liner layer is formed by sequentially stacking a silicon oxide layer and a silicon nitride layer. According to claim 1, The first trench or the second trench is formed using a time etching method.