CN113471138B - Method for preparing semiconductor substrate and semiconductor device - Google Patents
Method for preparing semiconductor substrate and semiconductor device Download PDFInfo
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- CN113471138B CN113471138B CN202110757022.2A CN202110757022A CN113471138B CN 113471138 B CN113471138 B CN 113471138B CN 202110757022 A CN202110757022 A CN 202110757022A CN 113471138 B CN113471138 B CN 113471138B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 133
- 239000000758 substrate Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000002955 isolation Methods 0.000 claims abstract description 138
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 4
- 238000002360 preparation method Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 5
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H01L27/088—
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- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a preparation method of a semiconductor substrate and a semiconductor device. The method comprises the following steps: forming an active region and an isolation trench on a semiconductor substrate; depositing insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer; removing the isolation layer to enable the surface of the isolation structure to be level with the surface of the active region; etching the active region to a preset depth to form an active groove; and epitaxially growing a semiconductor substrate in the active groove, so that the surface of the active region is flush with the surface of the isolation structure. The preparation method of the invention can eliminate the stress of the isolation structure and the isolation groove, ensure that the active region is not damaged by the stress to generate defects or cracks, simultaneously avoid influencing the mobility of carriers in the channel of the device to influence the performance of the device, and improve the yield of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for manufacturing a semiconductor substrate and a semiconductor device.
Background
In the process of manufacturing a semiconductor device, an active region and an isolation region between the active regions are generally formed in a semiconductor substrate, the isolation region is generally formed by a shallow trench isolation process to form a shallow trench, and an insulating material is filled in the shallow trench to form a Shallow Trench Isolation (STI).
Since the material of the shallow trench isolation is different from the material of the semiconductor substrate, the thermal expansion coefficients of the material and the material are different, and therefore, certain stress is generated when the STI process is performed. The stress typically damages the structure of the semiconductor substrate, such as defects or cracks formed in the active region, or affects the mobility of carriers in the channel of the device, and thus the device performance, and the like, affecting the yield of the semiconductor device.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention provides a preparation method of a semiconductor substrate, which can eliminate stress after an isolation structure is formed, avoid damage of the semiconductor substrate and improve the yield of the semiconductor substrate.
Another object of the present invention is to provide a semiconductor device capable of eliminating stress of an isolation structure to the semiconductor device, improving performance of the semiconductor device, and improving yield of the semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor substrate, comprising: forming an active region and an isolation trench on a semiconductor substrate; depositing insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer; removing the isolation layer to enable the surface of the isolation structure to be flush with the surface of the active area; etching the active region to a preset depth to form an active groove; and epitaxially growing the semiconductor substrate in the active groove so that the surface of the active region is flush with the surface of the isolation structure.
According to an exemplary embodiment of the present invention, the preset depth is 0.03 to 0.3 μm.
According to an exemplary embodiment of the invention, the preset depth is 0.15 μm.
According to an exemplary embodiment of the present invention, the insulating oxide is silicon oxide or silicon oxynitride.
According to an exemplary embodiment of the present invention, the insulating oxide is deposited using at least one of atomic layer deposition, chemical vapor deposition, and spin coating.
According to an exemplary embodiment of the present invention, the thickness of the isolation layer is 8 to 15nm.
According to an exemplary embodiment of the present invention, the process used to remove the isolation layer is chemical mechanical polishing or wet etching.
According to an exemplary embodiment of the present invention, the epitaxial growth is performed by molecular beam epitaxy or ultra-high vacuum chemical vapor deposition.
According to an exemplary embodiment of the present invention, the semiconductor substrate is monocrystalline silicon, and the monocrystalline silicon is epitaxially grown in the active recess.
According to an exemplary embodiment of the present invention, the process used to etch the active region to the predetermined depth is wet etching or dry etching.
According to an exemplary embodiment of the present invention, the forming the active region and the isolation trench on the semiconductor substrate includes: forming a photoresist mask on the semiconductor substrate; etching the semiconductor substrate by using the photoresist mask to form the isolation trench and the active region; and removing the photoresist mask above the active region.
According to an exemplary embodiment of the invention, the method further comprises: and depositing an ion implantation barrier layer on the surface of the semiconductor substrate after epitaxial growth.
According to an exemplary embodiment of the present invention, the thickness of the ion implantation blocking layer is 8 to 12nm.
According to an exemplary embodiment of the present invention, the material of the ion implantation blocking layer is silicon dioxide or silicon nitride.
According to another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate and a functional device located in the semiconductor substrate, wherein the semiconductor substrate is prepared by the method of any of the above embodiments.
According to the technical scheme, the invention has at least one of the following advantages and positive effects:
after the isolation structure is formed on the semiconductor substrate, the active area between the isolation structures is etched to a preset depth to form an active groove, so that the stress of the isolation structure and the stress of the isolation groove can be removed, the semiconductor substrate is epitaxially grown in the active groove, and the epitaxially grown semiconductor substrate is adapted to the isolation structure, therefore, the stress can be eliminated or reduced to the greatest extent in the semiconductor substrate forming the isolation structure, the active area is prevented from being damaged by the stress to generate defects or cracks, the mobility of carriers in a channel of a device is prevented from being influenced to influence the performance of the device, and the like, and the yield of the semiconductor device is improved.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a flowchart illustrating a method of manufacturing a semiconductor substrate according to an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram illustrating the formation of active regions and isolation trenches on a semiconductor substrate using photolithography in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of an active region and an isolation trench formed after photoresist removal according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic illustration of the deposition of an insulating oxide on a semiconductor substrate according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic view of a semiconductor substrate with an isolation layer removed according to an exemplary embodiment of the present invention;
fig. 6 is a schematic view of a semiconductor substrate with active recesses formed in accordance with an exemplary embodiment of the present invention;
fig. 7 is a schematic diagram of an epitaxially grown semiconductor substrate in an active recess according to an exemplary embodiment of the present invention;
fig. 8 is a schematic structural view of a semiconductor substrate on which an ion implantation barrier layer is formed according to an exemplary embodiment of the present invention;
fig. 9 is a one-dimensional stress distribution diagram of a channel surface of a semiconductor device according to an exemplary embodiment of the present invention.
Reference numerals illustrate:
1. a semiconductor substrate; 2. an active region; 3. an isolation trench; 4. an isolation structure; 5. an isolation layer; 6. an active recess; 7. a photoresist mask; 8. an ion implantation barrier layer; d. the depth is preset.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration various exemplary structures in which aspects of the disclosure may be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Moreover, although the terms "over," "between," "within," and the like may be used in this specification to describe various exemplary features and elements of the disclosure, these terms are used herein for convenience only, e.g., in accordance with the directions of examples in the drawings. Nothing in this specification should be construed as requiring a particular three-dimensional orientation of structures to fall within the scope of this disclosure. Furthermore, the terms "first," "second," and the like in the claims are used merely as labels, and are not intended to limit the numerals of their objects.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
In addition, in the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
The semiconductor base comprises a semiconductor substrate 1, and isolation structures 4 (shallow trench isolation STI) are typically formed on the semiconductor substrate 1, with active regions 2 being provided between the isolation structures 4, i.e. adjacent active regions 2 are insulated by the isolation structures 4 (see fig. 5).
The shallow trench isolation is generally made of an insulating material such as silicon dioxide, silicon oxynitride, etc., and the semiconductor substrate 1 for forming the shallow trench may be made of silicon, silicon carbide, silicon on insulator, silicon germanium on insulator, etc. Before forming the isolation structure 4, an isolation trench 3 (shallow trench) is formed on the semiconductor substrate 1, and then an insulating material is deposited into the isolation trench 3 to form the isolation structure 4. However, since the material of the isolation structure 4 is different from the material of the semiconductor substrate 1, the thermal expansion coefficient and the lattice constant of the two are different, and a certain stress exists between the isolation structure 4 and the isolation trench 3 during the deposition of the isolation structure 4.
The stress can be divided into two types, namely tensile stress and compressive stress. In the process of manufacturing a semiconductor device, some functional devices, such as a MOS (field effect transistor) device, are formed in a semiconductor substrate, and a conductive channel is formed between source and drain regions of the MOS device. For different types of MOS devices, the stress can influence the stress distribution of the surface of a conductive channel of the MOS device, so that adverse effects can be generated on the performance of the semiconductor device, for example, for PMOS, the tensile stress can influence and reduce the mobility of hole carriers, so as to reduce the on-state current of the device; for NMOS, compressive stress can affect and reduce mobility of electron carriers, thereby reducing on-state current of the device. Meanwhile, the stress also affects the structure of the semiconductor substrate, and when the stress is large enough, the active region 2 of the semiconductor substrate 1 may crack and deform, which eventually leads to performance degradation of the semiconductor device and affects the yield of the semiconductor device. Therefore, in integrated circuit structure design, it is necessary to effectively remove the effect of the stress.
In order to effectively remove the stress, according to an aspect of the present invention, a method of manufacturing a semiconductor substrate is provided. As shown in fig. 1 to 8, wherein fig. 1 shows a flowchart of a method of manufacturing a semiconductor substrate of the present invention; fig. 2 to 8 show schematic cross-sectional views of a semiconductor substrate at various steps of a method for manufacturing the semiconductor substrate. As shown in fig. 1, the method for preparing a semiconductor substrate of the present invention includes:
step S200: an active region 2 and an isolation trench 3 are formed on a semiconductor substrate 1.
Step S400: an insulating oxide is deposited in the isolation trench 3 and on the surface of the active region 2, wherein the insulating oxide located in the isolation trench 3 is an isolation structure 4 and the insulating oxide located on the surface of the isolation structure 4 and on the surface of the active region 2 is an isolation layer 5.
Step S600: the spacer layer 5 is removed so that the surface of the spacer structure 4 is flush with the surface of the active region 2.
Step S800: the active region 2 is etched to a predetermined depth d to form an active recess 6.
Step S1000: the semiconductor substrate 1 is epitaxially grown in the active recess 6 such that the surface of the active region 2 is flush with the surface of the isolation structure 4.
According to the preparation method of the semiconductor substrate, after the isolation structures 4 are formed, the active areas 2 between the isolation structures 4 are etched to a preset depth d to form the active grooves 6, the semiconductor substrate part affected by the stress between the isolation structures 4 and the isolation grooves 3 can be removed, and the semiconductor substrate 1 is further subjected to epitaxial growth in the active grooves 6, so that the semiconductor substrate 1 subjected to epitaxial growth is suitable for the isolation structures 4, and therefore, in the semiconductor substrate 1 for forming the isolation structures 4, the stress can be eliminated or reduced to the greatest extent, the defect or crack caused by the fact that the active areas 2 are not damaged by the stress is avoided, meanwhile, the electrical performance of a device is prevented from being affected by the stress, and the yield of the semiconductor device is improved.
The method for producing the semiconductor substrate of the present invention is described in detail below.
Step S200: an active region 2 and an isolation trench 3 are formed on a semiconductor substrate 1.
A semiconductor substrate 1 is provided, isolation trenches 3 are etched on the semiconductor substrate 1, and active regions 2 are formed in regions between the isolation trenches 3 on the semiconductor substrate 1.
As shown in fig. 2, forming an active region 2 and an isolation trench 3 on a semiconductor substrate 1 specifically includes: a photoresist mask 7 is formed on the semiconductor substrate 1, the semiconductor substrate 1 is etched using the photoresist mask 7, and after the etching is completed, an active region 2 is formed on the semiconductor substrate 1 at a portion masked by the photoresist mask 7, and an unmasked portion is etched as an isolation trench 3. Thereafter, as shown in fig. 3, the photoresist mask 7 located over the active region 2 is removed, forming the semiconductor substrate 1 having the isolation trench 3.
Wherein the etching of the semiconductor substrate 1 to form the isolation trenches 3 may employ a dry etching or wet etching process. The dry etching may be plasma etching, and the etching gas used in the plasma process may be chlorine gas, and the etching degree may be controlled by controlling the amount of the etching gas. The wet etching can use concentrated sulfuric acid and hydrogen peroxide as etchants, and the etching degree can be controlled by adjusting the concentration of the etchants, so that the depth of the isolation trench 3 can be controlled. In some embodiments, the depth of the isolation trench 3 may be 0.2 to 0.3 μm, for example, 0.22 μm, 0.25 μm or 0.28 μm, and the person skilled in the art may control the etching degree according to the actual situation, and thus the depth of the isolation trench 3 is not particularly limited herein.
Step S400: an insulating oxide is deposited in the isolation trench 3 and on the surface of the active region 2, wherein the insulating oxide located in the isolation trench 3 is an isolation structure 4 and the insulating oxide located on the surface of the isolation structure 4 and on the surface of the active region 2 is an isolation layer 5.
Wherein the insulating oxide may be silicon oxide (SiO 2 ) Or silicon oxynitride (SiON), the process of depositing the insulating oxide may be at least one of atomic layer deposition, chemical vapor deposition, and spin coating. In one embodiment, both atomic layer deposition and spin-on processes may be used for deposition to make the insulating oxide deposition more uniform.
As shown in fig. 4, the isolation structure 4 is a Shallow Trench Isolation (STI) located in the isolation trench 3, and in order to enable the isolation structure 4 to fill the isolation trench 3, the isolation oxide is deposited on top of the isolation trench 3, and then the isolation layer 5 is formed on top of the active region 2 and the isolation structure 4. The thickness of the spacer layer 5 may be 8 to 15nm, specifically, 10nm, 12nm or 13nm, and is not particularly limited herein.
Step S600: the spacer layer 5 is removed so that the surface of the spacer structure 4 is flush with the surface of the active region 2.
As shown in fig. 5, the isolation layer 5 is removed, exposing the active region 2 and the isolation structure 4, forming the semiconductor substrate 1 with the isolation structure 4. The process used to remove the isolation layer 5 may be Chemical Mechanical Polishing (CMP) or wet etching. When chemical mechanical polishing is used, the semiconductor substrate 1 may be used as a stop layer, and in one embodiment, the semiconductor substrate 1 is silicon, and silicon is used as a stop layer, so as to control polishing to stop in time and form a smooth surface in the active region 2. When wet etching is adopted, the ratio of the etching solution can be adjusted to adjust the selection ratio of the semiconductor substrate 1 and the isolation structure 4 for etching, and the isolation layer 5 is removed.
Step S800: the active region 2 is etched to a predetermined depth d to form an active recess 6.
As shown in fig. 6, after the isolation layer 5 is removed from the semiconductor substrate 1, the active region 2 is etched. The etching process may employ wet etching or dry etching. The etching gas used in the dry etching may be chlorine gas, and the etching degree can be controlled by controlling the amount and concentration of the etching gas. The wet etching can use concentrated sulfuric acid and hydrogen peroxide as the etchant, and the etchant has extremely high selectivity to the semiconductor substrate 1 by controlling the proportion and concentration of the etchant, for example, the semiconductor substrate 1 adopts silicon, so that the etchant can be adjusted to have high selectivity to silicon, and the active region 2 can be etched rapidly during etching.
As shown in fig. 6, the preset depth d is the depth of the active recess 6, and may be 0.03 to 0.3 μm, for example, 0.05 μm, 0.1 μm, 0.15 μm, 0.2 μm, 0.25 μm. In one embodiment, the predetermined depth d is preferably 0.15 μm. The value of the preset depth d may be set according to the depth of the isolation trench 3 and the stress condition, for example, the stress exists mainly on the bottom of the isolation trench 3 through analysis, the depth of the active recess 6 is smaller than the depth of the isolation trench 3, and if the stress exists on the bottom of the isolation trench 3 or the whole isolation trench 3, the depth of the active recess 6 formed by the etched active region 2 may be controlled to be the same as the depth of the isolation trench 3. I.e. the preset depth d is not greater than the depth of the isolation trenches 3.
Step S1000: the semiconductor substrate 1 is epitaxially grown in the active recess 6 such that the surface of the active region 2 is flush with the surface of the isolation structure 4.
After forming the active recess 6 with a preset depth d, this part is stress relieved, as the material of the semiconductor substrate 1 here has been separated from the isolation structure 4, as shown in fig. 7. Then, the semiconductor substrate 1 is epitaxially grown in the active groove 6, and during the epitaxial growth process, the material of the semiconductor substrate 1 is suitable for the growth of the isolation structure 4, and no new stress is generated, so that no stress or only minimal stress exists at the contact interface between the semiconductor substrate 1 and the isolation structure 4 formed after epitaxial growth, the active region 2 is ensured not to be damaged by the stress to generate defects or cracks, and the isolation structure 4 and the isolation groove 3 are prevented from generating gaps. In addition, the epitaxial growth process is controlled so that the surface of the active region 2 is flush with the surface of the isolation structure 4, thus forming the stress-relieved semiconductor substrate 1 having the isolation structure 4.
The process adopted by the epitaxial growth can be molecular beam epitaxy or ultrahigh vacuum chemical vapor deposition. In some embodiments, the material of the semiconductor substrate 1 may be selected to be monocrystalline silicon, and the monocrystalline silicon is epitaxially grown in the active groove 6, that is, homoepitaxial growth is adopted, so that uniformity of the semiconductor substrate 1 can be ensured, new stress is avoided, and stability of the semiconductor substrate 1 is improved.
The specific parameters of the epitaxial growth process can be adjusted by those skilled in the art according to practical situations, and will not be described herein.
In some embodiments, as shown in fig. 8, the method for preparing a semiconductor substrate according to the embodiment of the present invention further includes: an ion implantation barrier layer 8 is deposited on the surface of the epitaxially grown semiconductor substrate 1.
The ion implantation barrier layer 8 is an insulating dielectric layer to be able to block ion implantation in a subsequent process. In some embodiments, the thickness of the ion implantation barrier layer 8 may be 8 to 12nm, for example, 9nm, 10nm or 11nm, and those skilled in the art may adjust according to the process conditions and practical situations, and is not particularly limited herein. The material of the ion implantation barrier layer 8 may be silicon dioxide or silicon nitride, and the deposition process may be atomic layer deposition or chemical vapor deposition.
In summary, in the method for preparing a semiconductor substrate of the present invention, after forming the isolation structures 4 in the semiconductor substrate 1, the active grooves 6 are formed by etching the active regions 2 between the isolation structures 4 to a predetermined depth d, so that the stress of the isolation structures 4 and the isolation grooves 3 can be removed, and further, the semiconductor substrate 1 is epitaxially grown in the active grooves 6, so that the epitaxially grown semiconductor substrate 1 is adapted to the isolation structures 4, therefore, in the semiconductor substrate 1 where the isolation structures 4 are formed, the stress can be eliminated or reduced to the greatest extent, the electrical performance of the device is not affected by the existence of the stress in the active regions 2, and meanwhile, the gap between the isolation structures 4 and the isolation grooves 3 is avoided, and the yield of the semiconductor device is improved.
According to another aspect of the present invention, embodiments provide a semiconductor device including a semiconductor substrate and a functional device, such as a MOS device, formed in the semiconductor substrate. The semiconductor substrate is prepared by the method described in any of the above embodiments, and will not be described herein.
As shown in fig. 9, a one-dimensional stress distribution diagram of a conductive channel surface at the bottom of a functional device in a semiconductor device is shown, and the abscissa in fig. 9 represents the distance from the channel center of the functional device formed on a semiconductor substrate to the left and right side isolation structures, the channel center being located at X of 0 μm, and the ordinate representing the stress value. As can be seen from fig. 9, in the semiconductor substrate manufactured by the method of the present invention, since the stress between the isolation structure and the semiconductor substrate is eliminated or greatly weakened, the stress on the channel surface of the semiconductor device finally formed on the substrate is greatly improved compared with the prior art, and the stress on the channel surface is greatly reduced, the stability of the semiconductor device of the embodiment of the present invention is improved, and the yield of the finished product is also greatly improved.
It should be understood that the invention is not limited in its application to the details of construction and the arrangement of components set forth in the specification. The invention is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are intended to fall within the scope of the present invention. It should be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for carrying out the invention and will enable those skilled in the art to make and use the invention.
Claims (15)
1. A method of manufacturing a semiconductor substrate, comprising:
forming an active region and an isolation trench on a semiconductor substrate;
depositing insulating oxide in the isolation trench and on the surface of the active region, wherein the insulating oxide in the isolation trench is an isolation structure, and the insulating oxide on the surface of the isolation structure and the surface of the active region is an isolation layer;
removing the isolation layer to enable the surface of the isolation structure to be flush with the surface of the active area;
etching the active region to a preset depth to form an active groove;
and epitaxially growing the semiconductor substrate in the active groove so that the surface of the active region is flush with the surface of the isolation structure.
2. The method of claim 1, wherein the predetermined depth is 0.03-0.3 μm.
3. The method of claim 2, wherein the predetermined depth is 0.15 μm.
4. The method of claim 1, wherein the insulating oxide is silicon oxide or silicon oxynitride.
5. The method of claim 1, wherein the process used to deposit the insulating oxide is at least one of atomic layer deposition, chemical vapor deposition, and spin-on.
6. The method of claim 1, wherein the thickness of the isolation layer is 8-15 nm.
7. The method of claim 1, wherein the process used to remove the isolation layer is chemical mechanical polishing or wet etching.
8. The method of claim 1, wherein the epitaxial growth is performed by molecular beam epitaxy or ultra-high vacuum chemical vapor deposition.
9. The method of claim 1, wherein the semiconductor substrate is monocrystalline silicon, and the monocrystalline silicon is epitaxially grown in the active recess.
10. The method of claim 1, wherein the process employed to etch the active region to the predetermined depth is wet etching or dry etching.
11. The method of claim 1, wherein forming an active region and an isolation trench on the semiconductor substrate comprises:
forming a photoresist mask on the semiconductor substrate;
etching the semiconductor substrate by using the photoresist mask to form the isolation trench and the active region;
and removing the photoresist mask above the active region.
12. The method as recited in claim 1, further comprising:
and depositing an ion implantation barrier layer on the surface of the semiconductor substrate after epitaxial growth.
13. The method of claim 12, wherein the thickness of the ion implantation barrier layer is 8-12 nm.
14. The method of claim 12, wherein the material of the ion implantation barrier layer is silicon dioxide or silicon nitride.
15. A semiconductor device, comprising: a semiconductor substrate and a functional device in the semiconductor substrate, wherein the semiconductor substrate is prepared by the method of any one of claims 1 to 14.
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| US6413836B1 (en) * | 2000-09-20 | 2002-07-02 | Vanguard International Semiconductor Corporation | Method of making isolation trench |
| CN102456579A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Semiconductor device having localized extremely thin silicon on insulator channel region |
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| CN110970346A (en) * | 2018-09-29 | 2020-04-07 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method |
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| KR100676598B1 (en) * | 2005-04-01 | 2007-01-30 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor memory device |
| US8022472B2 (en) * | 2007-12-04 | 2011-09-20 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| US9601594B2 (en) * | 2011-11-14 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with enhanced strain |
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| US5851899A (en) * | 1996-08-08 | 1998-12-22 | Siemens Aktiengesellschaft | Gapfill and planarization process for shallow trench isolation |
| US6413836B1 (en) * | 2000-09-20 | 2002-07-02 | Vanguard International Semiconductor Corporation | Method of making isolation trench |
| CN102456579A (en) * | 2010-10-27 | 2012-05-16 | 国际商业机器公司 | Semiconductor device having localized extremely thin silicon on insulator channel region |
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