JPS62173763A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62173763A JPS62173763A JP1616086A JP1616086A JPS62173763A JP S62173763 A JPS62173763 A JP S62173763A JP 1616086 A JP1616086 A JP 1616086A JP 1616086 A JP1616086 A JP 1616086A JP S62173763 A JPS62173763 A JP S62173763A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- oxide film
- forming
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 description 8
- 230000001133 acceleration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法、特にライトリ−ド
ープト ドレイン(Lightly Doped Dr
ain :以下LDDと称す)構造の絶縁ゲート(M
OS)電界効果半導体装置の製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a lightly doped drain.
ain :hereinafter referred to as LDD) structure insulated gate (M
(OS) relates to a method of manufacturing a field effect semiconductor device.
第2図(a)ないしくC)は従来のこの種の半導体装置
の製造方法の主要段階における状態を示す断面図である
。まず、第2図(a)に示すように、P型シリコン基F
i1にゲート絶縁膜2及びゲート電極3を形成し、この
ゲート電極3をマスクとして、低加速電圧で低濃度のn
型不純物N)をイオン注入することで、ソース・ドレイ
ンの低濃度n型領域4を形成する。次に、第2図(b)
に示すように、減圧CV D (Loh Pressu
re Chemical Vapour Deposi
tion :以下LPCVDと記す)で酸化膜9を堆
積する。さらに、第2図(C)に示すように、RIE(
Reactive Ion Etching)異方性エ
ツチングによって、ゲート側壁(side wall
)にだけ酸化膜10を残してこれを除去し、その後、ゲ
ート電極3とゲート側壁残部10をマスクにして、高濃
度のn型不純物(IT)をイオン注入し、高濃度n型領
域5を形成する。このようにしてLDD構造が形成され
る。FIGS. 2(a) to 2(c) are cross-sectional views showing the main stages of a conventional method for manufacturing a semiconductor device of this type. First, as shown in FIG. 2(a), a P-type silicon base F
A gate insulating film 2 and a gate electrode 3 are formed on i1, and using this gate electrode 3 as a mask, a low concentration of n is formed at a low acceleration voltage.
By ion-implanting a type impurity (N), low concentration n-type regions 4 for the source and drain are formed. Next, Figure 2(b)
As shown in , low pressure CV D (Loh Pressu
re Chemical Vapor Deposit
An oxide film 9 is deposited using LPCVD (hereinafter referred to as LPCVD). Furthermore, as shown in FIG. 2(C), RIE (
Reactive Ion Etching) The gate side wall is etched by anisotropic etching.
), the oxide film 10 is removed, leaving only the oxide film 10. Then, using the gate electrode 3 and the remaining gate sidewalls 10 as masks, high concentration n-type impurity (IT) is ion-implanted to form the high concentration n-type region 5. Form. In this way, an LDD structure is formed.
従来のLDD構造では、ゲート側壁に酸化膜10を用い
ていたため、RIEを用いた異方性エツチングの終点検
出が困難で、ゲート側壁残部10の巾りの制御性が不十
分であり、ソース・ドレインがエツチングされる可能性
があった。In the conventional LDD structure, since the oxide film 10 is used on the gate sidewall, it is difficult to detect the end point of anisotropic etching using RIE, and the width of the remaining gate sidewall 10 is insufficiently controllable. There was a possibility that the drain could be etched.
この発明は、上記のような従来のものの欠点を除去する
ためになされたもので、容易にゲート側壁残部の巾の制
御性を改善できる半導体装置の製造方法を提供すること
を目的としている。The present invention has been made to eliminate the above-mentioned drawbacks of the conventional method, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can easily improve the controllability of the width of the remaining portion of the gate sidewall.
この発明に係る半導体装置の製造方法は、ゲート電極を
マスクにしてイオン注入した後、シリコン表面にエッチ
ストッパとしての窒化膜を形成し、その上に酸化膜を堆
積して、これをRIE異方性エツチングしてゲート側壁
に酸化膜を残すようにしたものである。In the method for manufacturing a semiconductor device according to the present invention, after ion implantation is performed using a gate electrode as a mask, a nitride film is formed as an etch stopper on the silicon surface, an oxide film is deposited on top of the nitride film, and this is subjected to RIE anisotropic The oxide film is left on the side walls of the gate by etching.
この発明においては、シリコン表面にエッチストッパー
としての窒化膜を形成し、その上に酸化膜を形成するよ
うにしたから、該酸化膜のRIE異方性エツチングの終
点検出をすることができる。In the present invention, since a nitride film is formed as an etch stopper on the silicon surface and an oxide film is formed thereon, the end point of RIE anisotropic etching of the oxide film can be detected.
、〔実施例〕 以下、この発明の実施例を図について説明する。,〔Example〕 Embodiments of the present invention will be described below with reference to the drawings.
第1図(a)ないしfd+は本発明の一実施例により半
導体装置の製造方法をその工程順に示し、図において、
第2図と同一符号は同−又は相当部分を示し、20はゲ
ート絶縁膜(酸化膜)2と多結晶シリコン3よりなるゲ
ート電極、11はソース・ドレインの低濃度n型領域4
を形成した後シリコン表面に形成された窒化膜、12は
該窒化15!11上に形成された酸化膜、13は該酸化
膜12をRIE異方性エツチングにより除去することに
よってゲート側壁部のみに残されたゲート側壁残部であ
る。FIGS. 1(a) to fd+ show a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and in the figures,
The same reference numerals as in FIG. 2 indicate the same or equivalent parts, 20 is a gate electrode made of a gate insulating film (oxide film) 2 and polycrystalline silicon 3, 11 is a low concentration n-type region 4 of the source/drain.
12 is an oxide film formed on the nitride 15!11, and 13 is an oxide film 12 formed on the silicon surface by RIE anisotropic etching to remove only the gate sidewalls. This is the remaining part of the gate side wall.
次に本実施例の製造方法を工程順に説明する。Next, the manufacturing method of this example will be explained step by step.
第1図(a)に示すように、P型シリコン基板1上にゲ
ート酸化膜2及び多結晶のシリコン3よりなるゲート電
極20を形成する(第1の工程)。次にゲート電極20
をマスクとして、例えばP CI)を35KeVの加速
電圧で1×10 イオン注入して低濃度n型領域4を形
成する(第2の工程)。As shown in FIG. 1(a), a gate oxide film 2 and a gate electrode 20 made of polycrystalline silicon 3 are formed on a P-type silicon substrate 1 (first step). Next, the gate electrode 20
Using as a mask, 1×10 6 ions of, for example, PCI) are implanted at an acceleration voltage of 35 KeV to form a low concentration n-type region 4 (second step).
次に第1図(b)に示すように、LPGVDで全面に窒
化膜11を300人堆積し、これをエソチス)7パとす
る(第3の工程)。さらに、LPGVDで該窒化膜13
上に酸化膜12を堆積する(第4の工程)。そして第1
図(C1に示すように、酸化膜12をRIE異方性エツ
チングする。この際エツチング時の発光をモニターする
ことにより、エツチングの終点検出を行って、ゲート側
壁部のみに酸化膜13が残るようにしている(第5の工
程)。Next, as shown in FIG. 1(b), a nitride film 11 is deposited by 300 people on the entire surface by LPGVD, and this is made into 7 layers (third step). Furthermore, the nitride film 13 is
An oxide film 12 is deposited thereon (fourth step). and the first
As shown in FIG. (fifth step).
次に、第1図+d)に示すように、エッチストッパの窒
化膜11を除去し、ゲート電極20と巾りのゲート側壁
残部13をマスクとして、As (II)を50Ke
Vの加速電圧で4×10 イオン注入し、高濃度n型領
域5を形成すると、LDD構造が得られる(第6の工程
)。以下コンタクト窓開き、電極配線工程(図示せず)
などを行なうことによって素子が完成する。Next, as shown in FIG. 1+d), the etch stopper nitride film 11 is removed, and As (II) is deposited at 50Ke using the gate electrode 20 and the remaining gate sidewall 13 as a mask.
By implanting 4×10 4 ions at an acceleration voltage of V to form a heavily doped n-type region 5, an LDD structure is obtained (sixth step). Contact window opening and electrode wiring process (not shown)
By performing these steps, the device is completed.
このように本実施例では、ゲート電極20をマスクにし
てイオン注入した後、シリコン表面に窒化膜11を形成
し、該窒化膜11上に酸化膜12を形成し、発光をモニ
タしながら該酸化膜12のRIE異方性エツチングを行
なうようにしたので、RIE異方性エツチングの終点検
出を可能にでき、その結果ゲート側壁残部13の1tの
制御性を改善でき、またソース・ドレインのエツチング
を防止することができる。In this example, after ion implantation using the gate electrode 20 as a mask, the nitride film 11 is formed on the silicon surface, the oxide film 12 is formed on the nitride film 11, and the oxide film 12 is implanted while monitoring the light emission. Since the RIE anisotropic etching of the film 12 is performed, it is possible to detect the end point of the RIE anisotropic etching, and as a result, it is possible to improve the controllability of 1t of the gate sidewall remaining portion 13, and to improve the etching of the source and drain. It can be prevented.
以上のように本発明にかかる半導体装置の製造方法によ
れば、エッチストッパの窒化膜をシリコン表面に形成す
るようにしたので、ゲート側壁残部13の巾の制御性を
改善できるとともにソース・ドレインのエツチングを防
止できる効果がある。As described above, according to the method of manufacturing a semiconductor device according to the present invention, since the nitride film of the etch stopper is formed on the silicon surface, it is possible to improve the controllability of the width of the gate sidewall remaining portion 13 and to improve the width of the source and drain. It has the effect of preventing etching.
第1図は本発明の一実施例による半導体装置の製造方法
を工程順に示す図、第2図は従来の半導体装置の製造方
法を工程順に示す図である。
1・・・半導体(P型シリコン)基板、2・・・ゲート
絶縁膜、20・・・ゲート電橿、4・・・低濃度(ソー
ス・ドレインn型)領域、5・・・高濃度n型領域、1
1・・・窒化膜、12・・・酸化膜、13・・・ゲート
側壁残部。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps, and FIG. 2 is a diagram showing a method of manufacturing a conventional semiconductor device in order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor (P-type silicon) substrate, 2... Gate insulating film, 20... Gate electrode, 4... Low concentration (source/drain n-type) region, 5... High concentration n type area, 1
1... Nitride film, 12... Oxide film, 13... Gate side wall remainder. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ン基板上にゲート絶縁膜及び多結晶シリコンからなるゲ
ート電極を形成する第1の工程と、この電極をマスクと
して上記シリコン基板に該基板と異なる導電型の不純物
をイオン注入してソース・ドレインを形成する第2の工
程と、 全面に窒化膜を形成する第3の工程と、 該窒化膜上に酸化膜を形成する第4の工程と、異方性エ
ッチングによって上記酸化膜をゲート側壁のみに残し他
の上記酸化膜を除去する第5の工程と、 上記ゲート電極及びゲート側壁残部をマスクとして上記
シリコン基板と異なる導電形の不純物をイオン注入して
上記ソース・ドレインの高濃度不純物領域を形成する第
6の工程とを含むことを特徴とする半導体装置の製造方
法。(1) In a method for manufacturing a field effect semiconductor device, a first step of forming a gate insulating film and a gate electrode made of polycrystalline silicon on a silicon substrate, and using this electrode as a mask, attaching a conductive material different from that of the silicon substrate to the silicon substrate. The second step of forming the source/drain by ion-implanting type impurities, the third step of forming a nitride film on the entire surface, and the fourth step of forming an oxide film on the nitride film are different. a fifth step of leaving the oxide film only on the gate sidewalls and removing the other oxide films by directional etching; and ion-implanting impurities of a conductivity type different from that of the silicon substrate using the gate electrode and the rest of the gate sidewalls as a mask. a sixth step of forming the high concentration impurity regions of the source and drain.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1616086A JPS62173763A (en) | 1986-01-27 | 1986-01-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1616086A JPS62173763A (en) | 1986-01-27 | 1986-01-27 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62173763A true JPS62173763A (en) | 1987-07-30 |
Family
ID=11908756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1616086A Pending JPS62173763A (en) | 1986-01-27 | 1986-01-27 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62173763A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4786609A (en) * | 1987-10-05 | 1988-11-22 | North American Philips Corporation, Signetics Division | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers |
JPH0235740A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JPH02271571A (en) * | 1989-04-12 | 1990-11-06 | Olympus Optical Co Ltd | Solid-state image pickup device and its manufacture |
US5102816A (en) * | 1990-03-27 | 1992-04-07 | Sematech, Inc. | Staircase sidewall spacer for improved source/drain architecture |
US5369297A (en) * | 1991-09-05 | 1994-11-29 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof |
US5766991A (en) * | 1990-05-11 | 1998-06-16 | U.S. Philips Corporation | CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain |
-
1986
- 1986-01-27 JP JP1616086A patent/JPS62173763A/en active Pending
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4786609A (en) * | 1987-10-05 | 1988-11-22 | North American Philips Corporation, Signetics Division | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers |
JPH0235740A (en) * | 1988-07-26 | 1990-02-06 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
JPH02271571A (en) * | 1989-04-12 | 1990-11-06 | Olympus Optical Co Ltd | Solid-state image pickup device and its manufacture |
US5102816A (en) * | 1990-03-27 | 1992-04-07 | Sematech, Inc. | Staircase sidewall spacer for improved source/drain architecture |
US5766991A (en) * | 1990-05-11 | 1998-06-16 | U.S. Philips Corporation | CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain |
US5369297A (en) * | 1991-09-05 | 1994-11-29 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof |
US5554876A (en) * | 1991-09-05 | 1996-09-10 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof |
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