JPS62274665A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the MOS transistor of LDD structure having no junction leak current and excellent controllability over the film thickness of a gate side part by a method wherein a CVD nitride film is grown on a thermally oxidized film, the nitride film is left on a gate side part by performing an anisotropic dry etching, the thermally oxided film is removed by performing a wet etching, and a source and a drain are formed. CONSTITUTION:A gate oxide film and a polycrystalline silicon gate 3 are formed on the surface of a silicon substrate 1, and a thermally oxided film (silicon oxide film) 4 is formed by performing a thermal oxidizing method. Then, a CVD nitride film 5 is grown on the thermally oxidized film 4, an anisotropic dry etching is performed on the film 4, and the dry etching is stopped before the film 4 is completely etched. At this time, the nitride film 5 can be left on the gate side part only. Then, a wet etching is performed on the thermally oxidized film 4, and the thermally oxidized film on the silicon substrate is removed. Subsequently, silicon is thermally oxidized, and a source 7 and a drain 8 are formed by ion-implanting impurities of the opposite conductivity type.

Description

[Detailed Description of the Invention] Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of manufacturing an MO3 structure transistor having a (Lightly Doped Drain) structure.

[Conventional technology]

FIGS. 2(a) to 2(d) show M of the LDD structure according to the prior art.
FIG. 2 is a cross-sectional view of a pellet shown in order of steps to explain a method for manufacturing an OS transistor.

A MOS transistor having an LDD structure can be manufactured by the following steps.

That is, as shown in FIG. 2(a), a gate oxide film 2 is formed on a silicon substrate 1, and then a gate polycrystalline silicon 3 is formed.Next, as shown in FIG. Form PSG 9.

Next, as shown in FIG. 2(c), anisotropic dry etching is performed to leave the PSG 9 only on the gate sides.

Next, a source 7 and a drain 8 are formed by ion implantation. In this case, since there is residual PSG on the side of the gate, the amount of ion implantation is reduced in this part, resulting in the LDD structure shown in FIG. 2(d).

[Problem that the invention seeks to solve]

The above-described conventional method of manufacturing a MOS transistor having an LDD structure has the following problems. In other words, Fig. 2 (b
) When performing anisotropic etching of PSG, if even a slight overetch occurs, the underlying silicon oxide film will be exposed and the silicon substrate will be struck. Hitting a silicon substrate with anisotropic etching tends to cause defects, which can later be sourced.

Even if a drain is formed, junction leakage current tends to increase. In addition, if the anisotropic etching of PSG is stopped long before the PSG film is left thick on the source and drain, when ions are implanted during the formation of the source and drain, the PSG
Ions stay inside, making it difficult for them to enter the silicon substrate and forming a source.

Drain formation will not work properly. It is possible to remove the remaining PSG film on the source and train by wet etching, but it is difficult to remove only the PSG on the source and drain without removing the PSG remaining on the gate side. .

The object of the present invention is to provide an LDD that has no junction leakage current, has good controllability of the film thickness on the gate side, has good controllability of the film thickness on the side with only a few additional steps, and can be formed with only a few additional steps.
It is an object of the present invention to provide a method for manufacturing a semiconductor device in a horizontal manner.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes a step of forming a gate oxide film and a gate electrode on the surface of a conductive type semiconductor substrate, a step of forming a thermal oxide film, and a CVD process on the thermal oxide film.
A step of forming a nitride film and anisotropic dry etching of the CVD nitride film to leave the CVD nitride film only on the gate side, a step of wet etching to remove the thermal oxide film, and a step of removing the remaining film on the gate and the gate side. The method includes a step of ion-implanting impurities of opposite conductivity type using the mask as a mask to form a source and a drain.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(f) are cross-sectional views of a pellet shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1(a), a gate oxide film is formed on the surface of a -conductivity type silicon substrate 1, and then a polycrystalline silicon gate 3 is formed. Next, as shown in FIG. 1(b), a thermal oxide film (silicon oxide film) 4 is formed by thermal oxidation. At this time, there were 500 people on the silicon substrate, and 150 people because the polycrystalline silicon that forms the gate has a high oxidation rate.
An oxide film of 0 people is formed. Next, as shown in FIG. 1(c), 500 CVD nitride films 5 are grown on the thermal oxide film 4.Next, as shown in FIG. 1(d), the CVD nitride film 5 is anisotropically grown. Dry etching is performed, and the etching is stopped when the underlying thermal oxide film 4 is not completely etched.

Since the etching rate of the CVD nitride film is about twice that of the thermal oxide film, it is easy to etch only the CVD nitride film and leave only the underlying thermal oxide film. At this time, since the side portions of the gate are not easily etched, the nitride film 5 can be left only on the side portions of the gate as shown in FIG. 1(d). Next, as shown in FIG. 1(e), the thermal oxide film V4 on the silicon substrate is removed by wet etching. At this time, the thermal oxide film on the gate surface is removed, but the oxide film on the sides of the gate is not etched because it is covered with a nitride film.

Note that since this thermal oxide film is removed by wet etching, no defects occur on the silicon substrate. Next, as shown in FIG. Membrane 4 is 150
Since there are 0 and 500 CVD nitride films, an LDD portion of 0.2 μm in total is formed. This thermal oxide film 4
And by changing the thickness of CVD nitride film 5, LDD
It is possible to control the size of the portions.

It should be noted that if the film thickness on the side of the gate is increased, the offset structure M OS ? -A transistor can be made.

Further, by implanting a small amount of ions of the same type as the source and train forming ions before forming the thermal oxide film 4, it is possible to weaken the electric field on the side of the gate I and strengthen the hot electron resistance.

〔Effect of the invention〕

As explained above, in the present invention, a CVD nitride film is grown on a thermal oxide film, the nitride film is left on the side of the gate by anisotropic dry etching, the thermal oxide film is removed by wet etching, and the source and train are removed. By forming L, there is no junction leakage current and the film thickness on the gate side can be easily controlled.
This has the effect that a DD elliptical MOS transistor can be achieved with only a few additional steps.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views of a semiconductor pellet shown in the order of steps to explain an embodiment of the present invention, and FIG.
a) to (d) are cross-sectional views of a semiconductor pellet shown in order of steps to explain a method of manufacturing a MOS transistor according to an example of the conventional technology. 1... Silicon substrate, 2... Gate oxide film, 3...
・Gate polycrystalline silicon, 4... thermal oxide film, 5...
C■D nitride film, 6... thermal oxide film, 7... source, 8
... Dore Kaya 1 time Y-to Mukuwa 6 items q Funmine 1 (2) Geni Fv gate Z, + Shiqfun half 2 agony

Claims (1)

[Claims] A step of forming a gate oxide film and a gate electrode on the surface of a semiconductor substrate of one conductivity type, a step of forming a thermal oxide film, and a step of forming a CVD nitride film on the thermal oxide film and making the CVD nitride film anisotropic. A process of dry etching to leave the CVD nitride film only on the gate sides, a process of wet etching to remove the thermal oxide film, and a process of ion-implanting impurities of the opposite conductivity type using the gate and the remaining film on the gate sides as a mask to remove the source. . A method of manufacturing a semiconductor device, the method comprising: forming a drain.