JPS6290974A - Manufacture of mosfet - Google Patents

Abstract

PURPOSE:To readily manufacture MOSFET of LDD structure without using anisotropic RIE unit by thermally oxidizing under high pressure a phosphorus- doped polysilicon layer. CONSTITUTION:A field oxide film 2 and a gate oxide film 3 are formed by a P-type silicon substrate 1, a phosphorus-doped polysilicon layers are laminated to form a gate electrode 4, and an N<-> type layer 5 is formed on source, drain regions. Then, high pressure thermal oxidation is applied to the substrate to form a thick oxide film 10 on the phosphorus-doped polysilicon layer of the gate electrode. A thin oxide film 11 is formed on the bulk silicon region of source, drain regions. The film 11 on the bulk silicon is removed by isotropic etching the substrate. At this time, an N<-1> type layer 12 remains on the region masked with the film 10 remaining on the sidewall of the gate electrode.

Description

[Detailed Description of the Invention] [Summary] As the channel length of MOSFET becomes shorter and reaches the submicron region, hot carrier
r) The problem of effectiveness becomes unavoidable, but usually L D D
(Lightly Doped Drain)
We are taking measures based on the structure. In the present invention, an MOS F using an LDD structure does not use an expensive anisotropic RIE device.
The method for manufacturing ET will be explained.

[Industrial application field]

The present invention is directed to an LD used in a highly integrated MOSFET.
The present invention relates to a method of manufacturing a D-structure MOS FET.

As the degree of integration increases, the channel length between the source and drain tends to become shorter and shorter, but when the channel length reaches the submicron range, hot carrier effects cannot be ignored. This is particularly a problem with n-channel O3FETs.

The hot carrier effect is a phenomenon in which carriers heading toward the drain are accelerated by the high electric field in the drain region, obtain sufficient energy, and are injected into the gate oxide film by overcoming the potential barrier between Si and SiO□. , threshold voltage, and other transconductance characteristics.

To solve this problem, a MOS FET with an LDD structure has been proposed, but this structure requires the use of anisotropic RIE as a process, and it is not possible to form an LDD structure without using an expensive RIE equipment. There is a need for a manufacturing method that does this.

[Conventional technology]

In order to improve the hot carrier effect, methods such as increasing the thickness of the gate oxide film and creating a gentle slope in the impurity concentration distribution are used to weaken the electric field at the junction near the drain region.

The LDD structure is designed to alleviate the electric field near the latter drain region, and its manufacturing method will be explained in more detail with reference to FIG.

As shown in Figure 2(a), a normal n-MOSFET
A substrate is used in which a field oxide film 2, a gate oxide film 3, and a gate electrode 4 made of polysilicon are formed on a p-type substrate 1 in the same manner as in the process described above.

In this state, as shown in the figure, an n layer 5 is first formed in the source and drain regions by ion implantation of phosphorus.

Next, a thick oxide film 6 is grown over the entire surface by CVD. This is shown in FIG. 2(b).

Anisotropic etching is applied to the above substrate by RIE method. Since it is anisotropic, the oxide film 6 is removed leaving the oxide film 7 on the sidewall surface of the gate electrode 4.

Highly concentrated arsenic ions are implanted into this to form a source region 8 and a drain region 9. This state is shown in Figure 2 (C
).

The n layer 5 formed by the initial phosphorus ion implantation has a low concentration, and the arsenic ion implantation region has a high concentration and is formed at a position slightly distant from the gate electrode due to the presence of the oxide film 7.

By providing a difference in impurity concentration as described above, the electric field strength in the region near the drain can be significantly reduced.

[Problem that the invention seeks to solve]

The above-mentioned measure against the hot carrier effect by the LDD structure is to use the RIE method as its manufacturing process.

Recently, the anisotropic RIE method has been increasingly used as a dry etching method, but the equipment is relatively expensive, and when considering mass production, it is preferable to use general isotropic etching. is desirable.

[Means for solving problems]

The above problems are solved by the manufacturing method of the present invention, which includes the following steps.

A gate oxide film and then a phosphorous-doped polysilicon layer are laminated on the substrate, and a gate electrode is formed by patterning.

Next, after patterning the source and drain regions to expose the substrate, phosphorus ions are implanted, and an oxide film is grown over the entire surface by high-pressure thermal oxidation.

Next, the oxide film on the bulk silicon of the source and drain is removed by isotropic etching, and arsenic ions are implanted into the source and drain regions to form a gradient in impurity concentration near the drain region, which increases the electric field. The strength can be weakened.

[Effect]

When a polysilicon layer that can be doped with phosphorus is subjected to high-pressure thermal oxidation,
The thickness of the oxide film is four to five times greater than the thickness of a normal bulk silicon oxide film.

Therefore, even if isotropic etching is subsequently applied,
The oxide film on the sidewalls of the gate electrode remains, and the oxide film on the bulk silicon surface of the source and drain regions can be removed.

As a result, the oxide film on the side wall surface of the gate electrode serves as a mask during arsenic ion implantation, and forms a gradient characteristic in the region into which impurities are introduced.

〔Example〕 An embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 fa) to (cl) are step-by-step cross-sectional views showing the manufacturing method of the present invention. 6 The description of steps that are the same as those of a normal MOSFET process will be simplified.

FIG. 1 (al shows a state in which a p-type silicon substrate 1 is used, a field oxide film 2 and a gate oxide film 3 are formed, and then a phosphorus-doped polysilicon layer is laminated and a gate electrode 4 is formed by patterning. .

The above process is no different from a normal MOSFET process except for the use of phosphorous-doped polysilicon.

Next, phosphorus ions are implanted into the source and drain regions. The implantation was 80KeV and the dose was IXIO”
/cm". This results in n in the source and drain regions.
One layer 5 is formed.

Next, high pressure thermal oxidation is applied to the substrate. A thick oxide film 1o is formed on the phosphorus-doped polysilicon layer of the gate electrode by placing the substrate in a pressure tank of about 10 atmospheres and raising the substrate temperature to about 900''C.

On the other hand, since the bulk silicon region of the source and drain regions has a slow oxidation rate, a thin oxide film 11 is formed. Under such high-pressure oxidation conditions, the growth rate of oxidized Nl of phosphorous-doped polysilicon is bulk.

The oxidation rate is 4 to 5 times that of silicon. The state after high-pressure oxidation is shown in FIG. 1(b).

The above substrate is subjected to isotropic etching, that is, wet etching to remove the oxide film 11 on the bulk silicon. At this time, most of the oxide film 10 covering the gate electrode remains because it is thick.

In this state, arsenic ions are implanted to form a highly concentrated n+ layer, and a source region 8 and a drain region 9 are formed.

Arsenic ion implantation is 120KeV, dose is lX
LO15/Cl11''.

At this time, the n layer 12 is left in the region masked by the oxide film 10 left on the side wall surface of the gate electrode.

This is shown in Figure 1 fc).

This remaining n layer has the function of relaxing the electric field strength during operation and suppressing the hot carrier effect.

Subsequent processes such as formation of wiring layers and formation of protective films are omitted.

〔Effect of the invention〕

As explained above, by applying the manufacturing method of the present invention, LD can be easily produced without using an anisotropic RIE device.
It has become possible to manufacture a D-structure MOS FET.

[Brief explanation of drawings]

FIG. 1 (al~(C1 is a step-order cross-sectional view showing the method for manufacturing an LDD structure MOSFET according to the present invention, and FIG. 2 (
al~(c) are MOSFs with LDD structure made by the conventional method.
1A and 1B are step-by-step cross-sectional views showing a method for manufacturing an ET. In the drawings, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5.12 is an n-layer, 6, 7.10.11 is an oxide film, 8 is a source region, 9 shows the drain region, respectively. 1st flash 2nd leap

Claims (1)

[Claims] A gate oxide film (3) is formed on a substrate (1), and then a gate electrode (4) made of a polysilicon layer doped with phosphorous is formed, and then source and drain forming regions of the substrate are selectively formed. After exposure, phosphorus ions are implanted, and oxide films (10) and (11) are grown on the entire surface by high-pressure thermal oxidation, and oxide films (10) and (11) are grown on the bulk silicon of the source and drain by isotropic etching. A step of removing the film (11) and removing the source region (8).
), a method for manufacturing a MOSFET, comprising the steps of implanting arsenic ions into the drain region (9).