JP2707901B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2707901B2
JP2707901B2 JP720092A JP720092A JP2707901B2 JP 2707901 B2 JP2707901 B2 JP 2707901B2 JP 720092 A JP720092 A JP 720092A JP 720092 A JP720092 A JP 720092A JP 2707901 B2 JP2707901 B2 JP 2707901B2
Authority
JP
Japan
Prior art keywords
film
silicon nitride
element isolation
oxide film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP720092A
Other languages
Japanese (ja)
Other versions
JPH05211233A (en
Inventor
浩 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP720092A priority Critical patent/JP2707901B2/en
Publication of JPH05211233A publication Critical patent/JPH05211233A/en
Application granted granted Critical
Publication of JP2707901B2 publication Critical patent/JP2707901B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に選択酸化法による素子分離酸化膜の形成法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation oxide film by a selective oxidation method.

【0002】[0002]

【従来の技術】従来の半導体装置の製造工程における素
子分離酸化膜の形成方法を図4を用いて説明する。
2. Description of the Related Art A method for forming an element isolation oxide film in a conventional semiconductor device manufacturing process will be described with reference to FIG.

【0003】まず図4(a)に示すように、シリコン基
板1上にパッド酸化膜(SiO2 )2Aと窒化シリコン
膜(Si3 4 )3Aを形成した後、窒化シリコン膜を
パターニングし素子分離領域に開口部を設ける。次でこ
の窒化シリコン膜3Aをマスクとして熱酸化し素子分離
酸化膜7Bを形成する。
First, as shown in FIG. 4A, a pad oxide film (SiO 2 ) 2A and a silicon nitride film (Si 3 N 4 ) 3A are formed on a silicon substrate 1, and then the silicon nitride film is patterned. An opening is provided in the separation region. Next, thermal oxidation is performed using the silicon nitride film 3A as a mask to form an element isolation oxide film 7B.

【0004】次に図4(b)に示すように、素子分離領
域以外の窒化シリコン膜3A及びパッド酸化膜2Aを除
去する。
Next, as shown in FIG. 4B, the silicon nitride film 3A and the pad oxide film 2A other than the element isolation region are removed.

【0005】[0005]

【発明が解決しようとする課題】デバイスの高集積化が
進むにつれ素子分離領域の縮小化、つまり選択酸化法に
よる素子分離酸化膜7Bの横方向の広がり(バーズビー
ク)の縮小化が要求されてきている。そのため、従来の
選択酸化による素子分離酸化膜の形成方法では、バーズ
ビークを縮小にするため窒化シリコン膜を厚くし、パッ
ド酸化膜を薄くする必要がある。パッド酸化膜の薄膜化
及び窒化シリコン膜を厚くすることにより、バーズビー
クの縮小は認められるものの、窒化シリコン膜のもたら
す応力がパッド酸化膜で緩和することができないため、
シリコン基板に欠陥を発生させデバイス特性を劣下させ
るという欠点がある。
As the degree of integration of the device increases, it is required to reduce the element isolation region, that is, to reduce the lateral spread (bird's beak) of the element isolation oxide film 7B by the selective oxidation method. I have. Therefore, in the conventional method of forming an element isolation oxide film by selective oxidation, it is necessary to increase the thickness of the silicon nitride film and reduce the thickness of the pad oxide film in order to reduce the bird's beak. By reducing the thickness of the pad oxide film and increasing the thickness of the silicon nitride film, the bird's beak is reduced, but the stress caused by the silicon nitride film cannot be reduced by the pad oxide film.
There is a disadvantage that defects are generated in the silicon substrate and device characteristics deteriorate.

【0006】また、チャンネルストッパーとして所望の
不純物をイオン注入する場合、パッド酸化膜を介してシ
リコン基板に注入し欠陥の発生を抑制していたが、パッ
ド酸化膜が薄くなると、窒化シリコン膜除去の際、パッ
ド酸化膜が同時に除去されベアー注入となり、基板に欠
陥が多量に発生するという欠点がある。
In addition, when a desired impurity is ion-implanted as a channel stopper, a silicon oxide is implanted through a pad oxide film to suppress the occurrence of defects. However, when the pad oxide film becomes thinner, the silicon nitride film is removed. In this case, the pad oxide film is removed at the same time, resulting in a bare implantation, which has a disadvantage that a large number of defects are generated on the substrate.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、シリコン基板上に薄い酸化シリコン膜と窒化
シリコン膜を順次形成したのち素子分離領域の少くとも
前記窒化シリコン膜を選択的に除去する工程と、前記窒
化シリコン膜の側壁に絶縁膜からなるサイドウォールを
形成した後全面にポリシリコン膜を形成する工程と、前
記ポリシリコン膜上よりチャンネルストッパーとして所
望の不純物をイオン注入した後前記素子分離領域を選択
的に酸化し素子分離酸化膜を形成する工程とを含むもの
である。
According to a method of manufacturing a semiconductor device of the present invention, a thin silicon oxide film and a silicon nitride film are sequentially formed on a silicon substrate, and then at least the silicon nitride film in an element isolation region is selectively formed. Removing, forming a sidewall made of an insulating film on the side wall of the silicon nitride film, and then forming a polysilicon film on the entire surface, and ion-implanting a desired impurity from above the polysilicon film as a channel stopper. Selectively oxidizing the element isolation region to form an element isolation oxide film.

【0008】[0008]

【実施例】次に本発明について図面を参照して説明す
る。図1(a),(b)は本発明の第1の実施例を説明
するための半導体チップの断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B are sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

【0009】まず図1(a)に示すように、低濃度P型
の面方位(100)を有するシリコン基板1上に、パッ
ド酸化膜2を45nm,窒化シリコン膜3を300nm
の厚さに形成する。次で素子分離領域上の窒化シリコン
膜3をパターニングし開口部を設けた後、この窒化シリ
コン膜3の側壁にサイドウォール4として窒化シリコン
膜を形成する。このサイドウォール4が横方向の酸化過
程を抑制し、素子分離領域の横方向広がりを小さくす
る。更に実際のマスク設計寸法より小さい素子分離領域
が形成されるわけである。その後、サイドウォール4上
にカバー膜およびイオン注入保護膜として、ポリシリコ
ン膜5を約100nmの厚さに形成する。その後チャン
ネルストッパーとしてボロンイオン6を50kev,ド
ーズ量1.5×1013cm-2の条件でポリシリコン膜5
を介してシリコン基板1に注入する。その際、ポリシリ
コン膜5は注入損傷を緩和させる保護膜となる。
First, as shown in FIG. 1A, a pad oxide film 2 and a silicon nitride film 3 are formed on a silicon substrate 1 having a low-concentration p-type plane orientation (100) at 45 nm and a silicon nitride film 3 at 300 nm.
Formed to a thickness of Next, after the silicon nitride film 3 on the element isolation region is patterned to provide an opening, a silicon nitride film is formed as a sidewall 4 on a side wall of the silicon nitride film 3. The sidewalls 4 suppress the lateral oxidation process and reduce the lateral spread of the element isolation region. Further, an element isolation region smaller than the actual mask design dimension is formed. Thereafter, a polysilicon film 5 having a thickness of about 100 nm is formed on the sidewalls 4 as a cover film and an ion implantation protection film. Thereafter, the polysilicon film 5 is formed as a channel stopper under the condition of boron ions 6 of 50 keV and a dose of 1.5 × 10 13 cm −2.
Is injected into the silicon substrate 1. At this time, the polysilicon film 5 becomes a protective film for alleviating implantation damage.

【0010】次に図1(b)に示すように、1000
℃、2時間、ウエット酸化を行ない、素子分離酸化膜7
を形成する。以下図1(c)に示すように、ウエットエ
ッチング法等により窒化シリコン膜3等を除去し、酸化
膜7からなる素子分離領域を完成させる。
Next, as shown in FIG.
At 2 ° C., wet oxidation is performed for 2 hours to obtain an element isolation oxide film 7.
To form Thereafter, as shown in FIG. 1C, the silicon nitride film 3 and the like are removed by a wet etching method or the like to complete an element isolation region composed of the oxide film 7.

【0011】従来の技術と比較するため図3に素子分離
領域の横方向広がりの素子分離酸化膜厚依存性を示す。
従来技術による素子分離領域の横方向の広がりに比べ、
本実施例では、素子分離酸化膜7のバーズビークが抑制
されるため素子分離領域の横方向広がりは小さく、本実
施例の優位性が認められる。
FIG. 3 shows the dependence of the lateral expansion of the isolation region on the thickness of the isolation oxide film for comparison with the prior art.
Compared to the lateral expansion of the element isolation region according to the prior art,
In this embodiment, since the bird's beak of the element isolation oxide film 7 is suppressed, the lateral expansion of the element isolation region is small, and the superiority of this embodiment is recognized.

【0012】図2(a)〜(c)は本発明の第2の実施
例を説明するための半導体チップの断面図である。
FIGS. 2A to 2C are sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

【0013】まず図2(a)に示すように、低濃度P型
の面方位(100)を有するシリコン基板1上に、パッ
ド酸化膜2を20nm,窒化シリコン膜3を300nm
の厚さに形成する。次で素子分離領域上の窒化シリコン
膜3をパターニングした後、その側壁にサイドウォール
4として窒化シリコン膜を形成する。その後、これら窒
化シリコン膜3,4をマスクとしてシリコン基板1に溝
10を100nmの深さで形成する。その際、ドライエ
ッニングの異方性を弱め、溝10の側壁が傾くようにす
る。その後、カバー膜およびイオン注入保護膜として、
ポリシリコン膜5Aを100nmの厚さに堆積させる。
その後、ボロンイオン6をポリシリコン膜5Aを介して
シリコン基板1に注入する。
First, as shown in FIG. 2A, on a silicon substrate 1 having a low-concentration P-type plane orientation (100), a pad oxide film 2 and a silicon nitride film 3 are formed to a thickness of 20 nm and 300 nm, respectively.
Formed to a thickness of Next, after patterning the silicon nitride film 3 on the element isolation region, a silicon nitride film is formed as a sidewall 4 on the side wall. Thereafter, a groove 10 is formed to a depth of 100 nm in the silicon substrate 1 using the silicon nitride films 3 and 4 as a mask. At this time, the anisotropy of dry etching is weakened, and the side wall of the groove 10 is inclined. Then, as a cover film and an ion implantation protection film,
A polysilicon film 5A is deposited to a thickness of 100 nm.
After that, boron ions 6 are implanted into the silicon substrate 1 via the polysilicon film 5A.

【0014】次に図2(b)に示すように、ウエット酸
化により素子分離酸化膜7Aを形成したのち、図2
(c)に示すように、窒化シリコン膜3等をウエットエ
ッチング法で除去する。
Next, as shown in FIG. 2B, after an element isolation oxide film 7A is formed by wet oxidation,
As shown in (c), the silicon nitride film 3 and the like are removed by a wet etching method.

【0015】このように第2の実施例によれば、溝10
の形成により素子分離酸化膜7Aが深く形成されるた
め、第1の実施例に比べバーズビークを更に小さくでき
る利点がある。
As described above, according to the second embodiment, the groove 10
Since the element isolation oxide film 7A is formed deeper by the formation of the gate electrode, the bird's beak can be further reduced as compared with the first embodiment.

【0016】[0016]

【発明の効果】以上説明したように本発明は、シリコン
基板上の絶縁膜の側壁にサイドウォールを形成し、その
上にカバー膜およびイオン注入保護膜として、ポリシリ
コン膜を形成した後、チャンネルストッパーとして所望
の不純物をイオン注入した後、素子分離領域を酸化させ
ることにより、酸化膜からなる素子分離領域の横方向広
がりを少くできるという効果がある。更にイオン注入よ
る欠陥の発生を抑制できるという効果もある。
As described above, according to the present invention, a side wall is formed on a side wall of an insulating film on a silicon substrate, and a polysilicon film is formed thereon as a cover film and an ion implantation protection film. By oxidizing the element isolation region after ion implantation of a desired impurity as a stopper, there is an effect that the lateral spread of the element isolation region made of an oxide film can be reduced. Further, there is an effect that generation of defects due to ion implantation can be suppressed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例を説明するための半導体
チップの断面図。
FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

【図2】本発明の第2の実施例を説明するための半導体
チップの断面図。
FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention.

【図3】実施例の効果を説明するための素子分離領域の
横方向広がりの酸化膜厚依存性を示す図。
FIG. 3 is a view showing the dependence of the lateral expansion of the element isolation region on the oxide film thickness for explaining the effect of the embodiment.

【図4】従来例を説明するための半導体チップの断面
図。
FIG. 4 is a sectional view of a semiconductor chip for explaining a conventional example.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2,2A パッド酸化膜 3,3A 窒化シリコン膜 4 サイドウォール 5,5A ポリシリコン膜 6 ボロンイオン 7,7A,7B 素子分離酸化膜 10 溝 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 2A Pad oxide film 3, 3A Silicon nitride film 4 Side wall 5, 5A Polysilicon film 6 Boron ion 7, 7A, 7B Element isolation oxide film 10 Groove

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 シリコン基板上に薄い酸化シリコン膜と
窒化シリコン膜を順次形成したのち素子分離領域の少く
とも前記窒化シリコン膜を選択的に除去する工程と、前
記窒化シリコン膜の側壁に絶縁膜からなるサイドウォー
ルを形成した後全面にポリシリコン膜を形成する工程
と、前記ポリシリコン膜上よりチャンネルストッパーと
して所望の不純物をイオン注入した後前記素子分離領域
を選択的に酸化し素子分離酸化膜を形成する工程とを含
むことを特徴とする半導体装置の製造方法。
A step of sequentially forming a thin silicon oxide film and a silicon nitride film on a silicon substrate and then selectively removing at least the silicon nitride film in an element isolation region; and forming an insulating film on a side wall of the silicon nitride film. Forming a polysilicon film over the entire surface after forming a sidewall made of a silicon oxide film, and selectively oxidizing the device isolation region after ion implantation of a desired impurity from above the polysilicon film as a channel stopper. Forming a semiconductor device.
【請求項2】 サイドウォール間のシリコン基板に浅い
溝を形成した後ポリシリコン膜を形成する請求項1記載
の半導体装置の製造方法。
2. The method according to claim 1, wherein a polysilicon film is formed after forming a shallow groove in the silicon substrate between the side walls.
JP720092A 1992-01-20 1992-01-20 Method for manufacturing semiconductor device Expired - Lifetime JP2707901B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP720092A JP2707901B2 (en) 1992-01-20 1992-01-20 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP720092A JP2707901B2 (en) 1992-01-20 1992-01-20 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH05211233A JPH05211233A (en) 1993-08-20
JP2707901B2 true JP2707901B2 (en) 1998-02-04

Family

ID=11659390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP720092A Expired - Lifetime JP2707901B2 (en) 1992-01-20 1992-01-20 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2707901B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960011859B1 (en) * 1993-04-22 1996-09-03 현대전자산업 주식회사 Manufacturing method of field oxide of semiconductor device
JP2625372B2 (en) * 1993-12-27 1997-07-02 行政院国家科学委員会 Improved method for growing oxide layer in zoned silicon oxidation method

Also Published As

Publication number Publication date
JPH05211233A (en) 1993-08-20

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