JPS6373667A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS6373667A JPS6373667A JP22000186A JP22000186A JPS6373667A JP S6373667 A JPS6373667 A JP S6373667A JP 22000186 A JP22000186 A JP 22000186A JP 22000186 A JP22000186 A JP 22000186A JP S6373667 A JPS6373667 A JP S6373667A
- Authority
- JP
- Japan
- Prior art keywords
- oxidation
- layer
- gate electrode
- electrode
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 40
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はＬ Ｄ Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ
Ｄｒａｉｎ ）構造のＭＯ３半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention is applied to LDD (Lightly Doped)
The present invention relates to a method of manufacturing an MO3 semiconductor device having a drain) structure.
（ロ）従来の技術
近年、ＭＯＳ半導体装置が微細化されるに伴い、ドレイ
ン領域近傍でのチャンネル領域における強電界によって
生じるホットキャリアの発生に伴うしきい値電圧の変動
等の緒特性の劣化が問題となっている。斯る問題を解決
するためにＬＤＤ構造のＭＯＳ半導体装置が提案された
。このＬＤＤ構造はＭＯＳ半導体装置のドレイン領域（
およびソース領域）をチャンネル領域近傍の低濃度不純
物領域とこの低濃度不純物領域に隣接する高濃度不純物
領域とから構成したものである。このＬＤＤ構造のＭＯ
３半導体装置はチャンネル領域における強電界を緩和す
ることができるので、ショートチャンネルにおける種々
の問題を解消できる。(b) Conventional technology In recent years, as MOS semiconductor devices have been miniaturized, their characteristics have deteriorated, such as fluctuations in threshold voltage due to the generation of hot carriers caused by strong electric fields in the channel region near the drain region. This has become a problem. In order to solve this problem, a MOS semiconductor device with an LDD structure has been proposed. This LDD structure is the drain region (
(and source region) is composed of a low concentration impurity region near the channel region and a high concentration impurity region adjacent to this low concentration impurity region. MO of this LDD structure
Since the third semiconductor device can alleviate the strong electric field in the channel region, various problems in short channels can be solved.
斯るＬＤＤ構造のＭＯ３半導体装置は第２図Ａ乃至第２
図りに示す製造方法で形成きれていた。MO3 semiconductor devices with such an LDD structure are shown in FIGS.
It was completed using the manufacturing method shown in the figure.
まず第２図Ａに示す如く、Ｐ型シリコン基板（２１）表
面に選択酸化法に従いフィールド酸化膜（２２）を形成
し、素子領域（２３）にゲート酸化膜（２４）を介して
ポリシリコンより成るゲート電極（２５）を形成した後
、このゲート電極（２５）をマスクとしてＮ型不純物を
低ドーズ量でイオン注入する。First, as shown in FIG. 2A, a field oxide film (22) is formed on the surface of a P-type silicon substrate (21) according to a selective oxidation method, and a polysilicon film is formed in the element region (23) via a gate oxide film (24). After forming the gate electrode (25), N-type impurities are ion-implanted at a low dose using the gate electrode (25) as a mask.
次に第２図Ｂに示す如く、全面にＣＶＤ酸化膜（２６）
を堆積する。Next, as shown in Figure 2B, a CVD oxide film (26) is formed on the entire surface.
Deposit.
続いて第２図Ｃに示す如く、このＣＶＤ酸化膜（２６）
を異方性エツチングによりエツチングし、ゲート電極（
２５〉の側面に残存するＣＶＤ酸化膜（２６）より成る
サイドウオール膜（２７）を形成する。このサイドウオ
ール膜（２７）の幅は形成すべきＮ−型不純物領域の幅
と等しくなるように異方性エツチングの条件を規定する
。そしてゲート電極（２５）とサイドウオール膜（２７
）をマスクとしてＮ型不純物を高ドーズ量でイオン注入
する。Next, as shown in FIG. 2C, this CVD oxide film (26) is
is etched by anisotropic etching, and the gate electrode (
A sidewall film (27) made of a CVD oxide film (26) remaining on the side surface of the film 25> is formed. The conditions for anisotropic etching are determined so that the width of this sidewall film (27) is equal to the width of the N- type impurity region to be formed. Then, the gate electrode (25) and the sidewall film (27)
) is used as a mask to implant N-type impurity ions at a high dose.
更に第２図りに示す如く、熱処理を行ない前記２回の不
純物イオン注入層を活性化してチャンネル領域近傍のＮ
−型不純物領域（２８ａ）（２９ａ）とこれらの領域に
隣接するＮ＋型不純物領域（２８ｂ）（２９ｂ）とから
なるソース、ドレイン領域（２８）（２９）を形成する
。Furthermore, as shown in the second diagram, heat treatment is performed to activate the impurity ion implantation layer described above and to remove N near the channel region.
Source and drain regions (28) and (29) are formed of - type impurity regions (28a) and (29a) and N+ type impurity regions (28b and 29b) adjacent to these regions.
斯上した従来の製造方法は例えば特開昭５９−１９７１
６１号公報等に記載されている。The above-mentioned conventional manufacturing method is described in, for example, Japanese Patent Application Laid-Open No. 1983-1971.
It is described in Publication No. 61, etc.
（八）発明が解決しようとする問題点
しかし斯上した製造方法ではＬＤＤ構造を形成するため
に、ＣＶＤ酸化膜（２６）を堆積し、異方性エツチング
によりサイドウオール膜（２７）を形成しているので、
サイドウオール膜（２７）の形成に２工程を要し工程が
複雑となる問題点があり、またサイドウオール膜（２７
）の巾のコントロールもＣＶＤ酸化膜（２６）の厚みと
異方性エツチングで決められるので、サイドウオール膜
（２７）の巾のコントロールが難しい問題点があった。(8) Problems to be solved by the invention However, in the above manufacturing method, in order to form the LDD structure, a CVD oxide film (26) is deposited and a sidewall film (27) is formed by anisotropic etching. Because
There is a problem that two steps are required to form the sidewall film (27), which complicates the process.
) is also determined by the thickness of the CVD oxide film (26) and anisotropic etching, so there is a problem in that it is difficult to control the width of the sidewall film (27).
（ニ）問題点を解決するための手段
本発明は斯上した問題点に鑑みてなされ、ゲート電極の
上面を耐酸化マスク層で被覆することにより、ゲート電
極の側面のみに選択酸化によりサイドウオール層を形成
することにより、従来の問題点を大巾に改善したＭＯ３
半導体装置の製造方法を実現するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and by covering the upper surface of the gate electrode with an oxidation-resistant mask layer, side walls are formed by selective oxidation only on the side surfaces of the gate electrode. MO3 has greatly improved the conventional problems by forming layers.
This realizes a method for manufacturing a semiconductor device.
（＊）作用
本発明に依れば、ゲート電極の側面のみに選択酸化によ
りサイドウオール層を形成しているので、サイドウオー
ル層の巾を熱酸化の酸化時間のみでコントロールでき、
サイドウオール層の巾のコントロールを容易にできる。(*) Function According to the present invention, since the sidewall layer is formed only on the side surface of the gate electrode by selective oxidation, the width of the sidewall layer can be controlled only by the oxidation time of thermal oxidation.
The width of the sidewall layer can be easily controlled.
（へ）実施例
本発明の一実施例を第１図Ａ乃至第１図Ｅを参照して詳
述する。(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.
本発明の第１の工程は第１図Ａおよび第１図Ｂに示すよ
うに、一導電型の半導体基板（１）表面にゲート絶縁膜
（２）を介してポリシリコンより成るゲート電極（３）
を形成し、ゲート電極（３）上面を耐酸化マスク層（４
）で被覆することにある。In the first step of the present invention, as shown in FIGS. 1A and 1B, a gate electrode (3 )
, and cover the upper surface of the gate electrode (3) with an oxidation-resistant mask layer (4).
).
本工程ではＰ型のシリコン基板（１）表面に選択酸化法
によりフィールド酸化膜（５）を形成し、素子領域（６
）表面には薄いゲート酸化膜（２）を形成する。続いて
ゲート酸化膜（２）上にはリンドープしたポリシリコン
層（７）を約５ｏｏｏ人の厚みに全面にＬＰＣＶＤ法で
付着し、その上にストレス防止のための約２５０人の薄
い酸化膜（８）と耐酸化マスク層となるシリコン窒化膜
（４）とを全面にＬＰＣＶＤ法で付着する。更にシリコ
ン窒化膜（４）上に所望のゲート電極（３）のパターン
をしたホトレジスト層（９）を付着し、このホトレジス
ト層（９）をマスクとして用い耐酸化マスク層（４）、
シリコン酸化膜（８）およびポリシリコン層（７）を順
次反応性イオンエツチングによりエツチングする。この
結果、上面を耐酸化マスク層（４）で被覆きれたゲート
電極（３）を形成できる。In this step, a field oxide film (5) is formed on the surface of a P-type silicon substrate (1) by selective oxidation, and a field oxide film (5) is formed on the surface of a P-type silicon substrate (1).
) A thin gate oxide film (2) is formed on the surface. Next, on the gate oxide film (2), a phosphorous-doped polysilicon layer (7) is deposited on the entire surface to a thickness of about 500 mm using the LPCVD method, and on top of this a thin oxide film of about 250 mm is deposited to prevent stress. 8) and a silicon nitride film (4) serving as an oxidation-resistant mask layer are deposited over the entire surface by LPCVD. Furthermore, a photoresist layer (9) with a desired gate electrode (3) pattern is deposited on the silicon nitride film (4), and using this photoresist layer (9) as a mask, an oxidation-resistant mask layer (4),
The silicon oxide film (8) and the polysilicon layer (7) are sequentially etched by reactive ion etching. As a result, a gate electrode (3) whose upper surface is completely covered with the oxidation-resistant mask layer (4) can be formed.
本発明の第２の工程は第１図Ｃに示すように、ゲート電
極（３）をマスクとして半導体基板（１）表面に低不純
物濃度のソースドレイン領域（１０）（１１）を形成す
ることにある。As shown in FIG. 1C, the second step of the present invention is to form source and drain regions (10) and (11) with low impurity concentration on the surface of the semiconductor substrate (1) using the gate electrode (3) as a mask. be.
本工程ではゲート酸化膜（２）を介してリンをドーズ量
３ Ｘ １０ ”ａｎ−”、加速電圧５０ＫｅＶでイオ
ン注入し、基板（１）表面に約６００人の深さにＮ−型
のソースドレイン領域（１０）（１１）を形成している
。In this step, phosphorus ions are implanted through the gate oxide film (2) at a dose of 3 x 10 "an-" and an acceleration voltage of 50 KeV, and an N- type source is implanted at a depth of about 600 nm on the surface of the substrate (1). Drain regions (10) and (11) are formed.
本発明の第３の工程は第１図りに示すように、耐酸化マ
スク層（４）をマスクとしてゲート電極（３）の側面に
選択酸化による酸化膜より成るサイドウオール層（１２
）を形成することにある。As shown in the first diagram, the third step of the present invention is to form a sidewall layer (12) made of an oxide film by selective oxidation on the side surface of the gate electrode (3) using the oxidation-resistant mask layer (4) as a mask.
).
本工程は本発明の特徴とする工程であり、ゲート電極（
３）上を被覆するシリコン窒化膜より成る耐酸化マスク
層（４）を選択酸化のマスクとして用い、８００℃、ス
チーム雰囲気中で約３０分間の選択酸化を行う、この結
果ゲート電極（３）の側面に巾約２０００人の熱酸化膜
より成るサイドウオール層（１２）を形成できる。サイ
ドウオール層（１２）の巾は熱酸化の時間で精度良くコ
ントロールでき、従来の方法よりその巾のコントロール
は容易となる。なおゲート電極（３）上面は耐酸化マス
ク層（４）があるので、不要の酸化は防げ、ゲート電極
（３）の厚みが酸化により薄くなり高抵抗化きれるのを
防げる。This process is a characteristic process of the present invention, and is the process in which the gate electrode (
3) Using the oxidation-resistant mask layer (4) made of a silicon nitride film covering the top as a mask for selective oxidation, selective oxidation is performed at 800°C in a steam atmosphere for about 30 minutes. As a result, the gate electrode (3) A sidewall layer (12) consisting of a thermal oxide film having a width of approximately 2000 layers can be formed on the side surface. The width of the sidewall layer (12) can be precisely controlled by the thermal oxidation time, making it easier to control the width than with conventional methods. Since the oxidation-resistant mask layer (4) is provided on the upper surface of the gate electrode (3), unnecessary oxidation can be prevented, and the thickness of the gate electrode (3) can be prevented from becoming thinner due to oxidation and becoming higher in resistance.
本発明の第４の工程は第１図Ｅに示すように、ゲート電
極（３）およびサイドウオール層（１２）をマスクとし
て高不純物濃度のソースドレイン領域（１３）（１４）
を形成することにある。In the fourth step of the present invention, as shown in FIG.
The goal is to form a
本工程ではヒ素をドーズ量５ Ｘ Ｉ Ｑ ’、’ｃｍ
’″−加速電圧８０ＫｅＶでイオン注入し、約３０００
人の深さのＮ＋型のソースドレイン領域（１３）（１４
）を形成する。従ってＮ−型のソースドレイン領域（１
０）（１１）はサイドウオール層（１２）の巾だけＮ”
型のソースドレイン領域（１３）（１４）よりチャンネ
ル側に突出したＬＤＤ構造を実現できる。In this process, the dose of arsenic is 5 x IQ','cm
''' - Ion implantation at an acceleration voltage of 80KeV, approximately 3000
Human-depth N+ type source/drain regions (13) (14)
) to form. Therefore, the N-type source/drain region (1
0) (11) is the width of the sidewall layer (12) N”
It is possible to realize an LDD structure that protrudes toward the channel side from the source/drain regions (13) and (14) of the mold.
衛士した工程の後、耐酸化マスク層（４）はウェットエ
ツチングで除去し、Ｎ＋型のソースドレイン領域（１３
）（１４）にオーミックコンタクトするソースドレイン
電極を形成する。After the regular process, the oxidation-resistant mask layer (4) is removed by wet etching, and the N+ type source/drain region (13) is removed by wet etching.
) A source/drain electrode is formed in ohmic contact with (14).
（ト）発明の効果
本発明に依れば、サイドウオール膜（１２）をゲート電
極（３）側面の選択酸化で形成するので、最初に耐酸化
マスク層（４）を積層するのみで良く、従来のＣＶＤ酸
化膜の付着および異方性エツチングの工程を省略でき、
工程の簡略化を図れる利点を有する。(G) Effects of the Invention According to the present invention, since the sidewall film (12) is formed by selective oxidation of the side surface of the gate electrode (3), it is only necessary to first stack the oxidation-resistant mask layer (4). The conventional CVD oxide film deposition and anisotropic etching steps can be omitted,
This has the advantage of simplifying the process.
また本発明に依れば、サイドウオール膜（１２）を選択
酸化による熱酸化で形成するので、サイドウオール膜（
１２）の巾のコントロールが容易となり、良好なＬＤＤ
構造のＭＯ３半導体装置を量産できる利点を有する。Further, according to the present invention, since the sidewall film (12) is formed by thermal oxidation using selective oxidation, the sidewall film (12) is formed by thermal oxidation using selective oxidation.
12) Width can be easily controlled, resulting in a good LDD
It has the advantage of being able to mass produce MO3 semiconductor devices with this structure.
更にゲート電極（３）の上面は耐酸化マスク層（４）で
被覆されているので、ゲート電極（３）が酸化により薄
くなることがなく、ゲート電極（３）の高抵抗化を防止
できる利点を有する。Furthermore, since the upper surface of the gate electrode (3) is covered with the oxidation-resistant mask layer (4), the gate electrode (3) does not become thinner due to oxidation, which has the advantage of preventing high resistance of the gate electrode (3). has.
第１図Ａ乃至第１図Ｅは本発明によるＭＯＳ半導体装置
の製造方法を説明する断面図、第２図Ａ乃至第２図りは
従来のＭＯ３半導体装置の製造方法を説明する断面図で
ある。
（１）は半導体基板、 （２）はゲート酸化膜、（３）
はゲート電極、 （４）は耐酸化マスク層、（１０）（
１１）はＮ−型ソースドレイン領域、 （１２）はサイ
ドウオール膜、（１３）（１４）はＮ“型ソースドレイ
ン領域である。
出願人 三洋電機株式会社外１名
代理人 弁理士 西野卓嗣 外１名
第１図八
第１図り
第１図Ｅ
第２図Ａ1A to 1E are cross-sectional views for explaining a method of manufacturing a MOS semiconductor device according to the present invention, and FIGS. 2A to 2E are cross-sectional views for explaining a conventional method for manufacturing an MO3 semiconductor device. (1) is a semiconductor substrate, (2) is a gate oxide film, (3)
is a gate electrode, (4) is an oxidation-resistant mask layer, (10) (
11) is an N-type source/drain region, (12) is a sidewall film, and (13) and (14) are N" type source/drain regions. Applicant: Sanyo Electric Co., Ltd. and one other representative Patent attorney: Takuji Nishino 1 person Figure 1 Figure 8 Figure 1 Figure 1 E Figure 2 A
Claims (1)
てポリシリコンより成るゲート電極を形成し、前記ゲー
ト電極上を耐酸化マスク層で被覆する工程、前記ゲート
電極をマスクとして前記半導体基板表面に低不純物濃度
のソースドレイン領域を形成する工程、前記耐酸化マス
ク層をマスクとして前記ゲート電極の側面に選択酸化に
よる酸化膜より成るサイドウォール層を形成する工程、
前記ゲート電極および前記サイドウォール層をマスクと
して高不純物濃度のソースドレイン領域を形成する工程
とを具備することを特徴とするＭＯＳ半導体装置の製造
方法。(1) A step of forming a gate electrode made of polysilicon on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and covering the gate electrode with an oxidation-resistant mask layer, and using the gate electrode as a mask, the semiconductor substrate a step of forming a source/drain region with a low impurity concentration on the surface; a step of forming a sidewall layer made of an oxide film by selective oxidation on the side surface of the gate electrode using the oxidation-resistant mask layer as a mask;
A method of manufacturing a MOS semiconductor device, comprising the step of forming a source/drain region with a high impurity concentration using the gate electrode and the sidewall layer as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22000186A JPS6373667A (en) | 1986-09-17 | 1986-09-17 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22000186A JPS6373667A (en) | 1986-09-17 | 1986-09-17 | Manufacture of mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6373667A true JPS6373667A (en) | 1988-04-04 |
Family
ID=16744376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22000186A Pending JPS6373667A (en) | 1986-09-17 | 1986-09-17 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6373667A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01134972A (en) * | 1987-10-05 | 1989-05-26 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH02153538A (en) * | 1988-12-05 | 1990-06-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH08148558A (en) * | 1994-11-15 | 1996-06-07 | Nec Corp | Manufacture of semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59207662A (en) * | 1983-05-11 | 1984-11-24 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS59220971A (en) * | 1983-05-31 | 1984-12-12 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-09-17 JP JP22000186A patent/JPS6373667A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59207662A (en) * | 1983-05-11 | 1984-11-24 | Hitachi Ltd | Manufacture of semiconductor device |
| JPS59220971A (en) * | 1983-05-31 | 1984-12-12 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01134972A (en) * | 1987-10-05 | 1989-05-26 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH02153538A (en) * | 1988-12-05 | 1990-06-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH08148558A (en) * | 1994-11-15 | 1996-06-07 | Nec Corp | Manufacture of semiconductor device |
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