JPS63219170A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a semiconductor device manufacturing process by a method wherein a gate electrode is subjected to pyrogenic oxidation (oxidation by burning hydrogen) for the formation of a side wall layer on the sides of the gate electrode through an oxidation process wherein oxidation is accelerated when impurity concentration is properly selected. CONSTITUTION:A gate insulating film and a polycrystalline silicon layer are formed on the surface of a substrate 1 and ion implantation is so accomplished that the peak may be located at the middle of the polycrystalline silicon layer. The polycrystalline silicon layer is subjected to etching for the construction of a gate electrode 6, after which source.drain regions 8 and 9 low in impurity concentration are formed. A process follows wherein pyrogenic oxidation is accomplished, with the property being taken into account that the rate of oxidation is high at a portion where implanted ion concentration is at its peak, whereby a side wall layer 10 is formed of silicon oxide on the sides of the gate electrode 6. After this, high-concentration source.drain regions 11 and 12 are formed. In this way, an anisotropic etching process may be dispensed with and the side wall width may be controlled with more ease.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention is applied to LDD (Lightly Doped)
The present invention relates to a method of manufacturing a MOS semiconductor device having a drain) structure.

(b) Conventional technology In recent years, as MOS semiconductor devices have been miniaturized, their characteristics have deteriorated, such as fluctuations in threshold voltage due to the generation of hot carriers caused by strong electric fields in the channel region near the drain region. This has become a problem. In order to solve this problem, a MOS semiconductor device with an LDD structure has been proposed. This LDD structure is the drain region (
(and source region) is composed of a low concentration impurity region near the channel region and a high concentration impurity region adjacent to this low concentration impurity region. MO of this LDD structure
Since the S semiconductor device can alleviate the strong electric field in the channel region, various problems in short channels can be solved.

MOS semiconductor devices with such an LDD structure are shown in FIGS.
It was completed using the manufacturing method shown in the figure.

First, as shown in FIG. 2A, a field oxide film (22) is formed on the surface of a P-type silicon substrate (21) according to a selective oxidation method, and a polysilicon film is formed on the element region (23) via a gate oxide film (24). After forming the gate electrode (25), N-type impurities are ion-implanted at a low dose using the gate electrode (25) as a mask.

Next, as shown in Figure 2B, a CVD oxide film (26) is formed on the entire surface.
Deposit.

Next, as shown in FIG. 2C, this CVD oxide film (26) is
is etched by anisotropic etching, and the gate electrode (
A sidewall film (27) made of a CVD oxide film (26) remaining on the side surface of the film 25> is formed. The conditions for anisotropic etching are determined so that the width of this sidewall film (27) is equal to the width of the N-type impurity region to be formed. Then, the gate electrode (25) and the sidewall film (27)
) is used as a mask to implant N-type impurity ions at a high dose.

Furthermore, as shown in the second diagram, heat treatment is performed to activate the impurity ion implantation layer described above and to remove N near the channel region.
Source and drain regions (28) and (29) are formed of - type impurity regions (28a) and (29a) and N+ type impurity regions (28b and 29b) adjacent to these regions.

The above-mentioned conventional manufacturing method is described in, for example, Japanese Patent Application Laid-Open No. 1983-1971.
It is described in Publication No. 61, etc.

(c) Problems to be solved by the invention However, in the above manufacturing method, in order to form the LDD structure, a CVD oxide film (26) is deposited, and a sidewall film (27) is formed by anisotropic etching. Because
There is a problem that two steps are required to form the sidewall film (27), which complicates the process.
) is also determined by the thickness of the CVD oxide film (26) and anisotropic etching, so there is a problem in that it is difficult to control the width of the sidewall film (27).

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and the peak position of ion implantation is set at an intermediate position of the polysilicon layer forming the gate electrode. By forming a sidewall layer on the side surface of the gate electrode by pyrooxidation, a method of manufacturing a MOS semiconductor device is realized which greatly improves the conventional problems.

(E) Function According to the present invention, since the sidewall layer is formed only on the side surface of the gate electrode by selective oxidation, the width of the sidewall layer can be controlled only by the oxidation time of thermal oxidation.
The width of the sidewall layer can be easily controlled.

Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1A to 1E.

As shown in FIG. 1A, the first step of the present invention is to deposit a polysilicon layer (3) on the surface of a semiconductor substrate (1) of one conductivity type via a gate insulating film (2). (3)
The purpose is to implant impurity ions so that the peak is at an intermediate position.

In this step, a field oxide film (4) is formed on the surface of a P-type silicon substrate (1) by selective oxidation, and a field oxide film (4) is formed on the surface of a P-type silicon substrate (1).
) A thin gate oxide film <2) is formed on the surface. Subsequently, a polysilicon layer (3) is deposited on the entire surface of the gate oxide film (2) to a thickness of about 5,000 mm using the LPCVD method. The polysilicon layer (3) has a phosphorus dose of 5 x 1
0 "cm-" and an acceleration voltage of 130 KeV, the impurity concentration peak due to ion implantation is 1 cm from the surface.
The number is set at 500 people. The reason for setting the peak of the impurity concentration of ion implantation at the middle position of the polysilicon layer (3) is to ensure that the oxidation rate of the accelerated oxidation performed in the subsequent process peaks at the side of the polysilicon layer (3). It's for a reason.

In the second step of the present invention, as shown in FIG. 1B, the polysilicon layer (3) is etched to form a desired gate electrode (6).
The goal is to form a

In this step, a photoresist layer (7) with a desired gate electrode (6) pattern is deposited on the polysilicon layer (3), and using this photoresist layer (7) as a mask, the polysilicon layer (3) is exposed to reactive ions. A gate electrode (6) is formed by etching.

As shown in FIG. 1C, the third step of the present invention is to form source and drain regions (8) and (9) with low impurity concentration on the surface of the semiconductor substrate (1) using the gate electrode (6) as a mask. be.

In this process, phosphorus is dosed through the gate oxide film (2) at a dose of 3XIQ "c1'rl-" and an acceleration voltage of 50Ke.
Ions are implanted at V to form an N-type source/drain region (8>(9)) at a depth of approximately 600 nm on the surface of the substrate (1).

As shown in the first diagram, the fourth step of the present invention is to thermally oxidize the gate electrode (6) at a low temperature to form a sidewall layer (10) made of an oxide film on the side surface of the gate electrode (6). It is in.

This step is a characteristic step of the present invention, in which the entire substrate (1) is thermally oxidized at a low temperature, and a silicon oxide film is formed on the side surface of the gate electrode (6) using accelerated oxidation of the gate electrode (6). A sidewall layer (10) is formed. This thermal oxidation treatment specifically performs pyrooxidation (hydrogen combustion oxidation) at 875° C. for 20 minutes, and utilizes the property that the peak position of impurity concentration in ion implantation has a high oxidation rate.

Therefore, in this process, as shown in Figure 3, the gate electrode (6)
When pyro-oxidized, a 900-layer oxide film is formed on the surface, whereas a 2,000-layer oxide film can be formed at the same time at the peak impurity concentration position of 1,500-layer ion implantation. As a result, a thicker oxide film is obtained on the sides of the gate electrode (6) than on the surface of the gate electrode (6), so the sidewall layer (10
) can be applied effectively without using a mask. The reason why accelerated oxidation occurs is thought to be that there are many defects at the peak position of the impurity concentration during ion implantation, which promotes oxidation.

The fifth step of the present invention, as shown in FIG. be.

In this process, the dose of arsenic is 5 x 10 "cm-",
Ion implantation is performed at an accelerating voltage of 80 KeV to form N+ type source/drain regions (11) and (12) with a depth of about 3000. Therefore, N-type source/drain regions (8) (9
) is an N+ type saw for the width of the sidewall layer (10).
7= It is possible to realize an LDD structure that protrudes toward the channel side from the strain regions (11) and (12).

After the above steps, an N" type source/drain region (11
) A source/drain electrode is formed in ohmic contact with (12).

(G) Effects of the Invention According to the present invention, since the sidewall layer (10) is formed by accelerated oxidation of the side surface of the gate electrode (6>), only a low-temperature oxidation step is required, and the deposition of a conventional CVD oxide film is not required. Also, the process of anisotropic etching can be omitted, which has the advantage of simplifying the process.

Further, according to the present invention, since the sidewall layer (1o) is formed by thermal oxidation using pyrooxidation, the width of the sidewall layer (10) can be easily controlled, resulting in a good LD.
It has the advantage that D-structure MOS semiconductor devices can be mass-produced.

Furthermore, since the upper surface of the gate electrode <6) uses accelerated oxidation, it is not oxidized much, and the gate electrode (6) does not become thin due to oxidation, which has the advantage of preventing the gate electrode (6) from becoming high in resistance. .

[Brief explanation of the drawing]

1A to 1E are cross-sectional views explaining a method for manufacturing an MO3 semiconductor device according to the present invention, and FIGS. 2A to 2E are cross-sectional views explaining a conventional method for manufacturing a MOS semiconductor device.
FIG. 3 is a characteristic diagram illustrating the accelerated oxidation used in the present invention. (1) is a semiconductor substrate, (2) is a gate oxide film, and 6)
is the gate electrode, (8) (9) is the N-type source/drain region, (10) is the sidewall film, (11) (
12) is an N+ type source/drain region. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Fig. 1 A Fig. 1 D Fig. 2 △ Fig. 2 Fig. 3 V Now Uka? Nephew/4/'; Niza

Claims (1)

[Claims] (1) A step of attaching a polysilicon layer to the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and implanting impurity ions so that a peak occurs at an intermediate position of the polysilicon layer, and the polysilicon layer. forming a source/drain region of opposite conductivity type and having a low impurity concentration on the surface of the semiconductor substrate using the gate electrode as a mask; and thermally oxidizing the gate electrode at a low temperature. forming a sidewall layer made of an oxide film on a side surface of the gate electrode; and forming a source/drain region of opposite conductivity type and having a high impurity concentration using the gate electrode and the sidewall layer as a mask. A method for manufacturing a MOS semiconductor device, characterized in that: