JPS59104167A - Manufacture of insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To readily manufacture in a self-alignment by oxidizing the entire surface to allow the part not oxidized of the substance formed in the prescribed shape to remain. CONSTITUTION:An oxidized film 22 and a polycrystalline Si 23 are sequentially formed on a P type semiconductor substrate 21. Then, only the exposed part of the film 22 is removed. Then, the entire surface is oxidized, the part not oxidized in the Si 23 is allowed to remain as a gate electrode 23'. Then, an oxidized film 24' is allowed to remain on the upper and side parts of the electrodes 23'. With the electrode 23' and the film 24' as masks an N<+> type high density impurity layer 26 is formed. Subsequently, with the electrode 23' as a mask, an N type low density impurity layer 27 is formed adjacent to the layer 26.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing an insulated gate field effect transistor having a structure that suppresses instability of transistor characteristics when miniaturized. .

[Technical background of the invention]

In order to increase the speed and density of semiconductor devices, it is necessary to reduce the size of insulated gate field effect transistors (hereinafter abbreviated as MO8FBT),
That is, it is necessary to make the gate insulating film thinner and shorten the gate length. However, the reduction in size of the MO8FET causes electric field concentration at the drain end at the semiconductor substrate interface, causing instability of transistor characteristics.

This instability is caused by the fact that the impurity concentration in the source and drain causes considerable defects in the semiconductor crystal lattice. This impurity concentration is
It is also required to provide good ohmic contact between the source and drain metal electrodes, and cannot be selected arbitrarily.

Therefore, the following structure was proposed. That is, the impurity concentration of the source and drain, which are in contact with both ends of the channel, respectively, is set to such a concentration that the impurity does not cause substantial physical defects in the semiconductor crystal lattice, and the impurity concentration of the source and drain, which is far from the channel, is adjusted to a concentration that does not cause substantial physical defects in the semiconductor crystal lattice. The concentration should be such that it provides good ohmic contact with the electrode. At this time, the former impurity concentration is lower than the latter impurity concentration.

Such a structure is Lightly Dopeol Dr.
This is called an ain structure (LDD structure).

Hereinafter, a conventional manufacturing method of the above structure will be described with reference to FIG. First, on the semiconductor substrate 11 of the first conductivity type, 100~
An insulating film of 12 gold is formed to a thickness of 200λ. (Figure 1(a)
)) After forming the entire gate electrode 13 with a thickness of about 3000X using photolithography, using this gate as a mask, the impurity exchange substrate of a second conductivity type different from the semiconductor substrate 11 is implanted. , a low concentration impurity layer 14 is formed.

(FIG. 1(b)) Next, an insulating film 15 with a thickness of about 3000× is deposited over the entire surface by CVD. At this time, the thickness of the insulating film at the stepped portion 16 due to the gate electrode 13 is approximately 600 mm.
(Fig. 1 (C)) Next, reactive ion etching (l(T)), which is anisotropic etching, is performed.
When the insulating film 15 is removed until the gate electrode 13 is exposed by E), approximately 300 mm is left at the end of the gate electrode 13.
An insulating film 17 with a thickness of X remains. The etching here is R
IE is required. This is because isotropic etching such as wet etching and dry etching cannot leave a desired insulating film at the end of the gate electrode. After that, the gate 'a layer 13 and the remaining insulating film 1 are removed.
7 as a mask, an impurity of a second conductivity type different from that of the semiconductor substrate 11 is implanted into the substrate to form a high concentration impurity layer 18f.

(FIG. 1(d)) After that, an interlayer insulating film is deposited, wiring of At or the like is formed, and MO8FETf is formed.

[Problems with background technology]

The conventional technology has the following drawbacks.

First, after forming the low concentration impurity f1114, it is difficult to control the shape of the deposition at the end of the gate electrode when the entire insulating film 15 is deposited by CVD. This is because the shape depends on the thickness and width of the gate electrode 13 and the thickness of the insulating film 15. If the insulating film 15 is not sufficiently deposited on the end of the gate electrode, RIF! 1: If this is done, very little of the insulating film 17 will remain, rendering the mask useless. Furthermore, if the stepped portion becomes gentle, the edge of the insulating film 17 left as a mask will also become gentle, making it difficult to form a high concentration impurity layer in the desired shape.

Next, if the thickness of the insulating film 15 at a position optically separated from the gate electrode 13 is not uniform, when performing RIE thereafter, the thin insulating film portion will be removed from the insulating film 12. The thickness of the insulating film 15 needs to be uniform, but it is difficult to do this with high precision because there is a risk that the etching may be etched to the semiconductor substrate 11, resulting in contamination and damage to the substrate surface. .

Furthermore, in order to etch the insulating film 15t, RIE must be used, but since RIE is uneven, some places are etched deeply and others are etched shallowly, and the insulating film is thoroughly removed. It is difficult to do so.

If all of the following steps are performed while the substrate surface is still damaged by RIE, junction leakage will increase, resulting in a decrease in drain breakdown voltage, making it impossible to obtain a MOSFET with desired performance.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and is
The purpose of the present invention is to provide a manufacturing method that can easily produce MO8FETi that can fully exhibit the effects of the D structure, has well-controlled, and uniform characteristic sound.

[Summary of the invention]

An insulating film is formed on a semiconductor substrate of a first conductivity type, and a substance having a faster oxidation rate than the semiconductor substrate is formed thereon in a predetermined shape.

The entire surface of the material is oxidized in a predetermined shape so that an unoxidized portion remains inside the material. The portion of the material formed into the predetermined shape that remains unoxidized becomes the gate electrode. At this time, due to the difference in oxidation rate, the oxide film on the semiconductor substrate is thinner than the oxide film around the gate electrode.

Using all or part of the gate electrode and the surrounding thick oxide film as a mask, a highly concentrated impurity layer of a second conductivity type different from that of the semiconductor substrate is formed. Next, the oxide film around the gate electrode is removed, and using the gate electrode as a mask, a low concentration impurity layer of a second conductivity type different from that of the substrate is entirely formed.

After that, an interlayer insulating film is deposited, wiring such as At is performed, and MO
Form an SFET.

[Embodiments of the invention]

The present invention will be explained below with reference to FIG.

The semiconductor substrate 21 is a thin plate of single crystal silicon about 600 μm thick and containing about 10 cm of boron. An oxide film 22 with a thickness of about 200 cm is formed as an insulating film on this P-type semiconductor substrate 21, and phosphorus is further applied on it to a thickness of about 10 cm.
Approximately 4 oooi of added polycrystalline silicon is deposited.

Using photolithography, polycrystalline silicon remains only in predetermined locations. As a mask for the remaining polycrystalline silicon 23, the oxide film 22 is removed using an aqueous ammonium fluoride solution.
Remove only the exposed parts. (Figure 2 (
a)) Next, the entire surface is oxidized for 100 minutes in an atmosphere of 8,500 H, 100° C., leaving an unoxidized portion of about 2,000× thick inside the remaining polycrystalline silicon 23. This will be referred to as the gate electrode 23'. A thick oxide film 24 with a thickness of about 4000X is formed on the upper and side parts of this gate electrode 23'.
is formed. On the other hand, about 1
A thin oxide film 25 having a thickness of 000X is formed. (
FIG. 2(b)) The reason why such a difference in the thickness of the oxide film occurs during simultaneous oxidation is that there is a large difference in the oxidation rate of the remaining polycrystalline silicon 23 and the substance constituting the semiconductor substrate 21. It is. In this case, the difference changes depending on the concentration of the impurity added to the polycrystalline silicon, so it is easy to make the thickness of each oxide film desired by adjusting the impurity concentration.

Then, the oxide film is completely removed by the thickness of the thin oxide film 25 using an ammonium fluoride aqueous solution.

Then, approximately 30
An oxide film 24' having a thickness of 0.00 K remains.

As a mask for the gate electrode 23' and the remaining oxide film 24', arsenic is fully implanted to form an N-type high concentration impurity layer 26 having a concentration of about 10"car". (Figure 2 (C)) Next,
After removing the oxide film exposed on the substrate with an ammonium fluoride aqueous solution, υ is implanted using the gate electrode 23' as a mask, and the N-type low-concentration impurity layer 27 with a concentration of about 10 α is replaced with an N-type high-concentration impurity. Formed adjacent layer 26. (
Figure 2 (d)) After that, by depositing an interlayer insulating film and wiring such as At, an LDD structure MO8F with the desired performance can be obtained.
IilT can be obtained.

In this example, the exposed portion of the oxide film 22 was removed after forming the remaining polycrystalline silicon 23;
The thickness of the oxide film 24.25 is approximately 200X, which can be considered to be sufficiently smaller than the thickness of the oxide film 24.25 that will be formed in a later step, so it is not essential to perform this removal step. It's a shame to omit this and go to the next step.

Further, after forming the oxide films 24 and 25, a thin oxide film 25 is formed.
Although the oxide film was removed by the thickness of , this removal step is not essential. If so, the thickness of the thin oxide film 25 is approximately 1
000λ, and it is also possible to implant impurities from above.

Furthermore, by appropriately selecting the removal amount in the three oxide film removal steps and the oxidation amount in the oxidation step in this embodiment, the height of the gate electrode 23', the channel length, the position of the two impurity layers, etc. can be freely adjusted. It can be changed.

Further, in this embodiment, wet etching using an aqueous ammonium fluoride solution was used to remove the oxide film, but other etching methods such as dry etching may also be used.

The impurities added to the semiconductor substrate, polycrystalline silicon, etc. shown in this embodiment are merely examples, and any impurity may be used as long as it produces similar sound effects. In addition, this embodiment uses N type M08F
Although the method of manufacturing ET was described above, it is clear that the present invention can also be used for manufacturing P-type MO8FET. Furthermore, the material deposited on the insulating film 22 is not limited to fully doped polycrystalline silicon, but may be any material that has a faster oxidation rate than the semiconductor substrate.

〔Effect of the invention〕

In the conventional method, after forming the gate electrode, an insulating film is deposited by CVD, and RIE'i is used to leave the insulating film on the shoulder of the gate electrode to serve as a mask. However, in this method, when the insulating film is entirely deposited by CVD, the thickness at a position away from the gate electrode is not uniform because of the presence of the gate electrode. If RIEi is performed in this state, if too much is removed, damage will be added to the substrate surface, and if too little is removed, the insulating film will remain at locations other than the gate electrode shoulder on the substrate surface. In other words, it is extremely difficult to leave the P film only on the shoulder portion of the gate electrode without damaging the substrate surface. Moreover, the shape of the insulating film remaining on the gate electrode shoulder changes depending on the CVD deposition process and the RIE process.
．． The control of the insulating film to remain by IFi is complicated.

However, according to the present invention, since the layer growth step is always carried out over the entire surface, unevenness in layer thickness is less likely to occur, and the gate voltage $i1. Since the entire surrounding oxide film is formed by an oxidation process, accurate shape control is possible.

Furthermore, in the conventional method, RIE is used in the mask forming process.
However, in the present invention, etching itself is not essential, and even if all etching is performed, it is not necessary to use anisotropic etching, so wet etching that does not damage the substrate surface can be selected. . In addition, RIB may be selected, and even in that case, since the amount of etching is smaller than in the conventional case, etching unevenness is reduced, and damage to the substrate surface can be reduced.

As described above, according to the present invention, the desired sex WE
It can be easily manufactured using the M08FFiTe self-fa line with k.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process according to the prior art. FIG. 2 is a sectional view showing the manufacturing process of an embodiment of the present invention. 21...Semiconductor substrate 22...Insulating film 23'...'dtlfj 24.
...Thick oxide film 25 ...Thin oxide film
26...High concentration impurity layer 27...
Low concentration impurity 1m1 Agent Patent attorney Noriyuki Chika (and 1 other person) Strategy 1 mouth (41 (1)) (Qr < d) ■2 mouth (b+ (Q) 2/1 (d) Shi-111 11111

Claims (1)

[Claims] 1. A step of forming a substance having a faster oxidation rate than the semiconductor substrate in a predetermined shape at a predetermined position on an insulating film formed on a semiconductor substrate of a first conductivity type; a substrate and
forming an oxide film on the surface by oxidizing the surface of the material having the predetermined shape; a step of forming a second conductivity type high concentration impurity region in its entirety; a step of removing an oxide film formed on the surface of the material having the predetermined shape; and a step of masking the entire non-oxidized portion of the material having the predetermined shape. , forming a part of the second conductivity type low concentration impurity region in the second conductivity type tortoise-type high concentration impurity region. . 2. The method of manufacturing an insulated gate field effect transistor according to claim 1, wherein the high concentration impurity region is deeper than the low concentration impurity region. 3. The method for manufacturing an insulated gate field effect transistor according to claim 1, wherein the material having the predetermined shape is polycrystalline 7-licon containing impurities Kt.