JPS63240068A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten a process by a method wherein a gate electrode is formed, using a photo-resist as a mask, the photo-resist on the gate electrode is deformed and employed as a mask and first source-drain regions are shaped through an ion implantation method. CONSTITUTION:When source-drain diffusion regions are formed, a gate electrode 105 is shaped, using a photo-resist 104 as a mask. The photo-resist 104 is deformed so that an orthogonal projection image to a semiconductor substrate 10 of the end section of the photo-resist 104 on the gate electrode 105 surrounds the end section of the gate electrode 105 and is positioned outside the gate electrode 105. A reverse conductivity type impurity is introduced through an ion implantation method, employing a deformed photo-resist 104a as a mask, thus shaping first source-drain regions. Accordingly, the processes of the formation of a novel film and etchback are unnecessitated after the formation of the gate electrode and processes can be shortened largely, and the silicon substrate is not etched, and damage and the effect of contamination can be removed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a field effect transistor having a (liqhtly doped drain) structure.

[Conventional technology]

A field effect transistor with the LIJJJ structure is made resistant to the hot electron effect by relaxing the electric field and making the slope of the source/drain impurity diffusion region partially east of the edge of the gate electrode gentle. Can be done. For this reason, the vicinity of the gate electrode is formed with a lower impurity level.

Conventional 1. ．． An example of a method for manufacturing a field effect transistor having the structure 131) will be explained using the fourth factor.

First, l! 4 As shown in Figure (a), a P-type silicon substrate 201
A field oxide film 2 with a thickness of soon m is selectively formed on the 0 surface.
02 is provided, and a gate oxide film 2 with a thickness of 2 Qnm is provided in the active region.
After forming 03, a polycrystalline silicon film with a thickness of 400 nm is released over the entire surface using chemical vapor deposition (CVD) = 2, and then after 7 otolithography steps, a gate electrode 2041&: is formed. Thereafter, phosphorus, which is an n-type impurity, is doped by ion implantation to a concentration of about 10 cR to form a source 205 and a drain 7206ft.

Next, as shown in FIG.
07 is formed.

Next, as in 21) (C), the entire surface is etched back using reactive ion etching (RIE) to form oxide film sidewalls 208 along the side surfaces of the gate electrode. This reactive ion etching method (l(, IE
), is it normal to perform over-etching in case the oxide film is not formed with a uniform thickness over the entire surface of the silicon substrate or the etchback is not performed at a uniform etching speed? Since the etching rate ratio between the oxide film and silicon is not infinite but has a finite value, the silicon substrate and the gate electrode made of the polycrystalline silicon group are also etched to some extent.

In particular, steps are formed on the silicon substrate.

Next, as shown in No. 21g(d), add a thick layer to the entire surface.
After forming the oxide @209 of m, arsenic, which is an n-type impurity, is doped with an ambiguity of about 10 (1'l!) by ion implantation, and then heat treatment for activation is performed to double diffuse. A source 205a and a drain 206a are formed.After this, using a suitable insulating layer and a conductive film, L
L) A field effect transistor with the structure 1) was manufactured.

[Problem that the invention seeks to solve]

According to the above-mentioned nine conventional manufacturing methods, it is necessary to form an oxide film and etch back after forming the gate electrode, resulting in a complicated process. In addition, as explained using the cross-sectional view of CJ in Figure 2, reactive ion etching (RIE)
During etchback using etching, the surface of the silicon substrate is inevitably etched, resulting in damage and step formation.

Further, at this time, there is a drawback that contaminants such as metals are deposited from the components inside the etching apparatus at the same time as etching, which becomes a factor in deteriorating the characteristics and reliability of the transistor.

It is an object of the present invention to form an LDD structure by greatly shortening the process without requiring a new film formation or etch-back process after forming a gate electrode, and without etching the silicon substrate, thereby preventing damage. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a field effect transistor, which can eliminate the influence of contamination, has excellent shape, characteristics, and reliability.

[Flat membrane to solve problems]

The method for manufacturing a semiconductor device of the present invention includes step 1 of forming source/drain diffusion regions* of opposite conductivity type in a -conductivity type semiconductor substrate! : A method of manufacturing a semiconductor device using an insulated gate field effect transistor comprising: a step of forming a gate electrode on a photoresist mask when forming the source/drain diffusion region; (7) deforming the photoresist so that the orthogonal projection image of the end of the photoresist onto the semiconductor substrate covers the entire end of the gate electrode and is located outside; and using the deformed photoresist as a mask. The structure includes a step of introducing reverse-conducting type impurities by ion implantation to form first source/drain regions, and gold.

(9) As a step before or after the step of forming the first source/drain impurity diffusion region, an impurity of the opposite conductivity type is introduced using the gate electrode as a mask, and the second source/drain impurity diffusion region is formed. LL) An embodiment of the invention is obtained which includes a gate field effect transistor having source and drain impurity diffusion regions of the iJ structure.

Maximum impurity concentration klOcr of the first source/drain impurity diffusion region! L or more, it is better to set the maximum impurity concentration of the second source/drain impurity diffusion region to 1OcnL or less7? An embodiment of the invention is obtained comprising an insulated gate field effect transistor having source/drain impurity diffusion regions of -LL)i) structure.

In addition, the present invention can be implemented by using a P-type semiconductor substrate, arsenic as an impurity in the first source/drain impurity diffusion region, and phosphorus as an impurity in the second source/drain impurity diffusion region. , 1) A semiconductor device having an n-channel insulated gate field effect transistor having the L) structure is obtained.

In addition, by implementing the present invention using an n-type semiconductor substrate, using boron as an impurity in the first source/drain impurity diffusion region, and also using boron as an impurity in the second source/drain impurity diffusion region, an LDL) structure can be obtained. P with
A semiconductor device having a channel type insulated gate field effect transistor is obtained.

〔Example〕

Next, embodiments of the present invention will be described with reference to all the drawings. FIG. 1 (aJ to (at) are longitudinal cross-sectional views of a friend semiconductor device shown in order of process for explaining one embodiment of the present invention.

First, as shown in FIG.
A field oxide film 102 with a thickness of 5QQnm is selectively formed on the surface of 1, and a gate oxide film 103 with a thickness of 20nm is released in the active region, and then a gate oxide film 103 with a thickness of 4001m is formed over the entire surface.
The polycrystalline silicon film is released using chemical vapor deposition (CVL), and a photoresist pattern 104 is formed using a photolithography process, and the photoresist is used as a mask to digate using anisotropic etching. Electrode 1
A source 106 and a drain 107 are formed by doping phosphorus, which is an n-type impurity, to a concentration of about 10 3 by ion implantation.

Next, as shown in FIG.
transform.

Next, photoresist 1 deformed as shown in FIG.
A source 106a and a drain 107a are formed by doping an n-type impurity with arsenic gold 1 (approximately 1771) by ion implantation into the silicon substrate vertically using a 0.04ae mask.

Next, remove the 7-otoresist as shown in Figure 1 (dl),
After an activation heat treatment, the double diffused t-source 10
6b and a drain 107b'i are formed.

After this, using an appropriate insulating layer and conductive film, LIJL)
The field effect transistor structure can be developed.

FIGS. 2(a) to 2(a)) are longitudinal sectional views of a refurbished conductor element shown in the order of steps for explaining another embodiment of the present invention.

First, a gate electrode 305 is formed in the same process as in the first embodiment as shown in FIG. 2 (aJ).

Next, as shown in FIG.
4, and this modified L7t photoresist 304a
The source 306 and drain 3 are doped with an n-type impurity by ion implantation from the perpendicular direction into the silicon substrate using a vi-mask to the extent of arsenic tlocIL.
07 is formed.

Next, as shown in Fig. 2, remove the 7-hole resist as shown in C1 and add 10 cm of arsenic to form the n-type impurity using the ion implantation method.
The doping layer is doped to a concentration of approximately 1IL, and heat treatment is performed for activation to form a source 306a and a drain 307a.

In this embodiment, since the photoresist is deformed without being ion-implanted, it has the advantage that the shape of the photoresist can be controlled better than in the first embodiment.

Ninth, since impurities are also implanted into the gate electrode 305,
Another advantage is that the gate electrode can have a low resistance.

FIG. 3 is a longitudinal sectional view of a third embodiment of the invention. First, as in the second factors (a) and (b), t) phosphorus, which is an n-type impurity, is added by ion implantation using the photoresist 304a' as a mask, which is deformed in the same process as in the second embodiment. The source 3 is doped to a concentration of about 10 (m2).
06 and drain 307″lr are formed.

Next, as shown in FIG. 3, the photoresist is removed and heat treatment for activation and pushing is performed to form a source 306b and a drain 307b.

In this embodiment, phosphorus is used to form the n-type source/drain impurity diffusion regions. Compared to the case of using arsenic, using phosphorus can make the junk gradient gentler and suppress the hot electron effect, but it is also pushed into the channel direction by heat treatment, which is disadvantageous for the short channel effect. Therefore, it has rarely been used when forming source/drain/impurity diffusion regions in self-alignment with conventional gate electrodes.

However, in this embodiment, the starting point of diffusion in the channel direction can be moved away from the gate electrode, making it possible to suppress both the hot electron effect and the short channel effect, thereby creating a field effect transistor with excellent characteristics. can be manufactured.

In addition, depending on the conditions, in the same example, phosphorus t”10
V of about cm! By doping with arsenic to a concentration of about 10 crrL to form double-diffused source/drain gold,
Part 717 mainly uses phosphorus to make the slope gentler and 1. The resistance of the source/drain/impurity diffusion region can be kept low mainly by arsenic, and the amount of pushing in the channel direction can be reduced, so the present invention is effective in this respect as well.

〔Effect of the invention〕

As explained above, the present invention uses a 7T photoresist pattern in one photolithography process when forming a gate electrode to form source/drain impurity diffusion layers at locations away from the gate electrode. A field effect transistor of LtL)L) structure can be manufactured using the method.

In addition, since there is no need to form a gate electrode or etch back, the process can be significantly shortened, and the effects of damage and contamination can be eliminated without etching the silicon base. Therefore, there is an effect that an electric field infant transistor having excellent shape, characteristics, and reliability can be manufactured.

[Brief explanation of drawings]

FIG. 1 (aJ to (dJ is a vertical cross-sectional view of a nine semiconductor device shown in order of process for explaining one embodiment of the present invention, 2nd h t
a+ to (C) are longitudinal cross-sectional views of a refurbished conductor element shown in the order of steps to explain other embodiments of the present invention, and FIG. 3 is a longitudinal cross-sectional view of a friend semiconductor element formed according to the third embodiment of the present invention. figure,
4(a) to tdJ are longitudinal cross-sectional views of a refurbished conductor cable shown in step Ill for the purpose of explaining an example of a conventional method for manufacturing a semiconductor device. 101.201,301...P-type silicon substrate, 10
2.202,302...field oxide layer, 103.
203,303...Gate oxide film, 104°304.
... Photoresist, 104a, 304a... Deformed photoresist, 105, 204, 305... Gate electrode (polycrystalline silicon, 106, 106a. 106b, 205. 205a, 306. 306a, 30
6b...source, 107, 107a, 107b, 2
06. 206a, 307.307a, 307b...-Drain. Agent: Patent Attorney Susumu Uchihara, Figure 2, Figure 3, 4 Sen

Claims (5)

[Claims] (1) In a method of manufacturing a semiconductor device using an insulated gate field effect transistor including the step of forming source/drain diffusion regions of an opposite conductivity type on a semiconductor substrate of one conductivity type, the source/drain diffusion When forming the region, a step of forming a gate electrode using a photoresist as a mask, and an orthogonal projection image of an end of the photoresist on the gate electrode onto the semiconductor substrate surrounds an end of the gate electrode;
and forming a first source/drain region by introducing impurities of opposite conductivity type by ion implantation using the deformed photoresist as a mask. A method for manufacturing a semiconductor device, characterized in that: (2) As a step before or after the step of forming the first source/drain impurity diffusion region, impurities of the opposite conductivity type are introduced by ion implantation using the gate electrode as a mask to form the second source/drain impurity diffusion region. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a doubly diffused impurity region. (3) The maximum impurity concentration of the first source/drain impurity diffusion region is 10^2^0cm^-^3 or more, and the maximum impurity concentration of the second source/drain impurity diffusion region is 10^
A method for manufacturing a semiconductor device according to claim (1) or (2), characterized in that the thickness is 1^9 cm^-^3 or less. (4) Using P type as the conductivity type of the semiconductor substrate, using arsenic as the impurity in the first source/drain impurity diffusion region,
Claim (1) characterized in that phosphorus is used as an impurity in the second source/drain impurity diffusion region.
The method for manufacturing a semiconductor device according to item (2) or item (2). (5) The conductivity type of the semiconductor substrate is n-type, boron is used as an impurity in the first source/drain impurity diffusion region, and boron is used as an impurity in the second source/drain impurity diffusion region. Claim No. (
A method for manufacturing a semiconductor device according to item 1), item (2), or item (3).