JPH0945921A - Method for manufacturing thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly achieve an LDD structure or an offset structure with an improved reproducibility without utilizing side etching by performing heat treatment of a resist film used for the patterning of a gate electrode and utilizing a process for enlarging a mask area. SOLUTION: A silicon oxide film 2 is formed on a glass substrate 1, amorphous silicon film is formed and is subjected to patterning in an island shape and then excimer laser is applied to form an island-shaped polycrystal silicon film 3, and a doped polycrystal silicon film 5A is formed at a substrate temperature of 400 deg.C or 600 deg.C. Then, a photoresist film 6A is subjected to patterning and dry etching to form a gate electrode 7A which crosses the island-shaped polycrystalline silicon film 3 and ion is implanted and then lightly doped regions 9-1A and 2A are formed in self-alignment manner with the gate electrode 7A. Therefore, by heating the photoresist part 6A, reducing viscosity for drooping, and increasing an area to be masked, a thin-film transistor in LDD structure can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT) applied to a large area active matrix liquid crystal display or the like, and particularly to a polycrystalline silicon thin film formed at a relatively low temperature (600 ° C. or lower). The present invention relates to a method of manufacturing a used polysilicon thin film transistor.

[0002]

2. Description of the Related Art A low temperature process polycrystalline silicon TFT is
Since it can achieve a mobility of about 10 to 1000 times that of an amorphous silicon TFT, it is a useful element in high definition, high aperture ratio, drive circuit integration, etc. of liquid crystal display devices. However, in the polycrystalline silicon TFT, many trap levels are localized at the crystal grain boundaries in the polycrystalline silicon thin film, and therefore a large amount of OFF current flows through this trap, especially for pixel switching. When used in a TFT, the data protection characteristic deteriorates, which is a serious problem. Therefore, the structure of the TFT is offset structure or LDD.
A method of suppressing the leak current by using a (Lightly Doped Drain) structure is used.

FIG. 7 (e) shows an LDD structure polycrystalline silicon T.
It is sectional drawing of FT. 1 is a glass substrate, 3 is a polycrystalline silicon film, 7 is a gate electrode, 8-1a and 8-2a are source / drain regions formed on the polycrystalline silicon film 3, 4 is a gate insulating film, 10 is an interlayer insulating film, 11-1 and 11-2 are source / drain electrodes, 9-1 and 9-2 are formed on the polycrystalline silicon film 3, and source / drain regions 8-1 and 8-
The LDD region is a low-concentration region of the same conductivity type as 2. If the LDD region is provided in this way, for example, in the case of an n-channel TFT, even if the gate voltage is negatively biased and the P-type layer is formed on the surface of the polycrystalline silicon thin film, the impurity concentration of the LDD region which is the N-type region is reduced. Since it is low, the width of the energy barrier of the PN junction becomes wide. Therefore, the electric field strength applied to the PN junction is weakened, and the OFF current does not increase.

L of this LDD structure polycrystalline silicon TFT
A manufacturing method capable of forming a DD region and a source / drain region in self-alignment with a gate electrode is disclosed in Japanese Patent Application Laid-Open No. 5-152325.
No. 6,086,045. That is, as shown in FIG. 7A, the SiO ₂ film 2 is formed on the surface of the glass substrate 1,
An island-shaped polycrystalline silicon film 3 is formed, a silicon oxide film 4 is formed as a gate insulating film, and a chromium film 5 having a thickness of 50 to 100 nm is formed. Next, as shown in FIG. 7B, a resist film 6 is formed and the chromium film 5 is wet-etched to form a gate electrode 7. In this case, by performing over-etching, side etching is performed to the inside of about 1 μm from the pattern edge of the resist film 6. next,
After baking at a temperature of 160 ° C., the side-etched portion is covered with a resist as shown in FIG. next,
The first impurity introduction is performed by using the deformed resist film 6a as a mask, and as shown in FIG.
-1, 8-2 are formed. Next, the resist film 6a is removed, and the second impurity is introduced using the gate electrode 7 as a mask. This is to form the LDD regions 9-1 and 9-2 shown in FIG. Next, a SiO ₂ film 10 is deposited as an interlayer insulating film, a contact hole C is opened, and source / drain electrodes 11-1 and 11-2 are formed.

[0005]

The above-mentioned conventional TFTs
The manufacturing method of (1) uses side etching by wet etching (Japanese Patent Laid-Open No. 5-152325 does not describe an offset structure, but it is easy to see that an offset structure can be realized by a similar method).
However, the polycrystalline silicon TFT is used for the purpose of achieving higher definition and higher aperture ratio of the liquid crystal display device, and wet etching is inferior in fine processability to dry etching. Of course, dry etching can also perform side etching, but in the case of a large-area device such as a liquid crystal display device, it is difficult to control the side etching amount uniformly over the entire surface. As a trial, the amount of side etching when CF ₄ gas was used was examined, and the result as shown by the broken line I in FIG. 3 was obtained. When the dimension of the LDD region is set to 1 μm or less, the variation is too large.

Therefore, an object of the present invention is to provide a method of manufacturing a thin film transistor which can realize an LDD structure or an offset structure uniformly and reproducibly without using side etching.

[0007]

A method of manufacturing a thin film transistor having an LDD structure according to a first aspect of the present invention forms an island-shaped semiconductor thin film that selectively covers a surface of a substrate and deposits an insulator thin film on the entire surface. Forming a gate electrode that intersects with the island-shaped semiconductor thin film by depositing a conductive thin film and patterning the conductive thin film with a resist film as a mask; and the island-shaped semiconductor with the resist film as a mask. A first impurity introduction step of introducing impurities into the thin film, a step of deforming the resist film by heating to increase a masking area, and introducing impurities into the island-shaped semiconductor thin film using the deformed resist film as a mask. And a second impurity step of

According to a second method of manufacturing a thin film transistor having an LDD structure of the present invention, an island-shaped semiconductor thin film that selectively covers the surface of a substrate is formed, an insulator thin film is deposited on the entire surface, and a conductive thin film is deposited. Then, a step of forming a gate electrode that intersects with the island-shaped semiconductor thin film by patterning the conductive thin film using the resist film as a mask, and a step of expanding the masking area by deforming the resist film by heating, A first impurity introducing step of introducing impurities into the island-shaped semiconductor thin film using the deformed resist film as a mask; and introducing impurities into the island-shaped semiconductor thin film using the gate electrode as a mask after removing the resist film And a second impurity introducing step.

A third method of manufacturing a thin film transistor having an offset structure of the present invention comprises forming an island-shaped semiconductor thin film that selectively covers the surface of a substrate, depositing an insulator thin film on the entire surface, and depositing a conductive thin film. A step of forming a gate electrode that intersects the island-shaped semiconductor thin film by patterning the conductive thin film using the resist film as a mask; and a step of deforming the resist film by heating to increase the masking area. And a step of introducing impurities into the island-shaped semiconductor thin film using the deformed resist film as a mask.

In these cases, the substrate can be an insulating substrate, the semiconductor thin film can be a polycrystalline silicon thin film, and the introduction of impurities can be performed by an ion implantation method.

The LDD region or the offset region is determined by the enlarged dimension of the resist film, and hence the heating condition of the resist film.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are sectional views in order of steps for explaining the first embodiment of the present invention, and FIG. 2 is a plan view corresponding to FIG. 1 (d). First, as shown in FIG. 1A, a silicon oxide film 2 serving as a barrier for impurity diffusion from the glass substrate 1 is formed on the glass substrate 1 at a substrate temperature of 400 ° C. by the LPCVD method. Subsequently, an amorphous silicon film having a thickness of 75 nm to be an active layer is formed by the LPCVD method at a substrate temperature of 560 ° C. Next, the amorphous silicon film is patterned into an island shape (island shape),
Then, an excimer laser (for example, Xe) is formed on the amorphous silicon film.
Cl laser) is irradiated three times with an irradiation intensity of 424 mJ / cm ² to polycrystallize. Thus, the formation of the island-shaped polycrystalline silicon film 3 is completed. Next, a silicon oxide film 4 serving as a gate insulating film is formed by a LPCVD method at a substrate temperature of 400 ° C., and subsequently a doped polycrystalline silicon film 5A is formed by a LPCVD method at a substrate temperature of 600 ° C. A photoresist film having a thickness of 3 μm is formed on the doped polycrystalline silicon film 5A by a coating method, and a photoresist film 6A having a gate electrode shape is formed by a photolithography process using an exposure machine, as shown in FIG. 1B. Then, the doped polycrystalline silicon film 5A is dry-etched using this as a mask to form a gate electrode 7A intersecting the island-shaped polycrystalline silicon film 3. After the dry etching, with the photoresist film 6A remaining on the gate electrode 7A, P ⁺ ions were implanted by ion implantation under the conditions of 2 × 10 ¹³ cm ^-2 and an acceleration voltage of 90 keV, as shown in FIG. 1 (c). like,
The low-concentration implantation regions 91-1A and 9-2A are formed on the gate electrode 7A.
Form in a self-aligning manner with. Then, the photoresist film 6A
By heating, the viscosity of the photoresist is lowered and the masked area is enlarged by dripping. At this time, by increasing the heating temperature to 200 ° C. and the heating time to 1H, it is possible to obtain a resist width expansion of about 0.5 μm per side. continue,
By using the photoresist film 6Aa having the enlarged mask area as a mask, P ⁺ ions are 2 × 10 ¹⁵ cm 2 by the ion implantation method.
^-2 , high-concentration impurity implantation is performed by implanting under an accelerating voltage of 70 keV. As shown in FIGS. 1 (d) and 2, high-concentration implantation regions and low-concentration implantation regions 9-1A, 9-2
Form A in a self-aligned manner. Next, when annealing is performed, the low concentration implantation region and the high concentration implantation region are respectively LDDed.
Regions 9-1A and 9-2A, source / drain regions 8-1
A, 8-2A. Next, the photoresist film 6Aa is removed, and the silicon oxide film 10 serving as an interlayer insulating film is formed by LPC.
The substrate 11 is formed by the VD method at a substrate temperature of 400 ° C. Then, the contact hole C in the source / drain region is opened to form an Al film, and the Al film is patterned to form the wiring 11-1,
11-2 is formed, and a thin film transistor having an LDD structure (gate length 6 μm, gate width 6 μm) is manufactured.

FIG. 3 shows an example of the variation in the resist width expansion amount within the substrate in the embodiment. It can be seen that the uniformity is good over the entire surface of the substrate. However, the photoresist used was OFPR800 manufactured by Tokyo Ohka Co., Ltd. The temperature distribution of the electric furnace used for the heat treatment is ± 5 ° C within the substrate plane.
Met. The reproducibility was also good.

FIG. 4 shows an example of drain current-gate voltage characteristics of the polycrystalline silicon TFT according to this embodiment.
The drain voltage with respect to the source is 12V. Even if the gate voltage is negative, the drain current (leakage current) is small,
A TFT having a good LDD structure was obtained.

Next, a second embodiment of the present invention will be described. The process up to the patterning process of the doped polycrystalline silicon film is the same as that of the first embodiment. FIG. 5 (a)
The doped polycrystalline silicon film is formed on the gate electrode 7 as shown in FIG.
The photoresist film used for patterning a is heated to drip to increase the masked area. Then, high-concentration impurity implantation is performed by an ion implantation method using the photoresist film 6B having an enlarged mask area as a mask, and as shown in FIG.
B, 8-2B are formed. After removing the photoresist film 6B, a low concentration impurity is implanted by the ion implantation method using the gate electrode 7A as a mask to perform a low concentration implantation region (by annealing, LDD regions 9-1B and 9-2B shown in FIG. 5C).
Becomes ) Is formed. The subsequent steps are the same as those in the first embodiment. Finally, a thin film transistor having an LDD structure similar to that according to the first embodiment is manufactured.

Next, a third embodiment of the present invention will be described. Similar to the second embodiment, FIG.
A photoresist film 6C is formed as shown in FIG.
As shown in (b), the high-concentration implantation regions 8-1C, 8-2
Form C. The only difference from the second embodiment is that the subsequent low concentration impurity implantation is not performed. Subsequent steps are the same as those in the first and second embodiments, so that a thin film transistor having an offset structure is finally manufactured as shown in FIG. 6C.

Although the example in which the impurities are introduced by the ion implantation method has been described above, it is also possible to use the ion shower doping method or the plasma doping method. Further, as is clear from the above description, the present invention can be applied to the case of manufacturing a thin film transistor using the dry etching technique.

[0019]

As described above, according to the present invention, a thin film transistor having an LDD structure or an offset structure can be realized by utilizing the process of increasing the mask area by heat-treating a resist film used for patterning a gate electrode. LD
Since the dimensions of the D region and the offset region are determined by the heat treatment conditions, they can be uniformly and precisely controlled. Further, since side etching is not used, it is compatible with a dry etching technique which is advantageous for high definition. Therefore, there is an effect that it can contribute to high definition and high aperture ratio of a liquid crystal display device using a TFT.

[Brief description of drawings]

1A to 1D are cross-sectional views in order of the processes, which are divided into (a) to (d) for describing a first embodiment of the present invention.

FIG. 2 is a plan view corresponding to FIG.
(D) is the XX sectional view taken on the line of FIG.

FIG. 3 is a graph for explaining the first embodiment.

FIG. 4 is a polycrystalline silicon TFT according to the first embodiment.
5 is a graph showing an example of the drain current-gate voltage characteristics of FIG.

5A to 5C are cross-sectional views in order of the processes, which are divided into (a) to (c) for describing a second embodiment of the present invention.

6A to 6C are cross-sectional views in order of the processes, which are divided into (a) to (c) for describing a third embodiment of the present invention.

FIG. 7A to FIG. 7C for explaining a conventional technique.
It is a process order sectional view divided and shown in (e).

[Explanation of symbols]

1 Glass Substrate 2 Silicon Oxide Film 3 Polycrystalline Silicon Film 4 Silicon Oxide Film 5 Chromium Film 5A Doped Polycrystalline Silicon Film 6, 6a, 6A, 6Aa, 6B, 6C Photoresist Film 7, 7A, 7B Gate Electrode 8-1, 8-1B, 8-1C, 8-2, 8-2B, 8-
2C high-concentration implantation region 8-1a, 8-1A, 8-1Ba, 8-1Ca source / drain region 9-1, 9-1Aa, 9-1B, 9-2, 9-2Aa,
9-2B LDD region 9-1A, 9-2A low concentration implantation region 10 silicon oxide film 11-1, 11-2 wiring (source / drain electrode) C contact hole

Claims (5)

[Claims] 1. An island-shaped semiconductor thin film that selectively covers the surface of a substrate is formed, an insulator thin film is deposited on the entire surface, a conductive thin film is deposited, and the conductive thin film is patterned using a resist film as a mask. Thereby forming a gate electrode that intersects with the island-shaped semiconductor thin film, a first impurity introduction step of introducing impurities into the island-shaped semiconductor thin film using the resist film as a mask, and heating the resist film. And a second impurity step of introducing an impurity into the island-shaped semiconductor thin film using the deformed resist film as a mask, and Production method. 2. An island-shaped semiconductor thin film that selectively covers the surface of a substrate is formed, an insulator thin film is deposited on the entire surface, a conductive thin film is deposited, and the conductive thin film is patterned using a resist film as a mask. Forming a gate electrode that intersects with the island-shaped semiconductor thin film by doing so, deforming the resist film by heating to increase the masking area, and using the deformed resist film as a mask A first impurity introducing step of introducing impurities into the thin film; and a second impurity introducing step of removing impurities from the resist film and then introducing impurities into the island-shaped semiconductor thin film using the gate electrode as a mask. LDD
Method of manufacturing thin film transistor having structure. 3. An island-shaped semiconductor thin film that selectively covers the surface of a substrate is formed, an insulator thin film is deposited on the entire surface, a conductive thin film is deposited, and the conductive thin film is patterned using a resist film as a mask. Thereby forming a gate electrode intersecting the island-shaped semiconductor thin film, deforming the resist film by heating to increase the masking area, and using the deformed resist film as a mask And a step of introducing impurities into the semiconductor thin film. 4. The method of manufacturing a thin film transistor according to claim 1, wherein the substrate is an insulating substrate and the semiconductor thin film is a polycrystalline silicon thin film. 5. The method for manufacturing a thin film transistor according to claim 1, 2, 3 or 4, wherein the impurity introduction is performed by an ion implantation method.