KR20000031174A - Production method for thin film transistor substrate of polycrystalline silicon - Google Patents
Production method for thin film transistor substrate of polycrystalline silicon Download PDFInfo
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- KR20000031174A KR20000031174A KR1019980047082A KR19980047082A KR20000031174A KR 20000031174 A KR20000031174 A KR 20000031174A KR 1019980047082 A KR1019980047082 A KR 1019980047082A KR 19980047082 A KR19980047082 A KR 19980047082A KR 20000031174 A KR20000031174 A KR 20000031174A
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- polycrystalline silicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 31
- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 48
- 239000010408 film Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 238000009413 insulation Methods 0.000 claims abstract 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 29
- 239000000463 material Substances 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 2
- 239000012530 fluid Substances 0.000 abstract 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
Description
본 발명은 다결정 규소 박막 트랜지스터 기판의 제조 방법에 관한 것으로서, 특히 다결정 규소층에 오프셋(off-set) 및 LDD(lightly doped drain) 구조를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a polycrystalline silicon thin film transistor substrate, and more particularly, to a method of forming an offset and lightly doped drain (LDD) structure in a polycrystalline silicon layer.
박막 트랜지스터 액정 표시 장치는 박막 트랜지스터, 데이터선 및 게이트선 등이 형성되어 있는 박막 트랜지스터 기판과 컬러 필터 및 투명한 공통 전극 등이 형성되어 있는 기판 사이에 액정 물질이 주입되어 있는 형태의 표시 장치로서, 액정 물질을 변위시키는 소자로서 박막 트랜지스터를 사용하고 있다.The thin film transistor liquid crystal display is a display device in which a liquid crystal material is injected between a thin film transistor substrate on which a thin film transistor, a data line, a gate line, and the like are formed, and a substrate on which a color filter and a transparent common electrode are formed. Thin film transistors are used as elements for displacing materials.
이 박막 트랜지스터의 반도체층은 주로 비정질 또는 다결정 규소를 이용하여 형성한다.The semiconductor layer of this thin film transistor is mainly formed using amorphous or polycrystalline silicon.
비정질 규소의 경우, 낮은 온도에서 증착이 가능하고 오프(off) 전류 특성이 뛰어나기는 하지만, 이동도가 1 cm3/V·sec 미만이므로 액정 표시 장치 내의 스위칭(switching)소자를 형성하는데에만 주로 이용되며, 구동 회로는 별도의 아이시(integrated circuit:IC)를 구성하여 주변에 장착한다. 이처럼 모듈 공정의 증가에 따라 공정 비용이 증가한다.Amorphous silicon can be deposited at low temperatures and has excellent off current characteristics, but its mobility is less than 1 cm 3 / V · sec and is mainly used to form switching elements in liquid crystal displays. In addition, the driving circuit forms a separate IC (IC) and is mounted around. As the module process increases, the process cost increases.
이에 비해, 다결정 규소는 비정질 규소보다 이동도가 50cm3/V·sec 이상의 큰 값을 가지기 때문에, 기판 내에 구동 회로를 화소 부분 형성과 동시에 집적할 수 있어서 구동 아이시 재료비나 관련 공정 설비의 비용을 줄일 수 있다. 또한, 비정질 규소를 사용하는 경우보다 5배 이상 소비 전력을 낮출 수 있다.On the other hand, since polycrystalline silicon has a greater mobility of 50 cm 3 / V · sec or more than amorphous silicon, it is possible to integrate a driving circuit in a substrate at the same time as forming a pixel portion, thereby reducing the cost of driving IC materials and related process equipment. Can be reduced. In addition, power consumption can be lowered by five times or more than when using amorphous silicon.
반면, 박막 트랜지스터가 닫히는 순간 전류가 과도하게 누설되는 등의 문제점이 있다.On the other hand, when the thin film transistor is closed, there is a problem such as excessive leakage of current.
오프(off) 전류를 제어하기 위한 방법으로 박막 트랜지스터의 소스 및 드레인 영역의 안쪽에 엷게 도핑된 LDD(lightly doped drain) 영역이나 도핑되지 않은 오프 셋(offset) 영역을 두는 것이 일반적이다.As a method for controlling the off current, it is common to have a lightly doped drain (LDD) region or an undoped offset region inside the source and drain regions of the thin film transistor.
오프셋 영역과 LDD 영역이 모두 형성되어 있는 구조가 오프 전류를 보다 효과적으로 제어할 수 있지만, 공정이 증가하는 단점이 있다.Although the structure in which both the offset region and the LDD region are formed can control the off current more effectively, there is a disadvantage in that the process increases.
본 발명의 과제는 오프셋 및 LDD 영역을 공정을 증가시키지 않고 형성하는 방법을 제공하는 것이다.An object of the present invention is to provide a method of forming the offset and LDD regions without increasing the process.
도 1a 내지 도 1h는 본 발명의 제1 실시예에 따른 다결정 규소 박막 트랜지스터 기판의 제조 방법을 공정 순서에 따라 도시한 단면도이고,1A to 1H are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor substrate according to a first embodiment of the present invention in a process sequence;
도 2a 내지 도 2b는 본 발명의 제2 실시예에 따른 다결정 규소 박막 트랜지스터 기판의 제조 방법의 일부를 공정 순서에 따라 도시한 단면도이다.2A to 2B are cross-sectional views of a part of a method of manufacturing a polysilicon thin film transistor substrate according to a second exemplary embodiment of the present invention, according to a process sequence.
이러한 과제를 해결하기 위해서 본 발명의 실시예에 따른 다결정 규소 박막 트랜지스터 기판의 제조 방법에서는 계단 모양의 감광막 패턴을 형성하고, 그 하부에 놓인 게이트 이중 금속막 및 게이트 절연층을 건식 식각 한다. 감광막 패턴과 유사하게, 게이트 절연층의 형태는 두께가 다른 계단 모양으로 패터닝되며, 이 계단 모양의 게이트 절연 패턴을 마스크로 이온을 주입하여 다결정 규소층에 소스 및 드레인 영역과 LDD 영역을 동시에 형성한다. 이후, 두 층의 게이트 금속막 중 상부막을 습식 식각으로 제거함과 동시에 하부막을 언더컷 시켜 오프셋 구조를 형성한다.In order to solve this problem, in the method of manufacturing a polysilicon thin film transistor substrate according to an embodiment of the present invention, a step-shaped photosensitive film pattern is formed, and the gate double metal film and the gate insulating layer disposed under the dry etching are performed. Similar to the photoresist pattern, the gate insulating layer is patterned in a step shape having a different thickness, and ions are implanted using the stepped gate insulating pattern as a mask to simultaneously form source and drain regions and LDD regions in the polysilicon layer. . Thereafter, the top layer of the gate metal layers of the two layers is removed by wet etching, and the bottom layer is undercut to form an offset structure.
이처럼, 일회의 공정으로 소스 및 드레인 영역과 LDD 영역을 형성하며, 별도의 공정을 추가하지 않고 오프셋 구조를 형성하기 때문에 공정이 단순화된다.As such, the process is simplified because the source and drain regions and the LDD region are formed in one process, and the offset structure is formed without adding a separate process.
소스 및 드레인 영역 상부에 잔류하는 게이트 절연 패턴은 이온 도핑 후에 건식 식각으로 제거하거나, 층간 절연막을 형성한 다음 소스 및 드레인 영역을 드러내는 접촉구를 형성하는 단계에서 동시에 제거할 수 있다.The gate insulating pattern remaining on the source and drain regions may be removed by dry etching after ion doping, or may be simultaneously removed in the step of forming an interlayer insulating layer and then forming a contact hole exposing the source and drain regions.
게이트 금속막의 하부막은 몰리브덴 또는 몰리브덴 합금으로 형성하며, 상부막은 하부막의 두께가 감소되는 것을 막기 위해 ITO로 500Å 이하의 두께로 형성하는 것이 바람직하다.The lower film of the gate metal film is formed of molybdenum or molybdenum alloy, and the upper film is preferably formed with a thickness of 500 kPa or less with ITO to prevent the thickness of the lower film from decreasing.
계단 모양의 감광막 패턴은 격자 패턴을 가지는 마스크를 이용하여 감광막에 노출되는 빛의 양을 조절함으로써 형성할 수 있다.The stepped photoresist pattern may be formed by adjusting the amount of light exposed to the photoresist using a mask having a lattice pattern.
그러면, 첨부한 도면을 참고로 본 발명의 실시예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.
도 1a 내지 도 1h는 본 발명의 제1 실시예에 따른 다결정 규소 박막 트랜지스터 기판의 제조 방법을 공정 순서에 따라 도시한 단면도이다.1A to 1H are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor substrate according to a first embodiment of the present invention in a process sequence.
먼저, 도 1a에 도시한 바와 같이, 절연 기판(1) 위에 500∼1,000Å 두께의 비정질 실리콘을 저압 화학 기상 증착(low pressure chemical vapor deposition:LPCVD) 방식으로 증착한 다음, 결정화시켜 다결정 규소층(1)을 형성한다.First, as shown in FIG. 1A, 500 to 1,000 Å thick amorphous silicon is deposited on the insulating substrate 1 by low pressure chemical vapor deposition (LPCVD), and then crystallized to form a polycrystalline silicon layer ( To form 1).
도 1b에 도시한 바와 같이, 산화 규소(SiOx) 또는 질화 규소(SiNx) 물질을 플라스마 확장 화학 기상 증착(plasma enhanced chemical vapor deposition : PECVD) 방식으로 증착하여 1,000∼3,000Å 두께의 게이트 절연층(3)을 형성하고, 그 위에 연속하여 게이트 전극 및 배선 형성을 위한 제1 금속층(4)과 제2 금속층(5)을 스퍼터링(Sputturing) 방식으로 증착한다. 제1 금속층(4)은 몰리브덴(Mo), 몰리브덴 텅스텐(MoW), 몰리브덴 티타늄(MoTi) 등과 같은 몰리브덴(Mo) 계열의 금속으로 2,000∼3,000Å, 바람직하게는 3,000Å 이상의 두께로 형성하며, 제2 금속층(5)은 후 공정인 건식 식각이나 습식 식각시 게이트 전극 등의 두께가 감소되는 것을 최소화하기 위해 500Å 두께 이하의 ITO 막으로 형성한다.As illustrated in FIG. 1B, a gate insulating layer having a thickness of 1,000 to 3,000 Å is deposited by depositing silicon oxide (SiOx) or silicon nitride (SiNx) material by plasma enhanced chemical vapor deposition (PECVD). ), And the first metal layer 4 and the second metal layer 5 for forming gate electrodes and wirings are successively deposited thereon by sputtering. The first metal layer 4 is formed of a molybdenum (Mo) -based metal such as molybdenum (Mo), molybdenum tungsten (MoW), molybdenum titanium (MoTi), and the like, and has a thickness of 2,000 to 3,000 kPa, preferably 3,000 kPa or more. The second metal layer 5 is formed of an ITO film having a thickness of 500 kPa or less in order to minimize the reduction of the thickness of the gate electrode during dry etching or wet etching.
다음, 도 1c에 도시한 바와 같이, 제2 금속층(5) 위에 감광 물질을 도포하고 노광 및 현상 공정을 통해 게이트 전극용 감광막 패턴(6)을 형성한다. 이때, 사진 공정은 가장자리 부근(A)에 다수의 격자 패턴(73)을 가지는 마스크(71)를 이용하여 실시하는데, 마스크(71)의 가운데 부분(72)을 통해서는 빛이 투과되지 않고, 격자 패턴(73)을 통해서는 빛이 일부 투과되므로, 감광막 패턴(6)의 중간 부분(61)보다 가장 자리 부분(62)의 두께가 얇게 형성된 계단 모양을 가진다.Next, as shown in FIG. 1C, a photosensitive material is coated on the second metal layer 5, and a photosensitive film pattern 6 for a gate electrode is formed through an exposure and development process. At this time, the photographing process is performed using a mask 71 having a plurality of grating patterns 73 near the edge A. Light is not transmitted through the center portion 72 of the mask 71, and the grating Since the light is partially transmitted through the pattern 73, the edge portion 62 has a stepped shape that is thinner than the middle portion 61 of the photosensitive film pattern 6.
다음, 도 1d에 도시한 바와 같이, 건식 식각 방식으로 감광막(6)의 두께가 얇은 가장자리 부근(61), ITO 제2 금속층(5), 제1 금속층(4) 및 게이트 절연층(3)을 연속으로 식각하여, 제2 금속 패턴(51) 및 게이트 전극인 제1 금속 패턴(41)을 형성한다. 제2 금속 패턴(51)과 제1 금속 패턴(41)은 동일한 경계를 가지도록 형성되거나, 제1 금속 패턴(41)이 제2 금속 패턴(51)에 대해 언더 컷 되거나, 게이트 절연층(3)의 일부가 제2 금속 패턴(51)에 대해 언더 컷되는 구조로 형성된다.Next, as shown in FIG. 1D, the photoresist film 6 has a thin edge vicinity 61, the ITO second metal layer 5, the first metal layer 4, and the gate insulating layer 3 by dry etching. Etching is performed continuously to form the second metal pattern 51 and the first metal pattern 41 serving as the gate electrode. The second metal pattern 51 and the first metal pattern 41 are formed to have the same boundary, the first metal pattern 41 is undercut with respect to the second metal pattern 51, or the gate insulating layer 3 is formed. A part of) is formed in a structure that is undercut with respect to the second metal pattern 51.
이 단계에서, 게이트 절연층(3)은 앞선 감광막 패턴(6)과 마찬가지로 계단 모양으로 식각된다. 즉, 게이트 절연층(3)의 두께는 제1 금속 패턴(41) 하부에 놓인 제1 부분(313), 감광막 패턴(6)의 가장자리 부분(62) 하부에 놓인 제2 부분(312), 감광막 패턴(6) 바깥쪽에 위치한 제3 부분(311)의 순서로 줄어든다. 이때, 다결정 규소층(2)이 손상되지 않도록, 제3 부분(311)의 게이트 절연층(31)을 완전히 제거하지 않고 500∼1,000Å 정도의 두께가 남도록 식각을 실시한다.In this step, the gate insulating layer 3 is etched stepwise like the photosensitive film pattern 6 described above. That is, the thickness of the gate insulating layer 3 may include a first portion 313 under the first metal pattern 41, a second portion 312 under the edge portion 62 of the photoresist pattern 6, and a photoresist layer. It is reduced in the order of the third part 311 located outside the pattern 6. At this time, in order not to damage the polysilicon layer 2, etching is performed so that a thickness of about 500 to 1,000 kPa remains without completely removing the gate insulating layer 31 of the third portion 311.
도 1e에 도시한 바와 같이, 감광막 패턴(61)을 제거한 후, 이온을 도핑한다. 게이트 절연층(31)의 제2 부분(312)은 두께가 제3 부분(311)에 비해 상대적으로 두껍기 때문에, 제2 부분(312) 하부의 다결정 규소층(2)으로 투과되는 이온의 양이 제3 부분(311) 하부의 다결정 규소층(2)보다 적다. 따라서, 1회의 이온 도핑 공정을 통해서, 제2 부분(312)과 제3 부분(311) 하부에 놓인 다결정 규소층(2)에 각각 엷게 이온 도핑된 LDD 영역(212)과 소스 및 드레인 영역(213, 214)이 형성된다. 이때, 게이트 절연층(31)의 제1 부분(313) 하부의 다결정 규소층(2)은 도핑되지 않은 채널 영역(211)이 된다.As shown in FIG. 1E, after the photosensitive film pattern 61 is removed, ions are doped. Since the second portion 312 of the gate insulating layer 31 is relatively thicker than the third portion 311, the amount of ions transmitted to the polycrystalline silicon layer 2 under the second portion 312 is increased. Less than the polycrystalline silicon layer 2 under the third portion 311. Therefore, the LDD region 212 and the source and drain regions 213 thinly ion-doped to the polycrystalline silicon layer 2 underlying the second portion 312 and the third portion 311 through one ion doping process. 214 is formed. In this case, the polysilicon layer 2 under the first portion 313 of the gate insulating layer 31 becomes the undoped channel region 211.
다음, 도 1f에 도시한 바와 같이, 소스 및 드레인 영역(213, 214)과 LDD 영역(212) 위에 남아있는 게이트 절연층(311, 312)을 건식 식각으로 제거하여 고립 게이트 절연층(313)을 형성한다.Next, as shown in FIG. 1F, the gate insulating layers 311 and 312 remaining on the source and drain regions 213 and 214 and the LDD region 212 are removed by dry etching to remove the isolation gate insulating layer 313. Form.
도 1g에 도시한 바와 같이, 왕수를 기본으로 하는 ITO 식각액으로 제2 금속 패턴(51)을 전면 식각하여 제거한다. 이 단계에서, ITO 식각액에서 다소 식각되는 몰리브덴(Mo) 계열의 제1 금속 패턴(41)의 측면이 동시에 식각되어, 최종적으로 선폭이 감소된 게이트 전극(42)이 형성되며, 게이트 전극(42)과 게이트 절연층(313) 사이의 언더 컷 구조가 제거된다. 따라서, 채널 영역(211)의 바깥쪽에 오프셋 영역(215)이 자연적으로 형성된다.As shown in FIG. 1G, the second metal pattern 51 is completely etched and removed with an ITO etchant based on aqua regia. In this step, the side surface of the molybdenum (Mo) -based first metal pattern 41, which is somewhat etched in the ITO etchant, is simultaneously etched to form a gate electrode 42 having a reduced line width. And the under cut structure between the gate insulating layer 313 is removed. Thus, an offset region 215 is naturally formed outside the channel region 211.
도 1h에서와 같이, 층간 절연층(8)을 증착하고, 소스 및 드레인 영역(213, 214)을 드러내는 접촉구(C1, C2)를 형성한 다음, 접촉구(C1, C2)를 통해 소스 및 드레인 영역(C1, C2)과 접촉하는 소스 및 드레인 전극(91, 92)을 형성한다.As shown in FIG. 1H, the interlayer insulating layer 8 is deposited, and the contacts C1 and C2 are formed to expose the source and drain regions 213 and 214, and then the source and the through holes C1 and C2. Source and drain electrodes 91 and 92 in contact with the drain regions C1 and C2 are formed.
이처럼, 본 발명의 제1 실시예에 따른 다결정 규소 박막 트랜지스터 액정 표시 장치의 제조 방법에서는 1회의 이온 주입 공정만으로 LDD 영역(212)과 소스 및 드레인 영역(213, 214)을 동시에 형성하며, 제2 금속 패턴(51)을 제거하는 공정에서 오프셋 영역(212)이 자연적으로 형성되기 때문에, 전체적인 공정이 줄어든다. 특히, LDD 영역(212)과 오프셋 영역(212)을 모두 가지므로 누설 전류를 낮추는 효과도 뛰어나다.As described above, in the method of manufacturing the polysilicon thin film transistor liquid crystal display according to the first embodiment of the present invention, the LDD region 212 and the source and drain regions 213 and 214 are simultaneously formed by only one ion implantation process, and the second Since the offset region 212 is naturally formed in the process of removing the metal pattern 51, the overall process is reduced. In particular, since both the LDD region 212 and the offset region 212 is included, the effect of lowering the leakage current is also excellent.
다음, 도 2a 내지 도 2b를 참고로 하여 본 발명의 제2 실시예에 따른 다결정 규소 박막 트랜지스터 기판의 제조 방법을 설명한다.Next, a method of manufacturing a polysilicon thin film transistor substrate according to a second embodiment of the present invention will be described with reference to FIGS. 2A to 2B.
도 2a 내지 도 2b는 본 발명의 제2 실시예에 따른 박막 트랜지스터 기판의 제조 방법을 공정 순서에 따라 차례로 도시한 단면도이다.2A to 2B are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention, in the order of a process.
도 1a 내지 도 1e에서와 동일한 방법으로, 제2 금속 패턴(51), 제2 금속 패턴(41), 계단 모양의 게이트 절연층(331, 332, 333), 소스 및 드레인 영역(213, 214), LDD 영역(212) 및 채널 영역(211)을 형성한다.In the same manner as in FIGS. 1A-1E, the second metal pattern 51, the second metal pattern 41, the stepped gate insulating layers 331, 332, and 333, the source and drain regions 213 and 214. LDD region 212 and channel region 211 are formed.
다음, 도 2a에 도시한 바와 같이, 소스 및 드레인 영역(213, 214) 및 LDD 영역(212) 상부에 잔류하는 게이트 절연층(331, 332)을 제거하는 단계를 거치지 않고, 바로 제2 금속 패턴(41)을 제거하는 단계를 실시한다. 앞선 실시예에서와 마찬가지로, 제1 금속 패턴(41)의 측면이 부분적으로 식각되어 선폭이 줄어든 게이트 전극(43)이 형성됨에 따라, 게이트 전극(43)의 가장자리와 LDD 영역(212) 가장자리 사이에 대응되는 다결정 규소층(2)에 도핑되지 않은 오프셋 영역(215)이 형성된다.Next, as shown in FIG. 2A, the second metal pattern is directly removed without removing the gate insulating layers 331 and 332 remaining on the source and drain regions 213 and 214 and the LDD region 212. Step 41 is performed. As in the previous embodiment, as the side surface of the first metal pattern 41 is partially etched to form a gate electrode 43 having a reduced line width, between the edge of the gate electrode 43 and the edge of the LDD region 212. An undoped offset region 215 is formed in the corresponding polycrystalline silicon layer 2.
도 2b에 도시한 바와 같이, 층간 절연층(8)을 증착하고 패터닝하여 소스 및 드레인 영역(213, 214)을 드러내는 접촉구(C1, C2)를 형성한다. 이 과정에서, 소스 및 드레인 영역(213, 214) 상부의 게이트 절연층(331)도 동시에 제거된다.As shown in FIG. 2B, the interlayer insulating layer 8 is deposited and patterned to form contact holes C1 and C2 exposing the source and drain regions 213 and 214. In this process, the gate insulating layer 331 on the source and drain regions 213 and 214 are also simultaneously removed.
다음, 접촉구(C1, C2)를 통해 소스 및 드레인 영역(213, 214)과 접촉하는 소스 및 드레인 전극(91, 92)을 층간 절연층(8) 위에 형성한다.Next, source and drain electrodes 91 and 92 contacting the source and drain regions 213 and 214 through the contact holes C1 and C2 are formed on the interlayer insulating layer 8.
제2 실시예에서는, 도핑된 영역 상부의 게이트 절연층(331)을 별도의 공정이 아닌 접촉구(C1, C2) 형성 과정에서 분리시켜주기 때문에 제1 실시예에서보다 공정이 한 단계 줄어든다.In the second embodiment, since the gate insulating layer 331 on the doped region is separated in the process of forming the contact holes C1 and C2 rather than a separate process, the process is reduced by one step than in the first embodiment.
이상에서와 같이, 본 발명에 따른 박막 트랜지스터 기판의 제조 방법에서는 LDD 영역과 소스 및 드레인 영역을 단일 공정에서 형성하며, 별도의 공정을 추가하지 않고 오프셋 영역을 형성함으로써, 전체 기판의 제조 공정을 단순화할 수 있다.As described above, in the method of manufacturing the thin film transistor substrate according to the present invention, the LDD region, the source and drain regions are formed in a single process, and the offset region is formed without adding a separate process, thereby simplifying the manufacturing process of the entire substrate. can do.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100488063B1 (en) * | 2002-04-15 | 2005-05-06 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and fabrication method thereof |
| KR100542983B1 (en) * | 2002-01-09 | 2006-01-20 | 삼성에스디아이 주식회사 | Method for formming thin film transistor having a lightly doped drain structure and thin film transistor therby |
| KR100693246B1 (en) * | 2000-06-09 | 2007-03-13 | 삼성전자주식회사 | Method of forming top gate type Thin Film Transistor |
| KR100702311B1 (en) * | 2001-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
| KR100856864B1 (en) * | 2001-09-24 | 2008-09-04 | 엘지디스플레이 주식회사 | A fabricating method of Thin Film Transistor for Liquid Crystal Display Device and TFT for LCD thereby |
| KR100878272B1 (en) * | 2002-07-24 | 2009-01-13 | 삼성전자주식회사 | A method for manufacturing a thin film transistor using polysilicon |
| KR101006439B1 (en) * | 2003-11-12 | 2011-01-06 | 삼성전자주식회사 | Method for manufacturing of Thin film transistor array panel |
| CN106935654A (en) * | 2015-12-31 | 2017-07-07 | 三星显示有限公司 | For the thin film transistor (TFT) of display device |
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| JPH0196927A (en) * | 1987-10-08 | 1989-04-14 | Nec Corp | Manufacture of semiconductor device |
| JP2596117B2 (en) * | 1989-03-09 | 1997-04-02 | 富士電機株式会社 | Method for manufacturing semiconductor integrated circuit |
| JP2564725B2 (en) * | 1991-12-24 | 1996-12-18 | 株式会社半導体エネルギー研究所 | Method of manufacturing MOS transistor |
| KR960002691A (en) * | 1994-06-17 | 1996-01-26 | 김주용 | Semiconductor device and manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100693246B1 (en) * | 2000-06-09 | 2007-03-13 | 삼성전자주식회사 | Method of forming top gate type Thin Film Transistor |
| KR100702311B1 (en) * | 2001-06-30 | 2007-03-30 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
| KR100856864B1 (en) * | 2001-09-24 | 2008-09-04 | 엘지디스플레이 주식회사 | A fabricating method of Thin Film Transistor for Liquid Crystal Display Device and TFT for LCD thereby |
| KR100542983B1 (en) * | 2002-01-09 | 2006-01-20 | 삼성에스디아이 주식회사 | Method for formming thin film transistor having a lightly doped drain structure and thin film transistor therby |
| KR100488063B1 (en) * | 2002-04-15 | 2005-05-06 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and fabrication method thereof |
| KR100878272B1 (en) * | 2002-07-24 | 2009-01-13 | 삼성전자주식회사 | A method for manufacturing a thin film transistor using polysilicon |
| KR101006439B1 (en) * | 2003-11-12 | 2011-01-06 | 삼성전자주식회사 | Method for manufacturing of Thin film transistor array panel |
| US7964873B2 (en) | 2003-11-12 | 2011-06-21 | Samsung Electronics Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
| CN106935654A (en) * | 2015-12-31 | 2017-07-07 | 三星显示有限公司 | For the thin film transistor (TFT) of display device |
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