JPH07131027A - Fabrication of thin film semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for fabricating a thin film semiconductor device having LDD structure in which the uniformity is enhanced in the width of LDD region, i.e., the offset width. CONSTITUTION:The method for fabricating a thin film semiconductor device having a lightly doped diffusion layer 19 formed contiguously to the source and drain regions 17, 18, with same conductivity type, which are formed on an insular semiconductor layer 12 formed on an insulating substrate 11 along with a gate insulation film 13, comprises a first etching step for depositing an anti-channeling film 15 on a gate electrode 14' formed on the gate insulating film 13 and machining the anti-channeling film 15 thinner than the gate electrode film 14' while self-aligning. The fabrication method further comprises a step for introducing impurities once from above the gate electrode 14' and the anti- channeling film 15 to form a source electrode 17, a drain electrode 18 and a lightly doped diffusion layer 19 on the insular semiconductor layer 12, and a second etching step for machining the gate electrode 14 to same width as the anti-channeling film 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film semiconductor device having a structure for reducing leakage current, and more particularly, to improving the uniformity of offset width in a thin film semiconductor device having a Lightly Doped Drain (LDD) structure. Regarding how to plan.

[0002]

2. Description of the Related Art When a semiconductor thin film is formed on an insulating substrate and a thin film semiconductor device, particularly a thin film transistor (hereinafter referred to as TFT) circuit, is formed in the semiconductor thin film, the manufacturing process of the TFT is suppressed to 600 ° C. or lower. It is desired that the TFT performance be high mobility and low off current. This is to ensure high drive capability of the drive circuit in the image input / output device using the TFT, and to ensure off characteristics at the time of gate turn-off. Further, when an inexpensive glass substrate is used as the insulating substrate, the process temperature for preventing the occurrence of thermal strain is said to be about 500 ° C. as a limit.

In order to increase the mobility of TFTs, it has been proposed that a poly-Si thin film obtained by melting and crystallizing a-Si by instantaneous heating using a laser is suitable as a semiconductor thin film. (IEEE Electron Devices
Letters vol.EDL-7 no.5, pp.276-278 (1986)). on the other hand,
Regarding the off-current, the poly-Si thin film has many grain boundaries in the film, and the field-emission of carriers through the electrical traps existing at the grain boundaries causes a large off-current, which is a practical problem. It is known that an LDD structure having a low concentration diffusion region between a source region, a drain region and a gate electrode is effective as a countermeasure against this.

For example, a manufacturing method of a thin film semiconductor device having an LDD structure shown in Japanese Patent Publication No. 3-38755 will be described with reference to FIG. An island-shaped semiconductor active layer 32 made of a poly-Si thin film is formed on an insulating substrate 31 such as glass. A gate insulating film 33 made of SiO ₂ or the like is deposited on the semiconductor active layer 32, and impurities such as phosphorus are injected from above the photoresist pattern 34 formed on the gate insulating film 33 to form the source region 35 and the drain region 3
6 is formed. After removing the photoresist pattern 34, a gate electrode 37 made of a poly-Si thin film or the like is formed on the gate insulating film 33, and impurities are introduced again. By making the amount of impurities at this time smaller than when forming the source region 35 and the drain region 36, the semiconductor active layer 32 below the source region 35, the drain region 36 and the gate electrode 37.
LDD regions 38, which are low-concentration regions, are formed therebetween. After that, an interlayer insulating film and a wiring metal are sequentially laminated and patterned to complete a TFT having an LDD structure.

[0005]

According to the above-described manufacturing method, the LDD region 38 is located between the edges of the resist pattern 34 and the gate electrode 37.
The region 38 is determined by the processing accuracy of the photoresist by photolithography when forming the resist pattern 34. However, while the optimum width of the LDD region 38 is about 1.0 to 3.0 μm, the insulating substrate 31
When a glass substrate is used as the substrate, since the alignment accuracy of photolithography is as large as about 2.0 μm due to the expansion and contraction thereof, the width of the LDD region 38 also varies widely, resulting in variations in TFT characteristics.

The present invention has been made in view of the above circumstances, and in a method of manufacturing a thin film semiconductor device having an LDD structure,
It is an object of the present invention to provide a manufacturing method capable of improving the uniformity of the LDD region width, that is, the offset width.

[0007]

In order to solve the problems of the above-mentioned conventional example, the present invention forms an island-shaped semiconductor layer and a gate insulating film on an insulating substrate, and forms a source on the island-shaped semiconductor layer. A method of manufacturing a thin film semiconductor device having a low-concentration diffusion region of the same conductivity type as the source region and the drain region adjacent to the region and the drain region is characterized by including the following steps. As the first etching step,
A channeling prevention film is laminated on the gate electrode formed on the gate insulating film, and the channeling prevention film is processed to be thin in a self-aligned manner with respect to the gate electrode width. In the impurity introducing step, the source electrode, the drain electrode and the low concentration diffusion region are formed in the island-shaped semiconductor layer by introducing the impurity once from above the gate electrode and the channeling prevention film. In the second etching step, the gate electrode is processed to have the same width as the channeling prevention film.

[0008]

According to the method of the present invention, the channeling prevention film is processed to be thin in a self-aligned manner with respect to the width of the gate electrode to form a region where the gate electrode is exposed. After that, since impurities are implanted, the impurities are implanted into the island-shaped semiconductor layer through the route through the gate insulating film and the route through the gate insulating film and the exposed gate electrode. The concentration of the impurity implanted into the island-shaped semiconductor layer through the gate insulating film and the gate electrode is lower than the concentration of the impurity implanted into the island-shaped semiconductor layer only through the gate insulating film. The low-concentration diffusion portion in the island-shaped semiconductor layer becomes an LDD region, and its width is defined by the side etching amount of the channeling prevention film, so that it can be made uniform.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the manufacturing process of a thin film semiconductor device according to the method of the present invention will be described with reference to FIGS. Poly-Si on transparent insulating substrate 11
Is deposited and patterned into a desired shape to form the island-shaped semiconductor layer 1
2 is formed (FIG. 1A). SiO ₂ is deposited so as to cover the island-shaped semiconductor layer 12 to form the gate insulating film 13 (FIG. 1B). Subsequently, Mo is deposited and then patterned to form a gate electrode 14 ′ located at the center of the island-shaped semiconductor layer 12. Further, SiNx is deposited to form the insulating layer 1.
5'is formed (FIG. 1 (c)).

A photoresist is applied on the insulating layer 15 ', and the photoresist is patterned by using a backside exposure method to form a resist pattern 16 which is self-aligned with the gate electrode 14'. Next, the insulating layer 15 'is dry-etched using the resist pattern 16 as a mask to form the channeling prevention film 15 so that the width of the channeling prevention film 15 is narrowed in a self-aligned manner with respect to the width of the gate electrode 14'. To process. At this time, the side edge surface of the gate electrode 14 'is exposed by a desired width by controlling the side etching amount by overetching (FIG. 1 (d)).

After removing the resist pattern 16, in order to form the source region 17 and the drain region 18 in the island-shaped semiconductor layer 12, ion implantation of phosphorus or the like is performed from above.
Conditions for ion implantation are P ⁺ , 110 keV, 2 × 1
It was set to 0 ¹⁵ ions / cm ² . At this time, in the portion of the island-shaped semiconductor layer 12 not covered with the gate electrode 14 ′, ions are implanted through the gate insulating layer 13 and the source region 17 is formed.
And a drain region 18 is formed. In the island-shaped semiconductor layer 12 portion covered with the gate electrode 14 ′, the portion not covered with the channel prevention film 15 has low concentration of ions because the ions penetrate through the gate electrode 14 ′ and the gate insulating layer 13 by channeling. LDD is injected into the inside of the source region 17 and the drain region 18 to form a lighter concentration diffusion region than the source region and the drain region.
A region 19 is formed (FIG. 1 (e)).

Next, using the channeling prevention film 15 as a mask, the gate electrode 14 'is patterned again with an HNO ₃ type etchant to form the gate electrode 14 (FIG. 1).
(F)). After that, an interlayer insulating film and a wiring metal are sequentially laminated and patterned to complete a TFT having an LDD structure. Since the surface of the gate electrode 14 after the formation of the gate electrode 14 is covered with the channeling prevention film 15, it is possible to prevent oxidation of the gate electrode surface due to heat or the like in the process, and reduce the contact resistance with the wiring metal. Can be planned.

According to the above manufacturing method, the gate electrode 14 '
Since back surface exposure is used in the step of forming the resist pattern 16 in a self-aligned manner with respect to the gate electrode 1
The position of the end of the resist pattern 16 with respect to the 4'end can be accurately controlled. In addition, the gate electrode 14 '(M
o) When forming the channeling prevention film 15 by patterning the insulating layer 15 ′ made of SiNx formed thereon, C under the condition that the etching selection ratio of SiNx and Mo is high.
If isotropic etching such as DE is performed, the side etching amount can be controlled, and the width of the channeling prevention film 15 is
The width of the gate electrode 14 'can be formed with good uniformity, and as a result, the width of the LDD region 19 can be made uniform.

FIGS. 2A to 2F show another embodiment of the manufacturing process of the thin film semiconductor device according to the method of the present invention. Poly-Si is deposited on the transparent insulating substrate 21 and patterned into a desired shape to form the island-shaped semiconductor layer 22 (FIG. 2A). S to cover the island-shaped semiconductor layer 22
The gate insulating film 23 is formed by depositing iO ₂ (see FIG. 2).
(B)). Subsequently, Mo and SiNx are sequentially deposited to form a gate electrode layer 24 ″ and an insulating layer 25 ′ (see FIG. 2).
(C)) Further, a photoresist is applied on the insulating layer 25 ', and the photoresist is patterned into a desired shape to form a resist pattern 26.

Next, the gate electrode layer 24 "and the insulating layer 25 'are etched using the resist pattern 26 as a mask to form a gate electrode 24' and a channeling prevention film 25. Dry etching is used for this patterning. By setting the conditions so that the etching rate of SiNx is faster than that of Mo, SiNx / M
The side surface of the laminated film having a columnar structure made of o is tapered.
That is, the width of the channeling prevention film 25 is processed so as to be narrow in a self-aligned manner with respect to the width of the gate electrode 24 '. At this time, the inclination of the tapered surface can be controlled by adjusting the etching rate, and the side end surface of the gate electrode 24 'is exposed by a desired width (FIG. 2 (d)).

After removing the resist pattern 26, in order to form the source region 27 and the drain region 28 in the island-shaped semiconductor layer 22, ion implantation of phosphorus or the like is performed from above.
Conditions for ion implantation are P ⁺ , 110 keV, 2 × 1
It was set to 0 ¹⁵ ions / cm ² . At this time, for the portion of the island-shaped semiconductor layer 22 not covered with the gate electrode 24 ′, ions are implanted through the gate insulating layer 23 and the source region 27 is formed.
And a drain region 28 is formed. In addition, of the island-shaped semiconductor layer 22 portion covered with the gate electrode 24 ′, the portion not covered with the channel prevention film 25 (the portion where the tapered surface is exposed) is channeled to the gate electrode 24 ′ and the gate insulating layer. Since the ions penetrate through 23, low-concentration ions are implanted, and LDD regions 29 are formed inside the source region 27 and the drain region 28 as diffusion regions having a lower concentration than the source region and the drain region (FIG. 2E). ).

Next, using the channeling prevention film 25 as a mask, the gate electrode 24 'is re-patterned with an HNO ₃ based etchant to form the gate electrode 24 (FIG. 2).
(F)). After that, an interlayer insulating film and a wiring metal are sequentially laminated and patterned to complete a TFT having an LDD structure. Since the surface of the gate electrode 24 after the formation of the gate electrode 24 is covered with the channeling prevention film 25, oxidation of the gate electrode surface due to heat or the like in the process can be prevented and the contact resistance with the wiring metal can be reduced. Can be planned.

According to the above manufacturing method, the gate electrode layer 2
An insulating layer 25 'made of 4 "(Mo) and SiNx is patterned by dry etching to form a gate electrode 24'.
Also, when forming the channeling prevention film 25, the exposed area of the tapered surface can be controlled by setting the etching rate of SiNx to Mo at a high rate, and the width of the channeling prevention film 25 can be set to the width of the gate electrode 24 '. However, the width of the LDD region 29 can be made uniform as a result.

According to the above-mentioned embodiments, the LDD region 1
The exposed portion of the gate electrode 14 ′ (the tapered surface of the gate electrode 24 ′) corresponding to the width of 9 (29) is
Since it is formed in a self-aligned thin manner with respect to (24 '), the width of the exposed portion can be made uniform, and as a result, the width of the LDD region 19 (29) can be made uniform. In addition, the source region 17 (27) and the drain region 18 (2) are formed by one-time impurity implantation without providing an impurity implantation process for forming the LDD region 19 (29).
8) and the LDD region 19 (29) can be formed at the same time, and the manufacturing process can be simplified and the cost can be reduced as compared with the conventional example.

[0020]

According to the method of the present invention, the channeling prevention film is processed by etching so as to be thinned in a self-aligned manner with respect to the width of the gate electrode to form a region in which the gate electrode is exposed, and thereafter, the impurities are removed. Since the implantation is performed, the region where the gate electrode is exposed corresponds to the LDD region (low concentration diffusion region) width. Therefore, since the LDD width is defined by the side etching amount of the channel prevention film, the width of the LDD region can be made uniform without being affected by the alignment accuracy, and the characteristics of the thin film semiconductor device can be made uniform.

Further, since the source region, the drain region and the LDD region can be formed by implanting impurities once, the manufacturing process can be simplified. Furthermore,
Since the surface of the gate electrode is covered with the anti-channeling film, the oxidation of the surface of the gate electrode can be prevented in the subsequent process.

[Brief description of drawings]

1 (a) to (f) show T according to the method of the present invention.
It is a section explanatory view showing an example of a manufacturing process of FT.

2 (a) to (f) show T according to the method of the present invention.
It is sectional explanatory drawing which shows the other Example of the manufacturing process of FT.

3A to 3E are TFs according to a conventional method.
It is a section explanatory view showing a manufacturing process of T.

[Explanation of symbols]

11 ... Insulating substrate, 12 ... Island semiconductor layer, 13 ... Gate insulating film, 14 ... Gate electrode, 15 ... Channeling prevention film, 16 ... Resist pattern, 17 ... Source region, 18 ... Drain region, 19 ... LDD region ( Low concentration diffusion region), 21 ... Insulating substrate, 22 ... Island semiconductor layer, 23 ... Gate insulating film, 24 ... Gate electrode,
25 ... Channeling prevention film, 26 ... Resist pattern, 27 ... Source region, 28 ... Drain region, 2
9 ... LDD region (low concentration diffusion region)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/306 H01L 21/302 P

Claims (1)

[Claims] 1. An island-shaped semiconductor layer and a gate insulating film are formed on an insulating substrate, adjacent to a source region and a drain region formed in the island-shaped semiconductor layer, and having the same conductivity as the source region and the drain region. In a method of manufacturing a thin film semiconductor device having a low-concentration diffusion region, a channeling prevention film is laminated on a gate electrode formed on a gate insulating film, and the channeling prevention film is self-aligned with the gate electrode width. The first to make it thinner
And an impurity introduction step of forming a source electrode, a drain electrode, and a low-concentration diffusion region in the island-shaped semiconductor layer by once introducing impurities from above the gate electrode and the channeling prevention film. A second etching step of processing the gate electrode to have a width, and a method of manufacturing a thin film semiconductor device.