KR100348314B1 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
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- KR100348314B1 KR100348314B1 KR1020000056208A KR20000056208A KR100348314B1 KR 100348314 B1 KR100348314 B1 KR 100348314B1 KR 1020000056208 A KR1020000056208 A KR 1020000056208A KR 20000056208 A KR20000056208 A KR 20000056208A KR 100348314 B1 KR100348314 B1 KR 100348314B1
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- insulating film
- groove
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- gate electrode
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052710 silicon Inorganic materials 0.000 description 17
- 239000010703 silicon Substances 0.000 description 17
- 150000004767 nitrides Chemical class 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
Abstract
별도의 장비를 이용하지 않고 채널영역보다 높게 소오스/드레인영역을 형성하므로써 공정을 단순화시킴과 동시에 숏채널효과와 소자 효율을 향상시키기에 알맞은 반도체소자 및 그의 제조방법을 제공하기 위한 것으로, 이와 같은 목적을 달성하기 위한 반도체소자는 활성영역과 격리영역이 정의된 반도체기판에 있어서, 격리영역에 형성된 격리절연막과, 활성영역의 중앙부분에 형성된 홈과, 상기 홈의 표면에 형성된 게이트절연막과, 상기 홈의 중앙부분을 따라 일라인 방향으로 형성된 게이트전극과, 상기 게이트전극 측면에 형성된 측벽스페이서와, 상기 홈 양측의 상기 반도체기판내에 형성된 불순물영역과, 상기 게이트전극과 상기 불순물영역상에 형성된 실리사이드층을 포함하여 구성됨을 특징으로 한다.It is to provide a semiconductor device and a method for manufacturing the same, which are suitable for improving the short channel effect and device efficiency while simplifying the process by forming a source / drain region higher than a channel region without using a separate device. A semiconductor device for achieving the purpose of the present invention is a semiconductor substrate in which an active region and an isolation region are defined, an isolation insulating film formed in an isolation region, a groove formed in a central portion of the active region, a gate insulating film formed on a surface of the groove, and the groove. A gate electrode formed in one line direction along a central portion of the substrate, sidewall spacers formed on side surfaces of the gate electrode, an impurity region formed in the semiconductor substrate on both sides of the groove, and a silicide layer formed on the gate electrode and the impurity region. Characterized in that configured to include.
Description
본 발명은 반도체소자에 대한 것으로, 특히 채널영역보다 높게 소오스/드레인영역을 형성한 반도체소자 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a source / drain region formed higher than a channel region, and a manufacturing method thereof.
이하, 종래 반도체소자의 제조방법에 대하여 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described.
실리콘기판의 활성영역에 게이트산화막과 게이트전극을 적층형성하고, 게이트전극 양측의 실리콘기판내에 저농도 불순물영역을 형성한 후에 게이트산화막과 게이트전극 양측면에 측벽스페이서를 형성한다.A gate oxide film and a gate electrode are stacked in the active region of the silicon substrate, and a low concentration impurity region is formed in the silicon substrate on both sides of the gate electrode, and then sidewall spacers are formed on both sides of the gate oxide film and the gate electrode.
다음에 선택적 실리콘 에피텍셜 장비를 이용한 선택적 실리콘 에피텍셜 성장공정으로 노출된 저농도 불순물영역의 실리콘기판에 에피층을 형성하여 트랜지스터의 채널영역보다 높은 소오스/드레인영역을 형성한다.Next, an epitaxial layer is formed on the silicon substrate of the low concentration impurity region exposed by the selective silicon epitaxial growth process using the selective silicon epitaxial equipment to form a source / drain region higher than the channel region of the transistor.
이때 에피텍셜 성장공정은 850℃정도의 온도에서 진행한다.At this time, the epitaxial growth process is performed at a temperature of about 850 ℃.
이후에 고농도 불순물이온을 주입하고 열처리하여 정션을 형성한다.Thereafter, a high concentration of impurity ions are injected and heat treated to form a junction.
상기와 같은 종래 반도체소자의 제조방법은 다음과 같은 문제가 있다.The conventional method of manufacturing a semiconductor device as described above has the following problems.
채널영역보다 높게 소오스/드레인영역을 형성하기 위해 별도의 실리콘 에피텍셜 장비를 이용해야 하므로 공정이 복잡해진다.The process is complicated because separate silicon epitaxial equipment must be used to form the source / drain regions higher than the channel region.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 별도의 장비를 이용하지 않고 채널영역보다 높게 소오스/드레인영역을 형성하므로써 공정을 단순화시킴과 동시에 숏채널효과와 소자 효율을 향상시키기에 알맞은 반도체소자 및 그의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, by simplifying the process by forming a source / drain region higher than the channel region without using a separate equipment to improve the short channel effect and device efficiency. It is an object of the present invention to provide a suitable semiconductor device and a method of manufacturing the same.
도 1a 내지 도 1l은 본 발명 반도체소자의 제조방법을 나타낸 공정단면도1A to 1L are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11 : 실리콘기판 12 : 버퍼산화막11 silicon substrate 12 buffer oxide film
13 : 버퍼질화막 14 : 제 1 감광막13 buffer nitride film 14 first photosensitive film
15 : 산화막 16a,16b : 제 1, 제 2 홈15: oxide film 16a, 16b: first and second grooves
17 : 제 2 감광막 18 : 트랜치17: second photosensitive film 18: trench
19 : 절연막 19a,19b : 제 1, 제 2 트랜치 격리막19: insulating film 19a, 19b: 1st, 2nd trench isolation film
20 : 게이트산화막 21 : 폴리실리콘층20 gate oxide film 21 polysilicon layer
22 : 게이트전극 23 : 측벽스페이서22 gate electrode 23 sidewall spacer
24 : 소오스/드레인영역 25 : 살리사이드층24 source / drain region 25 salicide layer
상기와 같은 목적을 달성하기 위한 본 발명 반도체소자는 활성영역과 격리영역이 정의된 반도체기판에 있어서, 격리영역에 형성된 격리절연막과, 활성영역의중앙부분에 형성된 홈과, 상기 홈의 표면에 형성된 게이트절연막과, 상기 홈의 중앙부분을 따라 일라인 방향으로 형성된 게이트전극과, 상기 게이트전극 측면에 형성된 측벽스페이서와, 상기 홈 양측의 상기 반도체기판내에 형성된 불순물영역과, 상기 게이트전극과 상기 불순물영역상에 형성된 실리사이드층을 포함하여 구성됨을 특징으로 한다.In order to achieve the above object, the semiconductor device of the present invention is a semiconductor substrate in which an active region and an isolation region are defined, an isolation insulating film formed in an isolation region, a groove formed in a central portion of the active region, and formed on the surface of the groove. A gate insulating film, a gate electrode formed in one line direction along a center portion of the groove, a sidewall spacer formed on the side of the gate electrode, an impurity region formed in the semiconductor substrate on both sides of the groove, the gate electrode and the impurity region It characterized in that it comprises a silicide layer formed on.
상기와 같은 구성을 갖는 본 발명 반도체소자의 제조방법은 활성영역과 격리영역이 정의된 반도체기판에 있어서, 활성영역의 중앙부분을 제외한 양측 가장자리 상부에 제 1, 제 2 절연막패턴을 형성하는 공정, 상기 제 1, 제 2 절연막패턴을 제외한 활성영역의 중앙부분과 격리영역의 상기 반도체기판에 제 1 절연막을 형성하는 공정, 상기 제 1 절연막을 제거하여 상기 활성영역의 중앙부분과 상기 격리영역의 상기 반도체기판에 제 1, 제 2 홈을 형성하는 공정, 상기 격리영역의 제 2 홈에 트랜치를 형성하는 공정, 상기 트랜치에 격리절연막과 상기 제 1 홈에 제 2 절연막을 형성하는 공정, 상기 제 2, 제 1 절연막패턴을 차례로 제거하는 공정, 상기 제 1 홈의 상기 제 2 절연막을 제거한 후에 상기 제 1 홈의 표면에 게이트절연막을 형성하는 공정, 상기 제 1 홈의 중앙 부분에 일라인 방향으로 게이트전극을 형성하는 공정, 상기 게이트전극의 측면에 측벽스페이서를 형성하는 공정, 상기 제 1 홈의 양측 반도체기판내에 불순물영역을 형성하는 공정, 상기 게이트전극과 상기 불순물영역상부에 살리사이드막을 형성하는 공정을 포함함을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention having the above structure includes the steps of: forming a first and a second insulating film pattern on both side edges of the semiconductor substrate in which the active region and the isolation region are defined, except for the central portion of the active region; Forming a first insulating film on the center portion of the active region excluding the first and second insulating layer patterns and on the semiconductor substrate in the isolation region; removing the first insulating layer to remove the first insulating layer from the center portion of the active region and the isolation region; Forming first and second grooves in the semiconductor substrate, forming a trench in the second groove of the isolation region, forming an isolation insulating film in the trench and a second insulating film in the first groove, and the second And sequentially removing the first insulating film pattern, removing the second insulating film of the first groove, and then forming a gate insulating film on the surface of the first groove. Forming a gate electrode in a one-line direction in a central portion, forming a sidewall spacer on a side surface of the gate electrode, forming an impurity region in the semiconductor substrate on both sides of the first groove, and forming the gate electrode and the impurity region And forming a salicide film thereon.
첨부 도면을 참조하여 본 발명 반도체소자 및 그의 제조방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a semiconductor device of the present invention and a method of manufacturing the same will be described.
도 1a 내지 도 1l은 본 발명 반도체소자의 제조방법을 나타낸 공정단면도이다.1A to 1L are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
먼저 본 발명 반도체소자는 도 1l에 도시한 바와 같이 활성영역과 격리영역이 정의된 실리콘기판(11)의 격리영역에 트랜치(18)(도 1e참조)가 형성되어 있고, 트랜치내에 제 2 트랜치 격리막(19b)이 형성되어 있다.In the semiconductor device of the present invention, as shown in FIG. 1L, a trench 18 (see FIG. 1E) is formed in an isolation region of a silicon substrate 11 in which an active region and an isolation region are defined, and a second trench isolation layer is formed in the trench. 19b is formed.
그리고 활성영역의 중앙부분에 제 1 홈(16a)이 형성되어 있고, 제 1 홈(16a)의 표면에 게이트산화막(20)이 형성되어 있다.The first groove 16a is formed in the center portion of the active region, and the gate oxide film 20 is formed on the surface of the first groove 16a.
이때 제 1, 제 2 홈(16a,16b)은 대략 1000~3000Å의 약 45%의 깊이 즉, 450~1350Å 범위의 깊이를 갖는다.In this case, the first and second grooves 16a and 16b have a depth of about 45% of approximately 1000 to 3000 mm 3, that is, a depth of 450 to 1350 mm 3.
그리고 제 1 홈(16a)의 게이트산화막(20)의 중앙부분에 일라인 방향으로 게이트전극(22)이 형성되어 있고, 상기 게이트전극(22) 측면에 측벽스페이서(23)가 형성되어있다.The gate electrode 22 is formed in the center of the gate oxide film 20 of the first groove 16a in one line direction, and the sidewall spacer 23 is formed on the side of the gate electrode 22.
그리고 상기 제 1 홈(16a) 양측의 상기 실리콘기판(11)내에 소오스/드레인영역(24)이 형성되어 있다.Source / drain regions 24 are formed in the silicon substrate 11 on both sides of the first groove 16a.
그리고 게이트전극(22)과 소오스/드레인영역(24)상에 살리사이드층(25)이 형성되어 있다.The salicide layer 25 is formed on the gate electrode 22 and the source / drain regions 24.
상기와 같은 본 발명의 구조에서 채널영역은 제 1 홈(16a)의 하부에 형성되고, 소오스/드레인영역(24)이 채널영역보다 높게 형성되어 있다.In the structure of the present invention as described above, the channel region is formed under the first groove 16a, and the source / drain region 24 is formed higher than the channel region.
다음에 상기와 같은 구성을 갖는 반도체소자의 제조방법에 대하여 설명한다.Next, the manufacturing method of the semiconductor element which has the above structure is demonstrated.
먼저, 도 1a에 도시한 바와같이 활성영역과 격리영역이 정의된실리콘기판(11)상에 실리콘산화막(SiO2)으로 구성된 버퍼산화막(12)을 증착하고, 버퍼산화막(12)상에 실리콘질화막(Si3N4)으로 구성된 버퍼질화막(13)을 증착한다.First, as shown in FIG. 1A, a buffer oxide film 12 including a silicon oxide film (SiO 2 ) is deposited on a silicon substrate 11 having active and isolation regions defined thereon, and a silicon nitride film on the buffer oxide film 12. A buffer nitride film 13 composed of (Si 3 N 4 ) is deposited.
그리고 도 1b에 도시한 바와 같이 버퍼질화막(13)상에 제 1 감광막(14)을 도포한 후에 노광 및 현상공정으로 활성영역과 격리영역으로 정의된 영역만 제거되도록 제 1 감광막(14)을 선택적으로 패터닝한다.As shown in FIG. 1B, the first photoresist layer 14 is selectively removed to apply only the first photoresist layer 14 to the buffer nitride layer 13 and then to remove only the region defined as the active region and the isolation region. Pattern with.
이후에 패터닝된 제 1 감광막(14)을 마스크로 버퍼질화막(13)을 이방성 식각하여 활성영역과 격리영역상의 버퍼산화막(12)이 노출되도록 한다.Thereafter, the buffer nitride layer 13 is anisotropically etched using the patterned first photoresist layer 14 as a mask so that the buffer oxide layer 12 on the active region and the isolation region is exposed.
다음에 도 1c에 도시한 바와 같이 제 1 감광막(14)을 제거하고 열산화공정으로 활성영역과 격리영역에 산화막(15)을 대략 1000~3000Å의 두께를 갖도록 형성한다. 이때 산화막(15)은 실리콘기판(11)의 표면내에까지 형성되어 있다.Next, as shown in FIG. 1C, the first photosensitive film 14 is removed and an oxide film 15 is formed in the active region and the isolation region to have a thickness of approximately 1000 to 3000 microns in a thermal oxidation process. At this time, the oxide film 15 is formed even within the surface of the silicon substrate 11.
그리고 도 1d에 도시한 바와 같이 성장시킨 산화막(15)을 HF의 케미컬용액을 이용한 습식각으로 전부 제거한다.Then, the oxide film 15 grown as shown in FIG. 1D is completely removed by wet etching using a chemical solution of HF.
이에 따라서 활성영역에는 제 1 홈(16a)이 형성되고, 격리영역에는 제 2 홈(16b)이 형성된다. 이때 제 1, 제 2 홈(16a,16b)은 상기 산화막(15) 두께의 약 45%의 깊이를 갖는다. 즉, 산화막(15)을 형성할 때 실리콘기판(11)은 대략 1000~3000Å의 45%의 깊이만큼 소실되도록 형성한다.Accordingly, the first groove 16a is formed in the active region, and the second groove 16b is formed in the isolation region. In this case, the first and second grooves 16a and 16b have a depth of about 45% of the thickness of the oxide film 15. That is, when the oxide film 15 is formed, the silicon substrate 11 is formed to be lost by a depth of 45% of approximately 1000 to 3000 microns.
상기에서 습식각할 때 버퍼질화막(13)이 마스크 역할을 한 것으로 활성영역과 격리영역을 제외한 영역의 버퍼산화막(12)과 버퍼질화막(13)은 남는다.In the wet etching process, the buffer nitride film 13 serves as a mask, and the buffer oxide film 12 and the buffer nitride film 13 in the regions excluding the active region and the isolation region remain.
이후에 도 1e에 도시한 바와 같이 전면에 제 2 감광막(17)을 도포한 후에 노광 및 현상공정으로 격리영역만 제거되도록 제 2 감광막(17)을 선택적으로 패터닝한다.Thereafter, as shown in FIG. 1E, the second photoresist film 17 is coated on the entire surface, and the second photoresist film 17 is selectively patterned so that only the isolation region is removed by an exposure and development process.
그리고 패터닝된 제 2 감광막(17)을 마스크로 격리영역의 실리콘기판(11)을 일정깊이 예를 들어 약 3500Å의 깊이를 갖도록 식각하여서 트랜치(18)를 형성한다.The trench 18 is formed by etching the silicon substrate 11 in the isolation region using a patterned second photoresist layer 17 as a mask to have a predetermined depth, for example, about 3500 m 3.
이와 같은 공정을 셀로우 트랜치 아이솔레이션(Shallow Trench Isolation)이라고 한다.This process is called shallow trench isolation.
다음에 제 2 감광막(17)을 제거하고, 도 1f에 도시한 바와 같이 트랜치(18)를 포함한 전면에 절연막(19)을 증착한다.Next, the second photosensitive film 17 is removed, and the insulating film 19 is deposited on the entire surface including the trench 18 as shown in FIG. 1F.
이후에 화학적 기계적 연마(Chemical Mechanical Polishing:CMP)공정으로 제 1 홈(16a)과 트랜치(18)를 메우는 제 1, 제 2 격리막(19a,19b)을 형성한다.Subsequently, the first and second separators 19a and 19b filling the first grooves 16a and the trenches 18 are formed by a chemical mechanical polishing (CMP) process.
CMP공정을 함에 의해서 제 1, 제 2 격리막(19a,19b) 사이의 활성영역의 버퍼질화막(13)은 일부만 남게된다.By performing the CMP process, only a part of the buffer nitride film 13 in the active region between the first and second separators 19a and 19b remains.
그리고 도 1h에 도시한 바와 같이 150℃정도의 뜨거운(hot) H3PO4을 이용해서 버퍼질화막(13)을 제거한다.As shown in FIG. 1H, the buffer nitride film 13 is removed using hot H 3 PO 4 of about 150 ° C.
이후에 도면에는 도시되지 않았지만 버퍼산화막(12)를 완전히 제거한 후에 활성영역내에 문턱전압 조절이온을 주입한다.Subsequently, although not shown in the drawing, after the buffer oxide film 12 is completely removed, the threshold voltage control ion is implanted into the active region.
그리고 도 1i에 도시한 바와 같이 활성영역에 게이트산화막(20)과 폴리실리콘층(21)을 차례로 증착한다.As shown in FIG. 1I, the gate oxide film 20 and the polysilicon layer 21 are sequentially deposited in the active region.
다음에 도 1j에 도시한바와 같이 게이트전극(22) 형성 마스크를 이용해서 폴리실리콘층(21)을 식각해서 제 1 홈(16a)의 중앙 부분에 일라인 방향으로 게이트전극(22)를 형성한다.Next, as illustrated in FIG. 1J, the polysilicon layer 21 is etched using the gate electrode 22 forming mask to form the gate electrode 22 in the one-line direction in the center portion of the first groove 16a. .
이때 게이트산화막(20)은 제 1 홈(16a)(도 1d참조)내에만 남는다.At this time, the gate oxide film 20 remains only in the first groove 16a (see FIG. 1D).
이때 게이트전극(22) 하부의 실리콘기판(11)에 위치한 채널영역과 소오스/드레인영역(24)이 형성될 제 1 홈(16a) 양측은 'd'만큼의 단차를 갖는다.At this time, both sides of the channel region disposed on the silicon substrate 11 under the gate electrode 22 and the first groove 16a on which the source / drain region 24 is to be formed have a step equal to 'd'.
그리고 도 1k에 도시한 바와 같이 전면에 절연막을 증착한 후에 에치백공정으로 상기 게이트전극(22) 양측의 제 1 홈(16a)에 LDD 측벽스페이서(23)를 형성한다.As shown in FIG. 1K, the LDD sidewall spacer 23 is formed in the first grooves 16a on both sides of the gate electrode 22 after the insulating film is deposited on the entire surface.
이후에 제 1 홈(16a) 양측의 실리콘기판(11)내에 실리콘기판(11)과 반대 도전형의 불순물영역을 주입하고 열처리하여 소오스/드레인영역(24)을 형성한다.Thereafter, an impurity region of opposite conductivity type to the silicon substrate 11 is injected into the silicon substrate 11 on both sides of the first groove 16a and heat treated to form a source / drain region 24.
다음에 티타늄(Titanium) 또는 코발트와 같은 금속층을 증착한 후 열처리하여 도 1l에 도시한 바와 같이 게이트전극(22)과 소오스/드레인영역(24)상에 살리사이드층(25)을 형성한다.Next, a metal layer such as titanium or cobalt is deposited and then heat-treated to form a salicide layer 25 on the gate electrode 22 and the source / drain regions 24 as shown in FIG.
상기와 같은 본 발명 반도체소자 및 그의 제조방법은 다음과 같은 효과가 있다.The semiconductor device of the present invention as described above and a method of manufacturing the same have the following effects.
첫째, 게이트전극 하부의 채널영역보다 높게 소오스/드레인영역을 형성하기 위해서 별도의 장비를 사용할 필요없이 채널영역에 홈을 형성하여 형성하므로 공정을 단순화시키기에 용이하다.First, it is easy to simplify the process because grooves are formed in the channel region to form a source / drain region higher than the channel region under the gate electrode without using a separate device.
둘째, 소오스/드레인 정션의 깊이가 깊어짐에 따라서 숏채널효과를 개선시킴과 동시에 정션 커패시턴스를 감소시킬 수 있다.Second, as the depth of the source / drain junction deepens, the short channel effect can be improved and the junction capacitance can be reduced.
셋째, 살리사이드층을 형성할 때 소모되는 실리콘기판의 깊이가 정션의 경계보다 멀리 떨어져서 형성되므로 정션 누설전류를 감소시키기에 유리하다.Third, since the depth of the silicon substrate consumed when forming the salicide layer is formed farther than the boundary of the junction, it is advantageous to reduce the junction leakage current.
넷째, 소오스/드레인 영역의 도핑농도를 크게 할 수 있기 때문에 소자의 구동효율을 향상시키기에 유리하다.Fourth, since the doping concentration of the source / drain regions can be increased, it is advantageous to improve the driving efficiency of the device.
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| JPH053210A (en) * | 1991-06-25 | 1993-01-08 | Sharp Corp | Manufacture of semiconductor device |
| JPH0661487A (en) * | 1992-08-05 | 1994-03-04 | Fuji Xerox Co Ltd | Semiconductor device and its manufacture |
| JPH06188259A (en) * | 1992-12-17 | 1994-07-08 | Toshiba Corp | Manufacture of semiconductor device |
| US5599728A (en) * | 1994-04-07 | 1997-02-04 | Regents Of The University Of California | Method of fabricating a self-aligned high speed MOSFET device |
| KR970024283A (en) * | 1995-10-20 | 1997-05-30 | 김광호 | MOS transistor and manufacturing method thereof |
| JPH10173072A (en) * | 1996-12-09 | 1998-06-26 | Sony Corp | Semiconductor device and manufacture thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH053210A (en) * | 1991-06-25 | 1993-01-08 | Sharp Corp | Manufacture of semiconductor device |
| JPH0661487A (en) * | 1992-08-05 | 1994-03-04 | Fuji Xerox Co Ltd | Semiconductor device and its manufacture |
| JPH06188259A (en) * | 1992-12-17 | 1994-07-08 | Toshiba Corp | Manufacture of semiconductor device |
| US5599728A (en) * | 1994-04-07 | 1997-02-04 | Regents Of The University Of California | Method of fabricating a self-aligned high speed MOSFET device |
| KR970024283A (en) * | 1995-10-20 | 1997-05-30 | 김광호 | MOS transistor and manufacturing method thereof |
| JPH10173072A (en) * | 1996-12-09 | 1998-06-26 | Sony Corp | Semiconductor device and manufacture thereof |
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